1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMGenInstrInfo.inc"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/ADT/STLExtras.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
203 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
204 MachineBasicBlock *&FBB,
205 SmallVectorImpl<MachineOperand> &Cond,
206 bool AllowModify) const {
207 // If the block has no terminators, it just falls into the block after it.
208 MachineBasicBlock::iterator I = MBB.end();
209 if (I == MBB.begin())
212 while (I->isDebugValue()) {
213 if (I == MBB.begin())
217 if (!isUnpredicatedTerminator(I))
220 // Get the last instruction in the block.
221 MachineInstr *LastInst = I;
223 // If there is only one terminator instruction, process it.
224 unsigned LastOpc = LastInst->getOpcode();
225 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
226 if (isUncondBranchOpcode(LastOpc)) {
227 TBB = LastInst->getOperand(0).getMBB();
230 if (isCondBranchOpcode(LastOpc)) {
231 // Block ends with fall-through condbranch.
232 TBB = LastInst->getOperand(0).getMBB();
233 Cond.push_back(LastInst->getOperand(1));
234 Cond.push_back(LastInst->getOperand(2));
237 return true; // Can't handle indirect branch.
240 // Get the instruction before it if it is a terminator.
241 MachineInstr *SecondLastInst = I;
242 unsigned SecondLastOpc = SecondLastInst->getOpcode();
244 // If AllowModify is true and the block ends with two or more unconditional
245 // branches, delete all but the first unconditional branch.
246 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
247 while (isUncondBranchOpcode(SecondLastOpc)) {
248 LastInst->eraseFromParent();
249 LastInst = SecondLastInst;
250 LastOpc = LastInst->getOpcode();
251 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
252 // Return now the only terminator is an unconditional branch.
253 TBB = LastInst->getOperand(0).getMBB();
257 SecondLastOpc = SecondLastInst->getOpcode();
262 // If there are three terminators, we don't know what sort of block this is.
263 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
266 // If the block ends with a B and a Bcc, handle it.
267 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
268 TBB = SecondLastInst->getOperand(0).getMBB();
269 Cond.push_back(SecondLastInst->getOperand(1));
270 Cond.push_back(SecondLastInst->getOperand(2));
271 FBB = LastInst->getOperand(0).getMBB();
275 // If the block ends with two unconditional branches, handle it. The second
276 // one is not executed, so remove it.
277 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
278 TBB = SecondLastInst->getOperand(0).getMBB();
281 I->eraseFromParent();
285 // ...likewise if it ends with a branch table followed by an unconditional
286 // branch. The branch folder can create these, and we must get rid of them for
287 // correctness of Thumb constant islands.
288 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
289 isIndirectBranchOpcode(SecondLastOpc)) &&
290 isUncondBranchOpcode(LastOpc)) {
293 I->eraseFromParent();
297 // Otherwise, can't handle this.
302 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
303 MachineBasicBlock::iterator I = MBB.end();
304 if (I == MBB.begin()) return 0;
306 while (I->isDebugValue()) {
307 if (I == MBB.begin())
311 if (!isUncondBranchOpcode(I->getOpcode()) &&
312 !isCondBranchOpcode(I->getOpcode()))
315 // Remove the branch.
316 I->eraseFromParent();
320 if (I == MBB.begin()) return 1;
322 if (!isCondBranchOpcode(I->getOpcode()))
325 // Remove the branch.
326 I->eraseFromParent();
331 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
332 MachineBasicBlock *FBB,
333 const SmallVectorImpl<MachineOperand> &Cond,
335 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
336 int BOpc = !AFI->isThumbFunction()
337 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
338 int BccOpc = !AFI->isThumbFunction()
339 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
341 // Shouldn't be a fall through.
342 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
343 assert((Cond.size() == 2 || Cond.size() == 0) &&
344 "ARM branch conditions have two components!");
347 if (Cond.empty()) // Unconditional branch?
348 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
350 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
351 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
355 // Two-way conditional branch.
356 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
357 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
358 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
362 bool ARMBaseInstrInfo::
363 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
364 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
365 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
369 bool ARMBaseInstrInfo::
370 PredicateInstruction(MachineInstr *MI,
371 const SmallVectorImpl<MachineOperand> &Pred) const {
372 unsigned Opc = MI->getOpcode();
373 if (isUncondBranchOpcode(Opc)) {
374 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
375 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
376 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
380 int PIdx = MI->findFirstPredOperandIdx();
382 MachineOperand &PMO = MI->getOperand(PIdx);
383 PMO.setImm(Pred[0].getImm());
384 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
390 bool ARMBaseInstrInfo::
391 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
392 const SmallVectorImpl<MachineOperand> &Pred2) const {
393 if (Pred1.size() > 2 || Pred2.size() > 2)
396 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
397 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
407 return CC2 == ARMCC::HI;
409 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
411 return CC2 == ARMCC::GT;
413 return CC2 == ARMCC::LT;
417 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
418 std::vector<MachineOperand> &Pred) const {
419 // FIXME: This confuses implicit_def with optional CPSR def.
420 const TargetInstrDesc &TID = MI->getDesc();
421 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
425 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
426 const MachineOperand &MO = MI->getOperand(i);
427 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
436 /// isPredicable - Return true if the specified instruction can be predicated.
437 /// By default, this returns true for every instruction with a
438 /// PredicateOperand.
439 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
440 const TargetInstrDesc &TID = MI->getDesc();
441 if (!TID.isPredicable())
444 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
445 ARMFunctionInfo *AFI =
446 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
447 return AFI->isThumb2Function();
452 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
453 LLVM_ATTRIBUTE_NOINLINE
454 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
456 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
458 assert(JTI < JT.size());
459 return JT[JTI].MBBs.size();
462 /// GetInstSize - Return the size of the specified MachineInstr.
464 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
465 const MachineBasicBlock &MBB = *MI->getParent();
466 const MachineFunction *MF = MBB.getParent();
467 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
469 // Basic size info comes from the TSFlags field.
470 const TargetInstrDesc &TID = MI->getDesc();
471 uint64_t TSFlags = TID.TSFlags;
473 unsigned Opc = MI->getOpcode();
474 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
476 // If this machine instr is an inline asm, measure it.
477 if (MI->getOpcode() == ARM::INLINEASM)
478 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
483 llvm_unreachable("Unknown or unset size field for instr!");
484 case TargetOpcode::IMPLICIT_DEF:
485 case TargetOpcode::KILL:
486 case TargetOpcode::PROLOG_LABEL:
487 case TargetOpcode::EH_LABEL:
488 case TargetOpcode::DBG_VALUE:
493 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
494 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
495 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
496 case ARMII::SizeSpecial: {
499 case ARM::t2MOVi32imm:
501 case ARM::CONSTPOOL_ENTRY:
502 // If this machine instr is a constant pool entry, its size is recorded as
504 return MI->getOperand(2).getImm();
505 case ARM::Int_eh_sjlj_longjmp:
507 case ARM::tInt_eh_sjlj_longjmp:
509 case ARM::Int_eh_sjlj_setjmp:
510 case ARM::Int_eh_sjlj_setjmp_nofp:
512 case ARM::tInt_eh_sjlj_setjmp:
513 case ARM::t2Int_eh_sjlj_setjmp:
514 case ARM::t2Int_eh_sjlj_setjmp_nofp:
522 case ARM::t2TBH_JT: {
523 // These are jumptable branches, i.e. a branch followed by an inlined
524 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
525 // entry is one byte; TBH two byte each.
526 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
527 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
528 unsigned NumOps = TID.getNumOperands();
529 MachineOperand JTOP =
530 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
531 unsigned JTI = JTOP.getIndex();
532 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
534 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
535 assert(JTI < JT.size());
536 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
537 // 4 aligned. The assembler / linker may add 2 byte padding just before
538 // the JT entries. The size does not include this padding; the
539 // constant islands pass does separate bookkeeping for it.
540 // FIXME: If we know the size of the function is less than (1 << 16) *2
541 // bytes, we can use 16-bit entries instead. Then there won't be an
543 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
544 unsigned NumEntries = getNumJTEntries(JT, JTI);
545 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
546 // Make sure the instruction that follows TBB is 2-byte aligned.
547 // FIXME: Constant island pass should insert an "ALIGN" instruction
550 return NumEntries * EntrySize + InstSize;
553 // Otherwise, pseudo-instruction sizes are zero.
558 return 0; // Not reached
561 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
562 MachineBasicBlock::iterator I, DebugLoc DL,
563 unsigned DestReg, unsigned SrcReg,
564 bool KillSrc) const {
565 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
566 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
568 if (GPRDest && GPRSrc) {
569 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
570 .addReg(SrcReg, getKillRegState(KillSrc))));
574 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
575 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
578 if (SPRDest && SPRSrc)
580 else if (GPRDest && SPRSrc)
582 else if (SPRDest && GPRSrc)
584 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
586 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
588 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
590 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
593 llvm_unreachable("Impossible reg-to-reg copy");
595 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
596 MIB.addReg(SrcReg, getKillRegState(KillSrc));
597 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
602 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
603 unsigned Reg, unsigned SubIdx, unsigned State,
604 const TargetRegisterInfo *TRI) {
606 return MIB.addReg(Reg, State);
608 if (TargetRegisterInfo::isPhysicalRegister(Reg))
609 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
610 return MIB.addReg(Reg, State, SubIdx);
613 void ARMBaseInstrInfo::
614 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
615 unsigned SrcReg, bool isKill, int FI,
616 const TargetRegisterClass *RC,
617 const TargetRegisterInfo *TRI) const {
619 if (I != MBB.end()) DL = I->getDebugLoc();
620 MachineFunction &MF = *MBB.getParent();
621 MachineFrameInfo &MFI = *MF.getFrameInfo();
622 unsigned Align = MFI.getObjectAlignment(FI);
624 MachineMemOperand *MMO =
625 MF.getMachineMemOperand(MachinePointerInfo(
626 PseudoSourceValue::getFixedStack(FI)),
627 MachineMemOperand::MOStore,
628 MFI.getObjectSize(FI),
631 // tGPR is used sometimes in ARM instructions that need to avoid using
632 // certain registers. Just treat it as GPR here. Likewise, rGPR.
633 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
634 || RC == ARM::rGPRRegisterClass)
635 RC = ARM::GPRRegisterClass;
637 switch (RC->getID()) {
638 case ARM::GPRRegClassID:
639 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
640 .addReg(SrcReg, getKillRegState(isKill))
641 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
643 case ARM::SPRRegClassID:
644 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
645 .addReg(SrcReg, getKillRegState(isKill))
646 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
648 case ARM::DPRRegClassID:
649 case ARM::DPR_VFP2RegClassID:
650 case ARM::DPR_8RegClassID:
651 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
652 .addReg(SrcReg, getKillRegState(isKill))
653 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
655 case ARM::QPRRegClassID:
656 case ARM::QPR_VFP2RegClassID:
657 case ARM::QPR_8RegClassID:
658 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
659 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
660 .addFrameIndex(FI).addImm(16)
661 .addReg(SrcReg, getKillRegState(isKill))
662 .addMemOperand(MMO));
664 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
665 .addReg(SrcReg, getKillRegState(isKill))
667 .addMemOperand(MMO));
670 case ARM::QQPRRegClassID:
671 case ARM::QQPR_VFP2RegClassID:
672 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
673 // FIXME: It's possible to only store part of the QQ register if the
674 // spilled def has a sub-register index.
675 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
676 .addFrameIndex(FI).addImm(16)
677 .addReg(SrcReg, getKillRegState(isKill))
678 .addMemOperand(MMO));
680 MachineInstrBuilder MIB =
681 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
684 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
685 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
686 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
687 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
690 case ARM::QQQQPRRegClassID: {
691 MachineInstrBuilder MIB =
692 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
695 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
696 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
697 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
698 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
699 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
700 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
701 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
702 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
706 llvm_unreachable("Unknown regclass!");
711 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
712 int &FrameIndex) const {
713 switch (MI->getOpcode()) {
716 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
717 if (MI->getOperand(1).isFI() &&
718 MI->getOperand(2).isReg() &&
719 MI->getOperand(3).isImm() &&
720 MI->getOperand(2).getReg() == 0 &&
721 MI->getOperand(3).getImm() == 0) {
722 FrameIndex = MI->getOperand(1).getIndex();
723 return MI->getOperand(0).getReg();
731 if (MI->getOperand(1).isFI() &&
732 MI->getOperand(2).isImm() &&
733 MI->getOperand(2).getImm() == 0) {
734 FrameIndex = MI->getOperand(1).getIndex();
735 return MI->getOperand(0).getReg();
738 case ARM::VST1q64Pseudo:
739 if (MI->getOperand(0).isFI() &&
740 MI->getOperand(2).getSubReg() == 0) {
741 FrameIndex = MI->getOperand(0).getIndex();
742 return MI->getOperand(2).getReg();
746 if (MI->getOperand(1).isFI() &&
747 MI->getOperand(0).getSubReg() == 0) {
748 FrameIndex = MI->getOperand(1).getIndex();
749 return MI->getOperand(0).getReg();
757 void ARMBaseInstrInfo::
758 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
759 unsigned DestReg, int FI,
760 const TargetRegisterClass *RC,
761 const TargetRegisterInfo *TRI) const {
763 if (I != MBB.end()) DL = I->getDebugLoc();
764 MachineFunction &MF = *MBB.getParent();
765 MachineFrameInfo &MFI = *MF.getFrameInfo();
766 unsigned Align = MFI.getObjectAlignment(FI);
767 MachineMemOperand *MMO =
768 MF.getMachineMemOperand(
769 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
770 MachineMemOperand::MOLoad,
771 MFI.getObjectSize(FI),
774 // tGPR is used sometimes in ARM instructions that need to avoid using
775 // certain registers. Just treat it as GPR here.
776 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
777 || RC == ARM::rGPRRegisterClass)
778 RC = ARM::GPRRegisterClass;
780 switch (RC->getID()) {
781 case ARM::GPRRegClassID:
782 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
783 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
785 case ARM::SPRRegClassID:
786 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
787 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
789 case ARM::DPRRegClassID:
790 case ARM::DPR_VFP2RegClassID:
791 case ARM::DPR_8RegClassID:
792 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
793 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
795 case ARM::QPRRegClassID:
796 case ARM::QPR_VFP2RegClassID:
797 case ARM::QPR_8RegClassID:
798 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
799 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
800 .addFrameIndex(FI).addImm(16)
801 .addMemOperand(MMO));
803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
805 .addMemOperand(MMO));
808 case ARM::QQPRRegClassID:
809 case ARM::QQPR_VFP2RegClassID:
810 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
811 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
812 .addFrameIndex(FI).addImm(16)
813 .addMemOperand(MMO));
815 MachineInstrBuilder MIB =
816 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
819 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
820 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
821 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
822 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
825 case ARM::QQQQPRRegClassID: {
826 MachineInstrBuilder MIB =
827 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
830 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
831 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
832 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
833 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
834 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
835 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
836 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
837 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
841 llvm_unreachable("Unknown regclass!");
846 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
847 int &FrameIndex) const {
848 switch (MI->getOpcode()) {
851 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
852 if (MI->getOperand(1).isFI() &&
853 MI->getOperand(2).isReg() &&
854 MI->getOperand(3).isImm() &&
855 MI->getOperand(2).getReg() == 0 &&
856 MI->getOperand(3).getImm() == 0) {
857 FrameIndex = MI->getOperand(1).getIndex();
858 return MI->getOperand(0).getReg();
866 if (MI->getOperand(1).isFI() &&
867 MI->getOperand(2).isImm() &&
868 MI->getOperand(2).getImm() == 0) {
869 FrameIndex = MI->getOperand(1).getIndex();
870 return MI->getOperand(0).getReg();
873 case ARM::VLD1q64Pseudo:
874 if (MI->getOperand(1).isFI() &&
875 MI->getOperand(0).getSubReg() == 0) {
876 FrameIndex = MI->getOperand(1).getIndex();
877 return MI->getOperand(0).getReg();
881 if (MI->getOperand(1).isFI() &&
882 MI->getOperand(0).getSubReg() == 0) {
883 FrameIndex = MI->getOperand(1).getIndex();
884 return MI->getOperand(0).getReg();
893 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
894 int FrameIx, uint64_t Offset,
897 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
898 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
902 /// Create a copy of a const pool value. Update CPI to the new index and return
904 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
905 MachineConstantPool *MCP = MF.getConstantPool();
906 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
908 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
909 assert(MCPE.isMachineConstantPoolEntry() &&
910 "Expecting a machine constantpool entry!");
911 ARMConstantPoolValue *ACPV =
912 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
914 unsigned PCLabelId = AFI->createConstPoolEntryUId();
915 ARMConstantPoolValue *NewCPV = 0;
916 // FIXME: The below assumes PIC relocation model and that the function
917 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
918 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
919 // instructions, so that's probably OK, but is PIC always correct when
921 if (ACPV->isGlobalValue())
922 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
924 else if (ACPV->isExtSymbol())
925 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
926 ACPV->getSymbol(), PCLabelId, 4);
927 else if (ACPV->isBlockAddress())
928 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
929 ARMCP::CPBlockAddress, 4);
930 else if (ACPV->isLSDA())
931 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
934 llvm_unreachable("Unexpected ARM constantpool value type!!");
935 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
939 void ARMBaseInstrInfo::
940 reMaterialize(MachineBasicBlock &MBB,
941 MachineBasicBlock::iterator I,
942 unsigned DestReg, unsigned SubIdx,
943 const MachineInstr *Orig,
944 const TargetRegisterInfo &TRI) const {
945 unsigned Opcode = Orig->getOpcode();
948 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
949 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
953 case ARM::tLDRpci_pic:
954 case ARM::t2LDRpci_pic: {
955 MachineFunction &MF = *MBB.getParent();
956 unsigned CPI = Orig->getOperand(1).getIndex();
957 unsigned PCLabelId = duplicateCPV(MF, CPI);
958 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
960 .addConstantPoolIndex(CPI).addImm(PCLabelId);
961 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
968 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
969 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
970 switch(Orig->getOpcode()) {
971 case ARM::tLDRpci_pic:
972 case ARM::t2LDRpci_pic: {
973 unsigned CPI = Orig->getOperand(1).getIndex();
974 unsigned PCLabelId = duplicateCPV(MF, CPI);
975 Orig->getOperand(1).setIndex(CPI);
976 Orig->getOperand(2).setImm(PCLabelId);
983 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
984 const MachineInstr *MI1) const {
985 int Opcode = MI0->getOpcode();
986 if (Opcode == ARM::t2LDRpci ||
987 Opcode == ARM::t2LDRpci_pic ||
988 Opcode == ARM::tLDRpci ||
989 Opcode == ARM::tLDRpci_pic) {
990 if (MI1->getOpcode() != Opcode)
992 if (MI0->getNumOperands() != MI1->getNumOperands())
995 const MachineOperand &MO0 = MI0->getOperand(1);
996 const MachineOperand &MO1 = MI1->getOperand(1);
997 if (MO0.getOffset() != MO1.getOffset())
1000 const MachineFunction *MF = MI0->getParent()->getParent();
1001 const MachineConstantPool *MCP = MF->getConstantPool();
1002 int CPI0 = MO0.getIndex();
1003 int CPI1 = MO1.getIndex();
1004 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1005 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1006 ARMConstantPoolValue *ACPV0 =
1007 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1008 ARMConstantPoolValue *ACPV1 =
1009 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1010 return ACPV0->hasSameValue(ACPV1);
1013 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1016 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1017 /// determine if two loads are loading from the same base address. It should
1018 /// only return true if the base pointers are the same and the only differences
1019 /// between the two addresses is the offset. It also returns the offsets by
1021 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1023 int64_t &Offset2) const {
1024 // Don't worry about Thumb: just ARM and Thumb2.
1025 if (Subtarget.isThumb1Only()) return false;
1027 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1030 switch (Load1->getMachineOpcode()) {
1043 case ARM::t2LDRSHi8:
1045 case ARM::t2LDRSHi12:
1049 switch (Load2->getMachineOpcode()) {
1062 case ARM::t2LDRSHi8:
1064 case ARM::t2LDRSHi12:
1068 // Check if base addresses and chain operands match.
1069 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1070 Load1->getOperand(4) != Load2->getOperand(4))
1073 // Index should be Reg0.
1074 if (Load1->getOperand(3) != Load2->getOperand(3))
1077 // Determine the offsets.
1078 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1079 isa<ConstantSDNode>(Load2->getOperand(1))) {
1080 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1081 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1088 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1089 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1090 /// be scheduled togther. On some targets if two loads are loading from
1091 /// addresses in the same cache line, it's better if they are scheduled
1092 /// together. This function takes two integers that represent the load offsets
1093 /// from the common base address. It returns true if it decides it's desirable
1094 /// to schedule the two loads together. "NumLoads" is the number of loads that
1095 /// have already been scheduled after Load1.
1096 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1097 int64_t Offset1, int64_t Offset2,
1098 unsigned NumLoads) const {
1099 // Don't worry about Thumb: just ARM and Thumb2.
1100 if (Subtarget.isThumb1Only()) return false;
1102 assert(Offset2 > Offset1);
1104 if ((Offset2 - Offset1) / 8 > 64)
1107 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1108 return false; // FIXME: overly conservative?
1110 // Four loads in a row should be sufficient.
1117 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1118 const MachineBasicBlock *MBB,
1119 const MachineFunction &MF) const {
1120 // Debug info is never a scheduling boundary. It's necessary to be explicit
1121 // due to the special treatment of IT instructions below, otherwise a
1122 // dbg_value followed by an IT will result in the IT instruction being
1123 // considered a scheduling hazard, which is wrong. It should be the actual
1124 // instruction preceding the dbg_value instruction(s), just like it is
1125 // when debug info is not present.
1126 if (MI->isDebugValue())
1129 // Terminators and labels can't be scheduled around.
1130 if (MI->getDesc().isTerminator() || MI->isLabel())
1133 // Treat the start of the IT block as a scheduling boundary, but schedule
1134 // t2IT along with all instructions following it.
1135 // FIXME: This is a big hammer. But the alternative is to add all potential
1136 // true and anti dependencies to IT block instructions as implicit operands
1137 // to the t2IT instruction. The added compile time and complexity does not
1139 MachineBasicBlock::const_iterator I = MI;
1140 // Make sure to skip any dbg_value instructions
1141 while (++I != MBB->end() && I->isDebugValue())
1143 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1146 // Don't attempt to schedule around any instruction that defines
1147 // a stack-oriented pointer, as it's unlikely to be profitable. This
1148 // saves compile time, because it doesn't require every single
1149 // stack slot reference to depend on the instruction that does the
1151 if (MI->definesRegister(ARM::SP))
1157 bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1159 unsigned ExtraPredCycles,
1161 float Confidence) const {
1165 // Attempt to estimate the relative costs of predication versus branching.
1166 float UnpredCost = Probability * NumCyles;
1167 UnpredCost += 1.0; // The branch itself
1168 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1170 return (float)(NumCyles + ExtraPredCycles) < UnpredCost;
1173 bool ARMBaseInstrInfo::
1174 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1175 unsigned TCycles, unsigned TExtra,
1176 MachineBasicBlock &FMBB,
1177 unsigned FCycles, unsigned FExtra,
1178 float Probability, float Confidence) const {
1179 if (!TCycles || !FCycles)
1182 // Attempt to estimate the relative costs of predication versus branching.
1183 float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles;
1184 UnpredCost += 1.0; // The branch itself
1185 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1187 return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost;
1190 /// getInstrPredicate - If instruction is predicated, returns its predicate
1191 /// condition, otherwise returns AL. It also returns the condition code
1192 /// register by reference.
1194 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1195 int PIdx = MI->findFirstPredOperandIdx();
1201 PredReg = MI->getOperand(PIdx+1).getReg();
1202 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1206 int llvm::getMatchingCondBranchOpcode(int Opc) {
1209 else if (Opc == ARM::tB)
1211 else if (Opc == ARM::t2B)
1214 llvm_unreachable("Unknown unconditional branch opcode!");
1219 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1220 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1221 unsigned DestReg, unsigned BaseReg, int NumBytes,
1222 ARMCC::CondCodes Pred, unsigned PredReg,
1223 const ARMBaseInstrInfo &TII) {
1224 bool isSub = NumBytes < 0;
1225 if (isSub) NumBytes = -NumBytes;
1228 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1229 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1230 assert(ThisVal && "Didn't extract field correctly");
1232 // We will handle these bits from offset, clear them.
1233 NumBytes &= ~ThisVal;
1235 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1237 // Build the new ADD / SUB.
1238 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1239 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1240 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1241 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1246 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1247 unsigned FrameReg, int &Offset,
1248 const ARMBaseInstrInfo &TII) {
1249 unsigned Opcode = MI.getOpcode();
1250 const TargetInstrDesc &Desc = MI.getDesc();
1251 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1254 // Memory operands in inline assembly always use AddrMode2.
1255 if (Opcode == ARM::INLINEASM)
1256 AddrMode = ARMII::AddrMode2;
1258 if (Opcode == ARM::ADDri) {
1259 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1261 // Turn it into a move.
1262 MI.setDesc(TII.get(ARM::MOVr));
1263 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1264 MI.RemoveOperand(FrameRegIdx+1);
1267 } else if (Offset < 0) {
1270 MI.setDesc(TII.get(ARM::SUBri));
1273 // Common case: small offset, fits into instruction.
1274 if (ARM_AM::getSOImmVal(Offset) != -1) {
1275 // Replace the FrameIndex with sp / fp
1276 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1277 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1282 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1284 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1285 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1287 // We will handle these bits from offset, clear them.
1288 Offset &= ~ThisImmVal;
1290 // Get the properly encoded SOImmVal field.
1291 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1292 "Bit extraction didn't work?");
1293 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1295 unsigned ImmIdx = 0;
1297 unsigned NumBits = 0;
1300 case ARMII::AddrMode_i12: {
1301 ImmIdx = FrameRegIdx + 1;
1302 InstrOffs = MI.getOperand(ImmIdx).getImm();
1306 case ARMII::AddrMode2: {
1307 ImmIdx = FrameRegIdx+2;
1308 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1309 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1314 case ARMII::AddrMode3: {
1315 ImmIdx = FrameRegIdx+2;
1316 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1317 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1322 case ARMII::AddrMode4:
1323 case ARMII::AddrMode6:
1324 // Can't fold any offset even if it's zero.
1326 case ARMII::AddrMode5: {
1327 ImmIdx = FrameRegIdx+1;
1328 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1329 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1336 llvm_unreachable("Unsupported addressing mode!");
1340 Offset += InstrOffs * Scale;
1341 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1347 // Attempt to fold address comp. if opcode has offset bits
1349 // Common case: small offset, fits into instruction.
1350 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1351 int ImmedOffset = Offset / Scale;
1352 unsigned Mask = (1 << NumBits) - 1;
1353 if ((unsigned)Offset <= Mask * Scale) {
1354 // Replace the FrameIndex with sp
1355 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1356 // FIXME: When addrmode2 goes away, this will simplify (like the
1357 // T2 version), as the LDR.i12 versions don't need the encoding
1358 // tricks for the offset value.
1360 if (AddrMode == ARMII::AddrMode_i12)
1361 ImmedOffset = -ImmedOffset;
1363 ImmedOffset |= 1 << NumBits;
1365 ImmOp.ChangeToImmediate(ImmedOffset);
1370 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1371 ImmedOffset = ImmedOffset & Mask;
1373 if (AddrMode == ARMII::AddrMode_i12)
1374 ImmedOffset = -ImmedOffset;
1376 ImmedOffset |= 1 << NumBits;
1378 ImmOp.ChangeToImmediate(ImmedOffset);
1379 Offset &= ~(Mask*Scale);
1383 Offset = (isSub) ? -Offset : Offset;
1387 bool ARMBaseInstrInfo::
1388 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1389 int &CmpValue) const {
1390 switch (MI->getOpcode()) {
1396 SrcReg = MI->getOperand(0).getReg();
1398 CmpValue = MI->getOperand(1).getImm();
1402 SrcReg = MI->getOperand(0).getReg();
1403 CmpMask = MI->getOperand(1).getImm();
1411 /// isSuitableForMask - Identify a suitable 'and' instruction that
1412 /// operates on the given source register and applies the same mask
1413 /// as a 'tst' instruction. Provide a limited look-through for copies.
1414 /// When successful, MI will hold the found instruction.
1415 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1416 int CmpMask, bool CommonUse) {
1417 switch (MI->getOpcode()) {
1420 if (CmpMask != MI->getOperand(2).getImm())
1422 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1426 // Walk down one instruction which is potentially an 'and'.
1427 const MachineInstr &Copy = *MI;
1428 MachineBasicBlock::iterator AND(
1429 llvm::next(MachineBasicBlock::iterator(MI)));
1430 if (AND == MI->getParent()->end()) return false;
1432 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1440 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1441 /// comparison into one that sets the zero bit in the flags register.
1442 bool ARMBaseInstrInfo::
1443 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1444 int CmpValue, const MachineRegisterInfo *MRI) const {
1448 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1449 if (llvm::next(DI) != MRI->def_end())
1450 // Only support one definition.
1453 MachineInstr *MI = &*DI;
1455 // Masked compares sometimes use the same register as the corresponding 'and'.
1456 if (CmpMask != ~0) {
1457 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1459 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1460 UE = MRI->use_end(); UI != UE; ++UI) {
1461 if (UI->getParent() != CmpInstr->getParent()) continue;
1462 MachineInstr *PotentialAND = &*UI;
1463 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1468 if (!MI) return false;
1472 // Conservatively refuse to convert an instruction which isn't in the same BB
1473 // as the comparison.
1474 if (MI->getParent() != CmpInstr->getParent())
1477 // Check that CPSR isn't set between the comparison instruction and the one we
1479 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1480 B = MI->getParent()->begin();
1482 // Early exit if CmpInstr is at the beginning of the BB.
1483 if (I == B) return false;
1486 for (; I != E; --I) {
1487 const MachineInstr &Instr = *I;
1489 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1490 const MachineOperand &MO = Instr.getOperand(IO);
1491 if (!MO.isReg()) continue;
1493 // This instruction modifies or uses CPSR after the one we want to
1494 // change. We can't do this transformation.
1495 if (MO.getReg() == ARM::CPSR)
1500 // The 'and' is below the comparison instruction.
1504 // Set the "zero" bit in CPSR.
1505 switch (MI->getOpcode()) {
1513 // Toggle the optional operand to CPSR.
1514 MI->getOperand(5).setReg(ARM::CPSR);
1515 MI->getOperand(5).setIsDef(true);
1516 CmpInstr->eraseFromParent();
1523 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1524 MachineInstr *DefMI, unsigned Reg,
1525 MachineRegisterInfo *MRI) const {
1526 // Fold large immediates into add, sub, or, xor.
1527 unsigned DefOpc = DefMI->getOpcode();
1528 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1530 if (!DefMI->getOperand(1).isImm())
1531 // Could be t2MOVi32imm <ga:xx>
1534 if (!MRI->hasOneNonDBGUse(Reg))
1537 unsigned UseOpc = UseMI->getOpcode();
1538 unsigned NewUseOpc = 0;
1539 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1540 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1541 bool Commute = false;
1543 default: return false;
1551 case ARM::t2EORrr: {
1552 Commute = UseMI->getOperand(2).getReg() != Reg;
1559 NewUseOpc = ARM::SUBri;
1565 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1567 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1568 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1571 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1572 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1573 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1577 case ARM::t2SUBrr: {
1581 NewUseOpc = ARM::t2SUBri;
1586 case ARM::t2EORrr: {
1587 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1589 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1590 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1593 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1594 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1595 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1603 unsigned OpIdx = Commute ? 2 : 1;
1604 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1605 bool isKill = UseMI->getOperand(OpIdx).isKill();
1606 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1607 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1608 *UseMI, UseMI->getDebugLoc(),
1609 get(NewUseOpc), NewReg)
1610 .addReg(Reg1, getKillRegState(isKill))
1611 .addImm(SOImmValV1)));
1612 UseMI->setDesc(get(NewUseOpc));
1613 UseMI->getOperand(1).setReg(NewReg);
1614 UseMI->getOperand(1).setIsKill();
1615 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1616 DefMI->eraseFromParent();
1621 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1622 const MachineInstr *MI) const {
1623 if (!ItinData || ItinData->isEmpty())
1626 const TargetInstrDesc &Desc = MI->getDesc();
1627 unsigned Class = Desc.getSchedClass();
1628 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1632 unsigned Opc = MI->getOpcode();
1635 llvm_unreachable("Unexpected multi-uops instruction!");
1643 // The number of uOps for load / store multiple are determined by the number
1646 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1647 // same cycle. The scheduling for the first load / store must be done
1648 // separately by assuming the the address is not 64-bit aligned.
1650 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1651 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1652 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1655 case ARM::VLDMDIA_UPD:
1656 case ARM::VLDMDDB_UPD:
1659 case ARM::VLDMSIA_UPD:
1660 case ARM::VLDMSDB_UPD:
1663 case ARM::VSTMDIA_UPD:
1664 case ARM::VSTMDDB_UPD:
1667 case ARM::VSTMSIA_UPD:
1668 case ARM::VSTMSDB_UPD: {
1669 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1670 return (NumRegs / 2) + (NumRegs % 2) + 1;
1673 case ARM::LDMIA_RET:
1678 case ARM::LDMIA_UPD:
1679 case ARM::LDMDA_UPD:
1680 case ARM::LDMDB_UPD:
1681 case ARM::LDMIB_UPD:
1686 case ARM::STMIA_UPD:
1687 case ARM::STMDA_UPD:
1688 case ARM::STMDB_UPD:
1689 case ARM::STMIB_UPD:
1691 case ARM::tLDMIA_UPD:
1693 case ARM::tSTMIA_UPD:
1697 case ARM::t2LDMIA_RET:
1700 case ARM::t2LDMIA_UPD:
1701 case ARM::t2LDMDB_UPD:
1704 case ARM::t2STMIA_UPD:
1705 case ARM::t2STMDB_UPD: {
1706 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1707 if (Subtarget.isCortexA8()) {
1710 // 4 registers would be issued: 2, 2.
1711 // 5 registers would be issued: 2, 2, 1.
1712 UOps = (NumRegs / 2);
1716 } else if (Subtarget.isCortexA9()) {
1717 UOps = (NumRegs / 2);
1718 // If there are odd number of registers or if it's not 64-bit aligned,
1719 // then it takes an extra AGU (Address Generation Unit) cycle.
1720 if ((NumRegs % 2) ||
1721 !MI->hasOneMemOperand() ||
1722 (*MI->memoperands_begin())->getAlignment() < 8)
1726 // Assume the worst.
1734 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1735 const TargetInstrDesc &DefTID,
1737 unsigned DefIdx, unsigned DefAlign) const {
1738 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1740 // Def is the address writeback.
1741 return ItinData->getOperandCycle(DefClass, DefIdx);
1744 if (Subtarget.isCortexA8()) {
1745 // (regno / 2) + (regno % 2) + 1
1746 DefCycle = RegNo / 2 + 1;
1749 } else if (Subtarget.isCortexA9()) {
1751 bool isSLoad = false;
1753 switch (DefTID.getOpcode()) {
1757 case ARM::VLDMSIA_UPD:
1758 case ARM::VLDMSDB_UPD:
1763 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1764 // then it takes an extra cycle.
1765 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1768 // Assume the worst.
1769 DefCycle = RegNo + 2;
1776 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1777 const TargetInstrDesc &DefTID,
1779 unsigned DefIdx, unsigned DefAlign) const {
1780 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1782 // Def is the address writeback.
1783 return ItinData->getOperandCycle(DefClass, DefIdx);
1786 if (Subtarget.isCortexA8()) {
1787 // 4 registers would be issued: 1, 2, 1.
1788 // 5 registers would be issued: 1, 2, 2.
1789 DefCycle = RegNo / 2;
1792 // Result latency is issue cycle + 2: E2.
1794 } else if (Subtarget.isCortexA9()) {
1795 DefCycle = (RegNo / 2);
1796 // If there are odd number of registers or if it's not 64-bit aligned,
1797 // then it takes an extra AGU (Address Generation Unit) cycle.
1798 if ((RegNo % 2) || DefAlign < 8)
1800 // Result latency is AGU cycles + 2.
1803 // Assume the worst.
1804 DefCycle = RegNo + 2;
1811 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1812 const TargetInstrDesc &UseTID,
1814 unsigned UseIdx, unsigned UseAlign) const {
1815 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1817 return ItinData->getOperandCycle(UseClass, UseIdx);
1820 if (Subtarget.isCortexA8()) {
1821 // (regno / 2) + (regno % 2) + 1
1822 UseCycle = RegNo / 2 + 1;
1825 } else if (Subtarget.isCortexA9()) {
1827 bool isSStore = false;
1829 switch (UseTID.getOpcode()) {
1833 case ARM::VSTMSIA_UPD:
1834 case ARM::VSTMSDB_UPD:
1839 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1840 // then it takes an extra cycle.
1841 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
1844 // Assume the worst.
1845 UseCycle = RegNo + 2;
1852 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
1853 const TargetInstrDesc &UseTID,
1855 unsigned UseIdx, unsigned UseAlign) const {
1856 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1858 return ItinData->getOperandCycle(UseClass, UseIdx);
1861 if (Subtarget.isCortexA8()) {
1862 UseCycle = RegNo / 2;
1867 } else if (Subtarget.isCortexA9()) {
1868 UseCycle = (RegNo / 2);
1869 // If there are odd number of registers or if it's not 64-bit aligned,
1870 // then it takes an extra AGU (Address Generation Unit) cycle.
1871 if ((RegNo % 2) || UseAlign < 8)
1874 // Assume the worst.
1881 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1882 const TargetInstrDesc &DefTID,
1883 unsigned DefIdx, unsigned DefAlign,
1884 const TargetInstrDesc &UseTID,
1885 unsigned UseIdx, unsigned UseAlign) const {
1886 unsigned DefClass = DefTID.getSchedClass();
1887 unsigned UseClass = UseTID.getSchedClass();
1889 if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
1890 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1892 // This may be a def / use of a variable_ops instruction, the operand
1893 // latency might be determinable dynamically. Let the target try to
1896 bool LdmBypass = false;
1897 switch (DefTID.getOpcode()) {
1899 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
1904 case ARM::VLDMDIA_UPD:
1905 case ARM::VLDMDDB_UPD:
1908 case ARM::VLDMSIA_UPD:
1909 case ARM::VLDMSDB_UPD:
1910 DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
1913 case ARM::LDMIA_RET:
1918 case ARM::LDMIA_UPD:
1919 case ARM::LDMDA_UPD:
1920 case ARM::LDMDB_UPD:
1921 case ARM::LDMIB_UPD:
1923 case ARM::tLDMIA_UPD:
1925 case ARM::t2LDMIA_RET:
1928 case ARM::t2LDMIA_UPD:
1929 case ARM::t2LDMDB_UPD:
1931 DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
1936 // We can't seem to determine the result latency of the def, assume it's 2.
1940 switch (UseTID.getOpcode()) {
1942 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
1947 case ARM::VSTMDIA_UPD:
1948 case ARM::VSTMDDB_UPD:
1951 case ARM::VSTMSIA_UPD:
1952 case ARM::VSTMSDB_UPD:
1953 UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
1960 case ARM::STMIA_UPD:
1961 case ARM::STMDA_UPD:
1962 case ARM::STMDB_UPD:
1963 case ARM::STMIB_UPD:
1965 case ARM::tSTMIA_UPD:
1970 case ARM::t2STMIA_UPD:
1971 case ARM::t2STMDB_UPD:
1972 UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
1977 // Assume it's read in the first stage.
1980 UseCycle = DefCycle - UseCycle + 1;
1983 // It's a variable_ops instruction so we can't use DefIdx here. Just use
1984 // first def operand.
1985 if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
1988 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
1989 UseClass, UseIdx)) {
1998 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1999 const MachineInstr *DefMI, unsigned DefIdx,
2000 const MachineInstr *UseMI, unsigned UseIdx) const {
2001 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2002 DefMI->isRegSequence() || DefMI->isImplicitDef())
2005 const TargetInstrDesc &DefTID = DefMI->getDesc();
2006 if (!ItinData || ItinData->isEmpty())
2007 return DefTID.mayLoad() ? 3 : 1;
2010 const TargetInstrDesc &UseTID = UseMI->getDesc();
2011 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2012 if (DefMO.getReg() == ARM::CPSR) {
2013 if (DefMI->getOpcode() == ARM::FMSTAT) {
2014 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2015 return Subtarget.isCortexA9() ? 1 : 20;
2018 // CPSR set and branch can be paired in the same cycle.
2019 if (UseTID.isBranch())
2023 unsigned DefAlign = DefMI->hasOneMemOperand()
2024 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2025 unsigned UseAlign = UseMI->hasOneMemOperand()
2026 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2027 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2028 UseTID, UseIdx, UseAlign);
2031 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2032 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2033 // variants are one cycle cheaper.
2034 switch (DefTID.getOpcode()) {
2038 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2039 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2041 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2048 case ARM::t2LDRSHs: {
2049 // Thumb2 mode: lsl only.
2050 unsigned ShAmt = DefMI->getOperand(3).getImm();
2051 if (ShAmt == 0 || ShAmt == 2)
2062 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2063 SDNode *DefNode, unsigned DefIdx,
2064 SDNode *UseNode, unsigned UseIdx) const {
2065 if (!DefNode->isMachineOpcode())
2068 const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
2069 if (!ItinData || ItinData->isEmpty())
2070 return DefTID.mayLoad() ? 3 : 1;
2072 if (!UseNode->isMachineOpcode()) {
2073 int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
2074 if (Subtarget.isCortexA9())
2075 return Latency <= 2 ? 1 : Latency - 1;
2077 return Latency <= 3 ? 1 : Latency - 2;
2080 const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
2081 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2082 unsigned DefAlign = !DefMN->memoperands_empty()
2083 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2084 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2085 unsigned UseAlign = !UseMN->memoperands_empty()
2086 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2087 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2088 UseTID, UseIdx, UseAlign);
2091 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2092 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2093 // variants are one cycle cheaper.
2094 switch (DefTID.getOpcode()) {
2099 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2100 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2102 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2109 case ARM::t2LDRSHs: {
2110 // Thumb2 mode: lsl only.
2112 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2113 if (ShAmt == 0 || ShAmt == 2)
2123 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2124 const MachineInstr *MI,
2125 unsigned *PredCost) const {
2126 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2127 MI->isRegSequence() || MI->isImplicitDef())
2130 if (!ItinData || ItinData->isEmpty())
2133 const TargetInstrDesc &TID = MI->getDesc();
2134 unsigned Class = TID.getSchedClass();
2135 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2136 if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR))
2137 // When predicated, CPSR is an additional source operand for CPSR updating
2138 // instructions, this apparently increases their latencies.
2141 return ItinData->getStageLatency(Class);
2142 return getNumMicroOps(ItinData, MI);
2145 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2146 SDNode *Node) const {
2147 if (!Node->isMachineOpcode())
2150 if (!ItinData || ItinData->isEmpty())
2153 unsigned Opcode = Node->getMachineOpcode();
2156 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2165 bool ARMBaseInstrInfo::
2166 hasHighOperandLatency(const InstrItineraryData *ItinData,
2167 const MachineRegisterInfo *MRI,
2168 const MachineInstr *DefMI, unsigned DefIdx,
2169 const MachineInstr *UseMI, unsigned UseIdx) const {
2170 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2171 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2172 if (Subtarget.isCortexA8() &&
2173 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2174 // CortexA8 VFP instructions are not pipelined.
2177 // Hoist VFP / NEON instructions with 4 or higher latency.
2178 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2181 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2182 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2185 bool ARMBaseInstrInfo::
2186 hasLowDefLatency(const InstrItineraryData *ItinData,
2187 const MachineInstr *DefMI, unsigned DefIdx) const {
2188 if (!ItinData || ItinData->isEmpty())
2191 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2192 if (DDomain == ARMII::DomainGeneral) {
2193 unsigned DefClass = DefMI->getDesc().getSchedClass();
2194 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2195 return (DefCycle != -1 && DefCycle <= 2);