1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Handle register classes that require multiple instructions.
684 unsigned BeginIdx = 0;
685 unsigned SubRegs = 0;
686 unsigned Spacing = 1;
688 // Use VORRq when possible.
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
693 // Fall back to VMOVD.
694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
709 llvm_unreachable("Impossible reg-to-reg copy");
711 const TargetRegisterInfo *TRI = &getRegisterInfo();
712 MachineInstrBuilder Mov;
713 for (unsigned i = 0; i != SubRegs; ++i) {
714 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
715 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
716 assert(Dst && Src && "Bad sub-register");
717 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
719 // VORR takes two source operands.
720 if (Opc == ARM::VORRq)
722 Mov = AddDefaultPred(Mov);
724 // Add implicit super-register defs and kills to the last instruction.
725 Mov->addRegisterDefined(DestReg, TRI);
727 Mov->addRegisterKilled(SrcReg, TRI);
731 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
732 unsigned Reg, unsigned SubIdx, unsigned State,
733 const TargetRegisterInfo *TRI) {
735 return MIB.addReg(Reg, State);
737 if (TargetRegisterInfo::isPhysicalRegister(Reg))
738 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
739 return MIB.addReg(Reg, State, SubIdx);
742 void ARMBaseInstrInfo::
743 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
744 unsigned SrcReg, bool isKill, int FI,
745 const TargetRegisterClass *RC,
746 const TargetRegisterInfo *TRI) const {
748 if (I != MBB.end()) DL = I->getDebugLoc();
749 MachineFunction &MF = *MBB.getParent();
750 MachineFrameInfo &MFI = *MF.getFrameInfo();
751 unsigned Align = MFI.getObjectAlignment(FI);
753 MachineMemOperand *MMO =
754 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
755 MachineMemOperand::MOStore,
756 MFI.getObjectSize(FI),
759 switch (RC->getSize()) {
761 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
762 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
763 .addReg(SrcReg, getKillRegState(isKill))
764 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
765 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
766 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
767 .addReg(SrcReg, getKillRegState(isKill))
768 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
770 llvm_unreachable("Unknown reg class!");
773 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
774 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
775 .addReg(SrcReg, getKillRegState(isKill))
776 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
778 llvm_unreachable("Unknown reg class!");
781 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
782 // Use aligned spills if the stack can be realigned.
783 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
784 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
785 .addFrameIndex(FI).addImm(16)
786 .addReg(SrcReg, getKillRegState(isKill))
787 .addMemOperand(MMO));
789 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
790 .addReg(SrcReg, getKillRegState(isKill))
792 .addMemOperand(MMO));
795 llvm_unreachable("Unknown reg class!");
798 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
799 // Use aligned spills if the stack can be realigned.
800 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
801 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
802 .addFrameIndex(FI).addImm(16)
803 .addReg(SrcReg, getKillRegState(isKill))
804 .addMemOperand(MMO));
806 MachineInstrBuilder MIB =
807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
810 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
812 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
815 llvm_unreachable("Unknown reg class!");
818 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
819 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
820 // FIXME: It's possible to only store part of the QQ register if the
821 // spilled def has a sub-register index.
822 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
823 .addFrameIndex(FI).addImm(16)
824 .addReg(SrcReg, getKillRegState(isKill))
825 .addMemOperand(MMO));
827 MachineInstrBuilder MIB =
828 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
831 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
832 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
833 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
834 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
837 llvm_unreachable("Unknown reg class!");
840 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
841 MachineInstrBuilder MIB =
842 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
845 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
846 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
851 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
852 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
854 llvm_unreachable("Unknown reg class!");
857 llvm_unreachable("Unknown reg class!");
862 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
863 int &FrameIndex) const {
864 switch (MI->getOpcode()) {
867 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
868 if (MI->getOperand(1).isFI() &&
869 MI->getOperand(2).isReg() &&
870 MI->getOperand(3).isImm() &&
871 MI->getOperand(2).getReg() == 0 &&
872 MI->getOperand(3).getImm() == 0) {
873 FrameIndex = MI->getOperand(1).getIndex();
874 return MI->getOperand(0).getReg();
882 if (MI->getOperand(1).isFI() &&
883 MI->getOperand(2).isImm() &&
884 MI->getOperand(2).getImm() == 0) {
885 FrameIndex = MI->getOperand(1).getIndex();
886 return MI->getOperand(0).getReg();
890 case ARM::VST1d64TPseudo:
891 case ARM::VST1d64QPseudo:
892 if (MI->getOperand(0).isFI() &&
893 MI->getOperand(2).getSubReg() == 0) {
894 FrameIndex = MI->getOperand(0).getIndex();
895 return MI->getOperand(2).getReg();
899 if (MI->getOperand(1).isFI() &&
900 MI->getOperand(0).getSubReg() == 0) {
901 FrameIndex = MI->getOperand(1).getIndex();
902 return MI->getOperand(0).getReg();
910 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
911 int &FrameIndex) const {
912 const MachineMemOperand *Dummy;
913 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
916 void ARMBaseInstrInfo::
917 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
918 unsigned DestReg, int FI,
919 const TargetRegisterClass *RC,
920 const TargetRegisterInfo *TRI) const {
922 if (I != MBB.end()) DL = I->getDebugLoc();
923 MachineFunction &MF = *MBB.getParent();
924 MachineFrameInfo &MFI = *MF.getFrameInfo();
925 unsigned Align = MFI.getObjectAlignment(FI);
926 MachineMemOperand *MMO =
927 MF.getMachineMemOperand(
928 MachinePointerInfo::getFixedStack(FI),
929 MachineMemOperand::MOLoad,
930 MFI.getObjectSize(FI),
933 switch (RC->getSize()) {
935 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
936 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
937 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
939 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
940 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
941 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
943 llvm_unreachable("Unknown reg class!");
946 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
947 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
948 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
950 llvm_unreachable("Unknown reg class!");
953 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
954 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
955 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
956 .addFrameIndex(FI).addImm(16)
957 .addMemOperand(MMO));
959 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
961 .addMemOperand(MMO));
964 llvm_unreachable("Unknown reg class!");
967 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
968 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
969 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
970 .addFrameIndex(FI).addImm(16)
971 .addMemOperand(MMO));
973 MachineInstrBuilder MIB =
974 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
976 .addMemOperand(MMO));
977 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
978 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
979 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
980 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
981 MIB.addReg(DestReg, RegState::ImplicitDefine);
984 llvm_unreachable("Unknown reg class!");
987 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
988 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
989 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
990 .addFrameIndex(FI).addImm(16)
991 .addMemOperand(MMO));
993 MachineInstrBuilder MIB =
994 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
997 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
998 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
999 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1000 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1001 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1002 MIB.addReg(DestReg, RegState::ImplicitDefine);
1005 llvm_unreachable("Unknown reg class!");
1008 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1009 MachineInstrBuilder MIB =
1010 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1012 .addMemOperand(MMO);
1013 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1018 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1019 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1020 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1021 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1022 MIB.addReg(DestReg, RegState::ImplicitDefine);
1024 llvm_unreachable("Unknown reg class!");
1027 llvm_unreachable("Unknown regclass!");
1032 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1033 int &FrameIndex) const {
1034 switch (MI->getOpcode()) {
1037 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1038 if (MI->getOperand(1).isFI() &&
1039 MI->getOperand(2).isReg() &&
1040 MI->getOperand(3).isImm() &&
1041 MI->getOperand(2).getReg() == 0 &&
1042 MI->getOperand(3).getImm() == 0) {
1043 FrameIndex = MI->getOperand(1).getIndex();
1044 return MI->getOperand(0).getReg();
1052 if (MI->getOperand(1).isFI() &&
1053 MI->getOperand(2).isImm() &&
1054 MI->getOperand(2).getImm() == 0) {
1055 FrameIndex = MI->getOperand(1).getIndex();
1056 return MI->getOperand(0).getReg();
1060 case ARM::VLD1d64TPseudo:
1061 case ARM::VLD1d64QPseudo:
1062 if (MI->getOperand(1).isFI() &&
1063 MI->getOperand(0).getSubReg() == 0) {
1064 FrameIndex = MI->getOperand(1).getIndex();
1065 return MI->getOperand(0).getReg();
1069 if (MI->getOperand(1).isFI() &&
1070 MI->getOperand(0).getSubReg() == 0) {
1071 FrameIndex = MI->getOperand(1).getIndex();
1072 return MI->getOperand(0).getReg();
1080 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1081 int &FrameIndex) const {
1082 const MachineMemOperand *Dummy;
1083 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1086 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1087 // This hook gets to expand COPY instructions before they become
1088 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1089 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1090 // changed into a VORR that can go down the NEON pipeline.
1091 if (!WidenVMOVS || !MI->isCopy())
1094 // Look for a copy between even S-registers. That is where we keep floats
1095 // when using NEON v2f32 instructions for f32 arithmetic.
1096 unsigned DstRegS = MI->getOperand(0).getReg();
1097 unsigned SrcRegS = MI->getOperand(1).getReg();
1098 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1101 const TargetRegisterInfo *TRI = &getRegisterInfo();
1102 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1104 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1106 if (!DstRegD || !SrcRegD)
1109 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1110 // legal if the COPY already defines the full DstRegD, and it isn't a
1111 // sub-register insertion.
1112 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1115 // A dead copy shouldn't show up here, but reject it just in case.
1116 if (MI->getOperand(0).isDead())
1119 // All clear, widen the COPY.
1120 DEBUG(dbgs() << "widening: " << *MI);
1122 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1123 // or some other super-register.
1124 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1125 if (ImpDefIdx != -1)
1126 MI->RemoveOperand(ImpDefIdx);
1128 // Change the opcode and operands.
1129 MI->setDesc(get(ARM::VMOVD));
1130 MI->getOperand(0).setReg(DstRegD);
1131 MI->getOperand(1).setReg(SrcRegD);
1132 AddDefaultPred(MachineInstrBuilder(MI));
1134 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1135 // register scavenger and machine verifier, so we need to indicate that we
1136 // are reading an undefined value from SrcRegD, but a proper value from
1138 MI->getOperand(1).setIsUndef();
1139 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1141 // SrcRegD may actually contain an unrelated value in the ssub_1
1142 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1143 if (MI->getOperand(1).isKill()) {
1144 MI->getOperand(1).setIsKill(false);
1145 MI->addRegisterKilled(SrcRegS, TRI, true);
1148 DEBUG(dbgs() << "replaced by: " << *MI);
1153 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1154 int FrameIx, uint64_t Offset,
1155 const MDNode *MDPtr,
1156 DebugLoc DL) const {
1157 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1158 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1162 /// Create a copy of a const pool value. Update CPI to the new index and return
1164 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1165 MachineConstantPool *MCP = MF.getConstantPool();
1166 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1168 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1169 assert(MCPE.isMachineConstantPoolEntry() &&
1170 "Expecting a machine constantpool entry!");
1171 ARMConstantPoolValue *ACPV =
1172 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1174 unsigned PCLabelId = AFI->createPICLabelUId();
1175 ARMConstantPoolValue *NewCPV = 0;
1176 // FIXME: The below assumes PIC relocation model and that the function
1177 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1178 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1179 // instructions, so that's probably OK, but is PIC always correct when
1181 if (ACPV->isGlobalValue())
1182 NewCPV = ARMConstantPoolConstant::
1183 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1185 else if (ACPV->isExtSymbol())
1186 NewCPV = ARMConstantPoolSymbol::
1187 Create(MF.getFunction()->getContext(),
1188 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1189 else if (ACPV->isBlockAddress())
1190 NewCPV = ARMConstantPoolConstant::
1191 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1192 ARMCP::CPBlockAddress, 4);
1193 else if (ACPV->isLSDA())
1194 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1196 else if (ACPV->isMachineBasicBlock())
1197 NewCPV = ARMConstantPoolMBB::
1198 Create(MF.getFunction()->getContext(),
1199 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1201 llvm_unreachable("Unexpected ARM constantpool value type!!");
1202 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1206 void ARMBaseInstrInfo::
1207 reMaterialize(MachineBasicBlock &MBB,
1208 MachineBasicBlock::iterator I,
1209 unsigned DestReg, unsigned SubIdx,
1210 const MachineInstr *Orig,
1211 const TargetRegisterInfo &TRI) const {
1212 unsigned Opcode = Orig->getOpcode();
1215 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1216 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1220 case ARM::tLDRpci_pic:
1221 case ARM::t2LDRpci_pic: {
1222 MachineFunction &MF = *MBB.getParent();
1223 unsigned CPI = Orig->getOperand(1).getIndex();
1224 unsigned PCLabelId = duplicateCPV(MF, CPI);
1225 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1227 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1228 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1235 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1236 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1237 switch(Orig->getOpcode()) {
1238 case ARM::tLDRpci_pic:
1239 case ARM::t2LDRpci_pic: {
1240 unsigned CPI = Orig->getOperand(1).getIndex();
1241 unsigned PCLabelId = duplicateCPV(MF, CPI);
1242 Orig->getOperand(1).setIndex(CPI);
1243 Orig->getOperand(2).setImm(PCLabelId);
1250 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1251 const MachineInstr *MI1,
1252 const MachineRegisterInfo *MRI) const {
1253 int Opcode = MI0->getOpcode();
1254 if (Opcode == ARM::t2LDRpci ||
1255 Opcode == ARM::t2LDRpci_pic ||
1256 Opcode == ARM::tLDRpci ||
1257 Opcode == ARM::tLDRpci_pic ||
1258 Opcode == ARM::MOV_ga_dyn ||
1259 Opcode == ARM::MOV_ga_pcrel ||
1260 Opcode == ARM::MOV_ga_pcrel_ldr ||
1261 Opcode == ARM::t2MOV_ga_dyn ||
1262 Opcode == ARM::t2MOV_ga_pcrel) {
1263 if (MI1->getOpcode() != Opcode)
1265 if (MI0->getNumOperands() != MI1->getNumOperands())
1268 const MachineOperand &MO0 = MI0->getOperand(1);
1269 const MachineOperand &MO1 = MI1->getOperand(1);
1270 if (MO0.getOffset() != MO1.getOffset())
1273 if (Opcode == ARM::MOV_ga_dyn ||
1274 Opcode == ARM::MOV_ga_pcrel ||
1275 Opcode == ARM::MOV_ga_pcrel_ldr ||
1276 Opcode == ARM::t2MOV_ga_dyn ||
1277 Opcode == ARM::t2MOV_ga_pcrel)
1278 // Ignore the PC labels.
1279 return MO0.getGlobal() == MO1.getGlobal();
1281 const MachineFunction *MF = MI0->getParent()->getParent();
1282 const MachineConstantPool *MCP = MF->getConstantPool();
1283 int CPI0 = MO0.getIndex();
1284 int CPI1 = MO1.getIndex();
1285 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1286 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1287 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1288 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1289 if (isARMCP0 && isARMCP1) {
1290 ARMConstantPoolValue *ACPV0 =
1291 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1292 ARMConstantPoolValue *ACPV1 =
1293 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1294 return ACPV0->hasSameValue(ACPV1);
1295 } else if (!isARMCP0 && !isARMCP1) {
1296 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1299 } else if (Opcode == ARM::PICLDR) {
1300 if (MI1->getOpcode() != Opcode)
1302 if (MI0->getNumOperands() != MI1->getNumOperands())
1305 unsigned Addr0 = MI0->getOperand(1).getReg();
1306 unsigned Addr1 = MI1->getOperand(1).getReg();
1307 if (Addr0 != Addr1) {
1309 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1310 !TargetRegisterInfo::isVirtualRegister(Addr1))
1313 // This assumes SSA form.
1314 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1315 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1316 // Check if the loaded value, e.g. a constantpool of a global address, are
1318 if (!produceSameValue(Def0, Def1, MRI))
1322 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1323 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1324 const MachineOperand &MO0 = MI0->getOperand(i);
1325 const MachineOperand &MO1 = MI1->getOperand(i);
1326 if (!MO0.isIdenticalTo(MO1))
1332 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1335 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1336 /// determine if two loads are loading from the same base address. It should
1337 /// only return true if the base pointers are the same and the only differences
1338 /// between the two addresses is the offset. It also returns the offsets by
1340 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1342 int64_t &Offset2) const {
1343 // Don't worry about Thumb: just ARM and Thumb2.
1344 if (Subtarget.isThumb1Only()) return false;
1346 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1349 switch (Load1->getMachineOpcode()) {
1362 case ARM::t2LDRSHi8:
1364 case ARM::t2LDRSHi12:
1368 switch (Load2->getMachineOpcode()) {
1381 case ARM::t2LDRSHi8:
1383 case ARM::t2LDRSHi12:
1387 // Check if base addresses and chain operands match.
1388 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1389 Load1->getOperand(4) != Load2->getOperand(4))
1392 // Index should be Reg0.
1393 if (Load1->getOperand(3) != Load2->getOperand(3))
1396 // Determine the offsets.
1397 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1398 isa<ConstantSDNode>(Load2->getOperand(1))) {
1399 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1400 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1407 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1408 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1409 /// be scheduled togther. On some targets if two loads are loading from
1410 /// addresses in the same cache line, it's better if they are scheduled
1411 /// together. This function takes two integers that represent the load offsets
1412 /// from the common base address. It returns true if it decides it's desirable
1413 /// to schedule the two loads together. "NumLoads" is the number of loads that
1414 /// have already been scheduled after Load1.
1415 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1416 int64_t Offset1, int64_t Offset2,
1417 unsigned NumLoads) const {
1418 // Don't worry about Thumb: just ARM and Thumb2.
1419 if (Subtarget.isThumb1Only()) return false;
1421 assert(Offset2 > Offset1);
1423 if ((Offset2 - Offset1) / 8 > 64)
1426 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1427 return false; // FIXME: overly conservative?
1429 // Four loads in a row should be sufficient.
1436 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1437 const MachineBasicBlock *MBB,
1438 const MachineFunction &MF) const {
1439 // Debug info is never a scheduling boundary. It's necessary to be explicit
1440 // due to the special treatment of IT instructions below, otherwise a
1441 // dbg_value followed by an IT will result in the IT instruction being
1442 // considered a scheduling hazard, which is wrong. It should be the actual
1443 // instruction preceding the dbg_value instruction(s), just like it is
1444 // when debug info is not present.
1445 if (MI->isDebugValue())
1448 // Terminators and labels can't be scheduled around.
1449 if (MI->isTerminator() || MI->isLabel())
1452 // Treat the start of the IT block as a scheduling boundary, but schedule
1453 // t2IT along with all instructions following it.
1454 // FIXME: This is a big hammer. But the alternative is to add all potential
1455 // true and anti dependencies to IT block instructions as implicit operands
1456 // to the t2IT instruction. The added compile time and complexity does not
1458 MachineBasicBlock::const_iterator I = MI;
1459 // Make sure to skip any dbg_value instructions
1460 while (++I != MBB->end() && I->isDebugValue())
1462 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1465 // Don't attempt to schedule around any instruction that defines
1466 // a stack-oriented pointer, as it's unlikely to be profitable. This
1467 // saves compile time, because it doesn't require every single
1468 // stack slot reference to depend on the instruction that does the
1470 // Calls don't actually change the stack pointer, even if they have imp-defs.
1471 // No ARM calling conventions change the stack pointer. (X86 calling
1472 // conventions sometimes do).
1473 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1479 bool ARMBaseInstrInfo::
1480 isProfitableToIfCvt(MachineBasicBlock &MBB,
1481 unsigned NumCycles, unsigned ExtraPredCycles,
1482 const BranchProbability &Probability) const {
1486 // Attempt to estimate the relative costs of predication versus branching.
1487 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1488 UnpredCost /= Probability.getDenominator();
1489 UnpredCost += 1; // The branch itself
1490 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1492 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1495 bool ARMBaseInstrInfo::
1496 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1497 unsigned TCycles, unsigned TExtra,
1498 MachineBasicBlock &FMBB,
1499 unsigned FCycles, unsigned FExtra,
1500 const BranchProbability &Probability) const {
1501 if (!TCycles || !FCycles)
1504 // Attempt to estimate the relative costs of predication versus branching.
1505 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1506 TUnpredCost /= Probability.getDenominator();
1508 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1509 unsigned FUnpredCost = Comp * FCycles;
1510 FUnpredCost /= Probability.getDenominator();
1512 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1513 UnpredCost += 1; // The branch itself
1514 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1516 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1519 /// getInstrPredicate - If instruction is predicated, returns its predicate
1520 /// condition, otherwise returns AL. It also returns the condition code
1521 /// register by reference.
1523 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1524 int PIdx = MI->findFirstPredOperandIdx();
1530 PredReg = MI->getOperand(PIdx+1).getReg();
1531 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1535 int llvm::getMatchingCondBranchOpcode(int Opc) {
1540 if (Opc == ARM::t2B)
1543 llvm_unreachable("Unknown unconditional branch opcode!");
1546 /// commuteInstruction - Handle commutable instructions.
1548 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1549 switch (MI->getOpcode()) {
1551 case ARM::t2MOVCCr: {
1552 // MOVCC can be commuted by inverting the condition.
1553 unsigned PredReg = 0;
1554 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1555 // MOVCC AL can't be inverted. Shouldn't happen.
1556 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1558 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1561 // After swapping the MOVCC operands, also invert the condition.
1562 MI->getOperand(MI->findFirstPredOperandIdx())
1563 .setImm(ARMCC::getOppositeCondition(CC));
1567 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1570 /// Identify instructions that can be folded into a MOVCC instruction, and
1571 /// return the corresponding opcode for the predicated pseudo-instruction.
1572 static unsigned canFoldIntoMOVCC(unsigned Reg, MachineInstr *&MI,
1573 const MachineRegisterInfo &MRI) {
1574 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1576 if (!MRI.hasOneNonDBGUse(Reg))
1578 MI = MRI.getVRegDef(Reg);
1581 // Check if MI has any non-dead defs or physreg uses. This also detects
1582 // predicated instructions which will be reading CPSR.
1583 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1584 const MachineOperand &MO = MI->getOperand(i);
1585 // Reject frame index operands, PEI can't handle the predicated pseudos.
1586 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1590 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1592 if (MO.isDef() && !MO.isDead())
1595 switch (MI->getOpcode()) {
1597 case ARM::ANDri: return ARM::ANDCCri;
1598 case ARM::ANDrr: return ARM::ANDCCrr;
1599 case ARM::ANDrsi: return ARM::ANDCCrsi;
1600 case ARM::ANDrsr: return ARM::ANDCCrsr;
1601 case ARM::t2ANDri: return ARM::t2ANDCCri;
1602 case ARM::t2ANDrr: return ARM::t2ANDCCrr;
1603 case ARM::t2ANDrs: return ARM::t2ANDCCrs;
1604 case ARM::EORri: return ARM::EORCCri;
1605 case ARM::EORrr: return ARM::EORCCrr;
1606 case ARM::EORrsi: return ARM::EORCCrsi;
1607 case ARM::EORrsr: return ARM::EORCCrsr;
1608 case ARM::t2EORri: return ARM::t2EORCCri;
1609 case ARM::t2EORrr: return ARM::t2EORCCrr;
1610 case ARM::t2EORrs: return ARM::t2EORCCrs;
1611 case ARM::ORRri: return ARM::ORRCCri;
1612 case ARM::ORRrr: return ARM::ORRCCrr;
1613 case ARM::ORRrsi: return ARM::ORRCCrsi;
1614 case ARM::ORRrsr: return ARM::ORRCCrsr;
1615 case ARM::t2ORRri: return ARM::t2ORRCCri;
1616 case ARM::t2ORRrr: return ARM::t2ORRCCrr;
1617 case ARM::t2ORRrs: return ARM::t2ORRCCrs;
1620 case ARM::ADDri: return ARM::ADDCCri;
1621 case ARM::ADDrr: return ARM::ADDCCrr;
1622 case ARM::ADDrsi: return ARM::ADDCCrsi;
1623 case ARM::ADDrsr: return ARM::ADDCCrsr;
1624 case ARM::SUBri: return ARM::SUBCCri;
1625 case ARM::SUBrr: return ARM::SUBCCrr;
1626 case ARM::SUBrsi: return ARM::SUBCCrsi;
1627 case ARM::SUBrsr: return ARM::SUBCCrsr;
1630 case ARM::t2ADDri: return ARM::t2ADDCCri;
1631 case ARM::t2ADDri12: return ARM::t2ADDCCri12;
1632 case ARM::t2ADDrr: return ARM::t2ADDCCrr;
1633 case ARM::t2ADDrs: return ARM::t2ADDCCrs;
1634 case ARM::t2SUBri: return ARM::t2SUBCCri;
1635 case ARM::t2SUBri12: return ARM::t2SUBCCri12;
1636 case ARM::t2SUBrr: return ARM::t2SUBCCrr;
1637 case ARM::t2SUBrs: return ARM::t2SUBCCrs;
1641 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1642 SmallVectorImpl<MachineOperand> &Cond,
1643 unsigned &TrueOp, unsigned &FalseOp,
1644 bool &Optimizable) const {
1645 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1646 "Unknown select instruction");
1651 // 3: Condition code.
1655 Cond.push_back(MI->getOperand(3));
1656 Cond.push_back(MI->getOperand(4));
1657 // We can always fold a def.
1662 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1663 bool PreferFalse) const {
1664 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1665 "Unknown select instruction");
1666 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1667 MachineInstr *DefMI = 0;
1668 unsigned Opc = canFoldIntoMOVCC(MI->getOperand(2).getReg(), DefMI, MRI);
1671 Opc = canFoldIntoMOVCC(MI->getOperand(1).getReg(), DefMI, MRI);
1675 // Create a new predicated version of DefMI.
1676 // Rfalse is the first use.
1677 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1678 get(Opc), MI->getOperand(0).getReg())
1679 .addOperand(MI->getOperand(Invert ? 2 : 1));
1681 // Copy all the DefMI operands, excluding its (null) predicate.
1682 const MCInstrDesc &DefDesc = DefMI->getDesc();
1683 for (unsigned i = 1, e = DefDesc.getNumOperands();
1684 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1685 NewMI.addOperand(DefMI->getOperand(i));
1687 unsigned CondCode = MI->getOperand(3).getImm();
1689 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1691 NewMI.addImm(CondCode);
1692 NewMI.addOperand(MI->getOperand(4));
1694 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1695 if (NewMI->hasOptionalDef())
1696 AddDefaultCC(NewMI);
1698 // The caller will erase MI, but not DefMI.
1699 DefMI->eraseFromParent();
1703 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1704 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1707 /// This will go away once we can teach tblgen how to set the optional CPSR def
1709 struct AddSubFlagsOpcodePair {
1711 uint16_t MachineOpc;
1714 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1715 {ARM::ADDSri, ARM::ADDri},
1716 {ARM::ADDSrr, ARM::ADDrr},
1717 {ARM::ADDSrsi, ARM::ADDrsi},
1718 {ARM::ADDSrsr, ARM::ADDrsr},
1720 {ARM::SUBSri, ARM::SUBri},
1721 {ARM::SUBSrr, ARM::SUBrr},
1722 {ARM::SUBSrsi, ARM::SUBrsi},
1723 {ARM::SUBSrsr, ARM::SUBrsr},
1725 {ARM::RSBSri, ARM::RSBri},
1726 {ARM::RSBSrsi, ARM::RSBrsi},
1727 {ARM::RSBSrsr, ARM::RSBrsr},
1729 {ARM::t2ADDSri, ARM::t2ADDri},
1730 {ARM::t2ADDSrr, ARM::t2ADDrr},
1731 {ARM::t2ADDSrs, ARM::t2ADDrs},
1733 {ARM::t2SUBSri, ARM::t2SUBri},
1734 {ARM::t2SUBSrr, ARM::t2SUBrr},
1735 {ARM::t2SUBSrs, ARM::t2SUBrs},
1737 {ARM::t2RSBSri, ARM::t2RSBri},
1738 {ARM::t2RSBSrs, ARM::t2RSBrs},
1741 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1742 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1743 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1744 return AddSubFlagsOpcodeMap[i].MachineOpc;
1748 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1749 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1750 unsigned DestReg, unsigned BaseReg, int NumBytes,
1751 ARMCC::CondCodes Pred, unsigned PredReg,
1752 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1753 bool isSub = NumBytes < 0;
1754 if (isSub) NumBytes = -NumBytes;
1757 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1758 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1759 assert(ThisVal && "Didn't extract field correctly");
1761 // We will handle these bits from offset, clear them.
1762 NumBytes &= ~ThisVal;
1764 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1766 // Build the new ADD / SUB.
1767 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1768 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1769 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1770 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1771 .setMIFlags(MIFlags);
1776 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1777 unsigned FrameReg, int &Offset,
1778 const ARMBaseInstrInfo &TII) {
1779 unsigned Opcode = MI.getOpcode();
1780 const MCInstrDesc &Desc = MI.getDesc();
1781 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1784 // Memory operands in inline assembly always use AddrMode2.
1785 if (Opcode == ARM::INLINEASM)
1786 AddrMode = ARMII::AddrMode2;
1788 if (Opcode == ARM::ADDri) {
1789 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1791 // Turn it into a move.
1792 MI.setDesc(TII.get(ARM::MOVr));
1793 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1794 MI.RemoveOperand(FrameRegIdx+1);
1797 } else if (Offset < 0) {
1800 MI.setDesc(TII.get(ARM::SUBri));
1803 // Common case: small offset, fits into instruction.
1804 if (ARM_AM::getSOImmVal(Offset) != -1) {
1805 // Replace the FrameIndex with sp / fp
1806 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1807 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1812 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1814 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1815 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1817 // We will handle these bits from offset, clear them.
1818 Offset &= ~ThisImmVal;
1820 // Get the properly encoded SOImmVal field.
1821 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1822 "Bit extraction didn't work?");
1823 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1825 unsigned ImmIdx = 0;
1827 unsigned NumBits = 0;
1830 case ARMII::AddrMode_i12: {
1831 ImmIdx = FrameRegIdx + 1;
1832 InstrOffs = MI.getOperand(ImmIdx).getImm();
1836 case ARMII::AddrMode2: {
1837 ImmIdx = FrameRegIdx+2;
1838 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1839 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1844 case ARMII::AddrMode3: {
1845 ImmIdx = FrameRegIdx+2;
1846 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1847 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1852 case ARMII::AddrMode4:
1853 case ARMII::AddrMode6:
1854 // Can't fold any offset even if it's zero.
1856 case ARMII::AddrMode5: {
1857 ImmIdx = FrameRegIdx+1;
1858 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1859 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1866 llvm_unreachable("Unsupported addressing mode!");
1869 Offset += InstrOffs * Scale;
1870 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1876 // Attempt to fold address comp. if opcode has offset bits
1878 // Common case: small offset, fits into instruction.
1879 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1880 int ImmedOffset = Offset / Scale;
1881 unsigned Mask = (1 << NumBits) - 1;
1882 if ((unsigned)Offset <= Mask * Scale) {
1883 // Replace the FrameIndex with sp
1884 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1885 // FIXME: When addrmode2 goes away, this will simplify (like the
1886 // T2 version), as the LDR.i12 versions don't need the encoding
1887 // tricks for the offset value.
1889 if (AddrMode == ARMII::AddrMode_i12)
1890 ImmedOffset = -ImmedOffset;
1892 ImmedOffset |= 1 << NumBits;
1894 ImmOp.ChangeToImmediate(ImmedOffset);
1899 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1900 ImmedOffset = ImmedOffset & Mask;
1902 if (AddrMode == ARMII::AddrMode_i12)
1903 ImmedOffset = -ImmedOffset;
1905 ImmedOffset |= 1 << NumBits;
1907 ImmOp.ChangeToImmediate(ImmedOffset);
1908 Offset &= ~(Mask*Scale);
1912 Offset = (isSub) ? -Offset : Offset;
1916 /// analyzeCompare - For a comparison instruction, return the source registers
1917 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1918 /// compares against in CmpValue. Return true if the comparison instruction
1919 /// can be analyzed.
1920 bool ARMBaseInstrInfo::
1921 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1922 int &CmpMask, int &CmpValue) const {
1923 switch (MI->getOpcode()) {
1927 SrcReg = MI->getOperand(0).getReg();
1930 CmpValue = MI->getOperand(1).getImm();
1934 SrcReg = MI->getOperand(0).getReg();
1935 SrcReg2 = MI->getOperand(1).getReg();
1941 SrcReg = MI->getOperand(0).getReg();
1943 CmpMask = MI->getOperand(1).getImm();
1951 /// isSuitableForMask - Identify a suitable 'and' instruction that
1952 /// operates on the given source register and applies the same mask
1953 /// as a 'tst' instruction. Provide a limited look-through for copies.
1954 /// When successful, MI will hold the found instruction.
1955 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1956 int CmpMask, bool CommonUse) {
1957 switch (MI->getOpcode()) {
1960 if (CmpMask != MI->getOperand(2).getImm())
1962 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1966 // Walk down one instruction which is potentially an 'and'.
1967 const MachineInstr &Copy = *MI;
1968 MachineBasicBlock::iterator AND(
1969 llvm::next(MachineBasicBlock::iterator(MI)));
1970 if (AND == MI->getParent()->end()) return false;
1972 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1980 /// getSwappedCondition - assume the flags are set by MI(a,b), return
1981 /// the condition code if we modify the instructions such that flags are
1983 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
1985 default: return ARMCC::AL;
1986 case ARMCC::EQ: return ARMCC::EQ;
1987 case ARMCC::NE: return ARMCC::NE;
1988 case ARMCC::HS: return ARMCC::LS;
1989 case ARMCC::LO: return ARMCC::HI;
1990 case ARMCC::HI: return ARMCC::LO;
1991 case ARMCC::LS: return ARMCC::HS;
1992 case ARMCC::GE: return ARMCC::LE;
1993 case ARMCC::LT: return ARMCC::GT;
1994 case ARMCC::GT: return ARMCC::LT;
1995 case ARMCC::LE: return ARMCC::GE;
1999 /// isRedundantFlagInstr - check whether the first instruction, whose only
2000 /// purpose is to update flags, can be made redundant.
2001 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2002 /// CMPri can be made redundant by SUBri if the operands are the same.
2003 /// This function can be extended later on.
2004 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2005 unsigned SrcReg2, int ImmValue,
2007 if ((CmpI->getOpcode() == ARM::CMPrr ||
2008 CmpI->getOpcode() == ARM::t2CMPrr) &&
2009 (OI->getOpcode() == ARM::SUBrr ||
2010 OI->getOpcode() == ARM::t2SUBrr) &&
2011 ((OI->getOperand(1).getReg() == SrcReg &&
2012 OI->getOperand(2).getReg() == SrcReg2) ||
2013 (OI->getOperand(1).getReg() == SrcReg2 &&
2014 OI->getOperand(2).getReg() == SrcReg)))
2017 if ((CmpI->getOpcode() == ARM::CMPri ||
2018 CmpI->getOpcode() == ARM::t2CMPri) &&
2019 (OI->getOpcode() == ARM::SUBri ||
2020 OI->getOpcode() == ARM::t2SUBri) &&
2021 OI->getOperand(1).getReg() == SrcReg &&
2022 OI->getOperand(2).getImm() == ImmValue)
2027 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2028 /// comparison into one that sets the zero bit in the flags register;
2029 /// Remove a redundant Compare instruction if an earlier instruction can set the
2030 /// flags in the same way as Compare.
2031 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2032 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2033 /// condition code of instructions which use the flags.
2034 bool ARMBaseInstrInfo::
2035 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2036 int CmpMask, int CmpValue,
2037 const MachineRegisterInfo *MRI) const {
2038 // Get the unique definition of SrcReg.
2039 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2040 if (!MI) return false;
2042 // Masked compares sometimes use the same register as the corresponding 'and'.
2043 if (CmpMask != ~0) {
2044 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
2046 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2047 UE = MRI->use_end(); UI != UE; ++UI) {
2048 if (UI->getParent() != CmpInstr->getParent()) continue;
2049 MachineInstr *PotentialAND = &*UI;
2050 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
2055 if (!MI) return false;
2059 // Get ready to iterate backward from CmpInstr.
2060 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2061 B = CmpInstr->getParent()->begin();
2063 // Early exit if CmpInstr is at the beginning of the BB.
2064 if (I == B) return false;
2066 // There are two possible candidates which can be changed to set CPSR:
2067 // One is MI, the other is a SUB instruction.
2068 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2069 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2070 MachineInstr *Sub = NULL;
2072 // MI is not a candidate for CMPrr.
2074 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2075 // Conservatively refuse to convert an instruction which isn't in the same
2076 // BB as the comparison.
2077 // For CMPri, we need to check Sub, thus we can't return here.
2078 if (CmpInstr->getOpcode() == ARM::CMPri ||
2079 CmpInstr->getOpcode() == ARM::t2CMPri)
2085 // Check that CPSR isn't set between the comparison instruction and the one we
2086 // want to change. At the same time, search for Sub.
2087 const TargetRegisterInfo *TRI = &getRegisterInfo();
2089 for (; I != E; --I) {
2090 const MachineInstr &Instr = *I;
2092 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2093 Instr.readsRegister(ARM::CPSR, TRI))
2094 // This instruction modifies or uses CPSR after the one we want to
2095 // change. We can't do this transformation.
2098 // Check whether CmpInstr can be made redundant by the current instruction.
2099 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2105 // The 'and' is below the comparison instruction.
2109 // Return false if no candidates exist.
2113 // The single candidate is called MI.
2116 switch (MI->getOpcode()) {
2150 case ARM::t2EORri: {
2151 // Scan forward for the use of CPSR
2152 // When checking against MI: if it's a conditional code requires
2153 // checking of V bit, then this is not safe to do.
2154 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2155 // If we are done with the basic block, we need to check whether CPSR is
2157 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2159 bool isSafe = false;
2161 E = CmpInstr->getParent()->end();
2162 while (!isSafe && ++I != E) {
2163 const MachineInstr &Instr = *I;
2164 for (unsigned IO = 0, EO = Instr.getNumOperands();
2165 !isSafe && IO != EO; ++IO) {
2166 const MachineOperand &MO = Instr.getOperand(IO);
2167 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2171 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2177 // Condition code is after the operand before CPSR.
2178 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2180 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2181 if (NewCC == ARMCC::AL)
2183 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2184 // on CMP needs to be updated to be based on SUB.
2185 // Push the condition code operands to OperandsToUpdate.
2186 // If it is safe to remove CmpInstr, the condition code of these
2187 // operands will be modified.
2188 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2189 Sub->getOperand(2).getReg() == SrcReg)
2190 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2196 // CPSR can be used multiple times, we should continue.
2209 // If CPSR is not killed nor re-defined, we should check whether it is
2210 // live-out. If it is live-out, do not optimize.
2212 MachineBasicBlock *MBB = CmpInstr->getParent();
2213 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2214 SE = MBB->succ_end(); SI != SE; ++SI)
2215 if ((*SI)->isLiveIn(ARM::CPSR))
2219 // Toggle the optional operand to CPSR.
2220 MI->getOperand(5).setReg(ARM::CPSR);
2221 MI->getOperand(5).setIsDef(true);
2222 CmpInstr->eraseFromParent();
2224 // Modify the condition code of operands in OperandsToUpdate.
2225 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2226 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2227 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2228 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2236 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2237 MachineInstr *DefMI, unsigned Reg,
2238 MachineRegisterInfo *MRI) const {
2239 // Fold large immediates into add, sub, or, xor.
2240 unsigned DefOpc = DefMI->getOpcode();
2241 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2243 if (!DefMI->getOperand(1).isImm())
2244 // Could be t2MOVi32imm <ga:xx>
2247 if (!MRI->hasOneNonDBGUse(Reg))
2250 const MCInstrDesc &DefMCID = DefMI->getDesc();
2251 if (DefMCID.hasOptionalDef()) {
2252 unsigned NumOps = DefMCID.getNumOperands();
2253 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2254 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2255 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2260 const MCInstrDesc &UseMCID = UseMI->getDesc();
2261 if (UseMCID.hasOptionalDef()) {
2262 unsigned NumOps = UseMCID.getNumOperands();
2263 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2264 // If the instruction sets the flag, do not attempt this optimization
2265 // since it may change the semantics of the code.
2269 unsigned UseOpc = UseMI->getOpcode();
2270 unsigned NewUseOpc = 0;
2271 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2272 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2273 bool Commute = false;
2275 default: return false;
2283 case ARM::t2EORrr: {
2284 Commute = UseMI->getOperand(2).getReg() != Reg;
2291 NewUseOpc = ARM::SUBri;
2297 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2299 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2300 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2303 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2304 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2305 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2309 case ARM::t2SUBrr: {
2313 NewUseOpc = ARM::t2SUBri;
2318 case ARM::t2EORrr: {
2319 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2321 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2322 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2325 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2326 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2327 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2335 unsigned OpIdx = Commute ? 2 : 1;
2336 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2337 bool isKill = UseMI->getOperand(OpIdx).isKill();
2338 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2339 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2340 UseMI, UseMI->getDebugLoc(),
2341 get(NewUseOpc), NewReg)
2342 .addReg(Reg1, getKillRegState(isKill))
2343 .addImm(SOImmValV1)));
2344 UseMI->setDesc(get(NewUseOpc));
2345 UseMI->getOperand(1).setReg(NewReg);
2346 UseMI->getOperand(1).setIsKill();
2347 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2348 DefMI->eraseFromParent();
2353 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2354 const MachineInstr *MI) const {
2355 if (!ItinData || ItinData->isEmpty())
2358 const MCInstrDesc &Desc = MI->getDesc();
2359 unsigned Class = Desc.getSchedClass();
2360 int ItinUOps = ItinData->getNumMicroOps(Class);
2364 unsigned Opc = MI->getOpcode();
2367 llvm_unreachable("Unexpected multi-uops instruction!");
2372 // The number of uOps for load / store multiple are determined by the number
2375 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2376 // same cycle. The scheduling for the first load / store must be done
2377 // separately by assuming the address is not 64-bit aligned.
2379 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2380 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2381 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2383 case ARM::VLDMDIA_UPD:
2384 case ARM::VLDMDDB_UPD:
2386 case ARM::VLDMSIA_UPD:
2387 case ARM::VLDMSDB_UPD:
2389 case ARM::VSTMDIA_UPD:
2390 case ARM::VSTMDDB_UPD:
2392 case ARM::VSTMSIA_UPD:
2393 case ARM::VSTMSDB_UPD: {
2394 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2395 return (NumRegs / 2) + (NumRegs % 2) + 1;
2398 case ARM::LDMIA_RET:
2403 case ARM::LDMIA_UPD:
2404 case ARM::LDMDA_UPD:
2405 case ARM::LDMDB_UPD:
2406 case ARM::LDMIB_UPD:
2411 case ARM::STMIA_UPD:
2412 case ARM::STMDA_UPD:
2413 case ARM::STMDB_UPD:
2414 case ARM::STMIB_UPD:
2416 case ARM::tLDMIA_UPD:
2417 case ARM::tSTMIA_UPD:
2421 case ARM::t2LDMIA_RET:
2424 case ARM::t2LDMIA_UPD:
2425 case ARM::t2LDMDB_UPD:
2428 case ARM::t2STMIA_UPD:
2429 case ARM::t2STMDB_UPD: {
2430 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2431 if (Subtarget.isCortexA8()) {
2434 // 4 registers would be issued: 2, 2.
2435 // 5 registers would be issued: 2, 2, 1.
2436 int A8UOps = (NumRegs / 2);
2440 } else if (Subtarget.isCortexA9()) {
2441 int A9UOps = (NumRegs / 2);
2442 // If there are odd number of registers or if it's not 64-bit aligned,
2443 // then it takes an extra AGU (Address Generation Unit) cycle.
2444 if ((NumRegs % 2) ||
2445 !MI->hasOneMemOperand() ||
2446 (*MI->memoperands_begin())->getAlignment() < 8)
2450 // Assume the worst.
2458 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2459 const MCInstrDesc &DefMCID,
2461 unsigned DefIdx, unsigned DefAlign) const {
2462 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2464 // Def is the address writeback.
2465 return ItinData->getOperandCycle(DefClass, DefIdx);
2468 if (Subtarget.isCortexA8()) {
2469 // (regno / 2) + (regno % 2) + 1
2470 DefCycle = RegNo / 2 + 1;
2473 } else if (Subtarget.isCortexA9()) {
2475 bool isSLoad = false;
2477 switch (DefMCID.getOpcode()) {
2480 case ARM::VLDMSIA_UPD:
2481 case ARM::VLDMSDB_UPD:
2486 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2487 // then it takes an extra cycle.
2488 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2491 // Assume the worst.
2492 DefCycle = RegNo + 2;
2499 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2500 const MCInstrDesc &DefMCID,
2502 unsigned DefIdx, unsigned DefAlign) const {
2503 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2505 // Def is the address writeback.
2506 return ItinData->getOperandCycle(DefClass, DefIdx);
2509 if (Subtarget.isCortexA8()) {
2510 // 4 registers would be issued: 1, 2, 1.
2511 // 5 registers would be issued: 1, 2, 2.
2512 DefCycle = RegNo / 2;
2515 // Result latency is issue cycle + 2: E2.
2517 } else if (Subtarget.isCortexA9()) {
2518 DefCycle = (RegNo / 2);
2519 // If there are odd number of registers or if it's not 64-bit aligned,
2520 // then it takes an extra AGU (Address Generation Unit) cycle.
2521 if ((RegNo % 2) || DefAlign < 8)
2523 // Result latency is AGU cycles + 2.
2526 // Assume the worst.
2527 DefCycle = RegNo + 2;
2534 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2535 const MCInstrDesc &UseMCID,
2537 unsigned UseIdx, unsigned UseAlign) const {
2538 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2540 return ItinData->getOperandCycle(UseClass, UseIdx);
2543 if (Subtarget.isCortexA8()) {
2544 // (regno / 2) + (regno % 2) + 1
2545 UseCycle = RegNo / 2 + 1;
2548 } else if (Subtarget.isCortexA9()) {
2550 bool isSStore = false;
2552 switch (UseMCID.getOpcode()) {
2555 case ARM::VSTMSIA_UPD:
2556 case ARM::VSTMSDB_UPD:
2561 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2562 // then it takes an extra cycle.
2563 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2566 // Assume the worst.
2567 UseCycle = RegNo + 2;
2574 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2575 const MCInstrDesc &UseMCID,
2577 unsigned UseIdx, unsigned UseAlign) const {
2578 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2580 return ItinData->getOperandCycle(UseClass, UseIdx);
2583 if (Subtarget.isCortexA8()) {
2584 UseCycle = RegNo / 2;
2589 } else if (Subtarget.isCortexA9()) {
2590 UseCycle = (RegNo / 2);
2591 // If there are odd number of registers or if it's not 64-bit aligned,
2592 // then it takes an extra AGU (Address Generation Unit) cycle.
2593 if ((RegNo % 2) || UseAlign < 8)
2596 // Assume the worst.
2603 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2604 const MCInstrDesc &DefMCID,
2605 unsigned DefIdx, unsigned DefAlign,
2606 const MCInstrDesc &UseMCID,
2607 unsigned UseIdx, unsigned UseAlign) const {
2608 unsigned DefClass = DefMCID.getSchedClass();
2609 unsigned UseClass = UseMCID.getSchedClass();
2611 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2612 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2614 // This may be a def / use of a variable_ops instruction, the operand
2615 // latency might be determinable dynamically. Let the target try to
2618 bool LdmBypass = false;
2619 switch (DefMCID.getOpcode()) {
2621 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2625 case ARM::VLDMDIA_UPD:
2626 case ARM::VLDMDDB_UPD:
2628 case ARM::VLDMSIA_UPD:
2629 case ARM::VLDMSDB_UPD:
2630 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2633 case ARM::LDMIA_RET:
2638 case ARM::LDMIA_UPD:
2639 case ARM::LDMDA_UPD:
2640 case ARM::LDMDB_UPD:
2641 case ARM::LDMIB_UPD:
2643 case ARM::tLDMIA_UPD:
2645 case ARM::t2LDMIA_RET:
2648 case ARM::t2LDMIA_UPD:
2649 case ARM::t2LDMDB_UPD:
2651 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2656 // We can't seem to determine the result latency of the def, assume it's 2.
2660 switch (UseMCID.getOpcode()) {
2662 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2666 case ARM::VSTMDIA_UPD:
2667 case ARM::VSTMDDB_UPD:
2669 case ARM::VSTMSIA_UPD:
2670 case ARM::VSTMSDB_UPD:
2671 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2678 case ARM::STMIA_UPD:
2679 case ARM::STMDA_UPD:
2680 case ARM::STMDB_UPD:
2681 case ARM::STMIB_UPD:
2682 case ARM::tSTMIA_UPD:
2687 case ARM::t2STMIA_UPD:
2688 case ARM::t2STMDB_UPD:
2689 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2694 // Assume it's read in the first stage.
2697 UseCycle = DefCycle - UseCycle + 1;
2700 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2701 // first def operand.
2702 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2705 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2706 UseClass, UseIdx)) {
2714 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2715 const MachineInstr *MI, unsigned Reg,
2716 unsigned &DefIdx, unsigned &Dist) {
2719 MachineBasicBlock::const_iterator I = MI; ++I;
2720 MachineBasicBlock::const_instr_iterator II =
2721 llvm::prior(I.getInstrIterator());
2722 assert(II->isInsideBundle() && "Empty bundle?");
2725 while (II->isInsideBundle()) {
2726 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2733 assert(Idx != -1 && "Cannot find bundled definition!");
2738 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2739 const MachineInstr *MI, unsigned Reg,
2740 unsigned &UseIdx, unsigned &Dist) {
2743 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2744 assert(II->isInsideBundle() && "Empty bundle?");
2745 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2747 // FIXME: This doesn't properly handle multiple uses.
2749 while (II != E && II->isInsideBundle()) {
2750 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2753 if (II->getOpcode() != ARM::t2IT)
2767 /// Return the number of cycles to add to (or subtract from) the static
2768 /// itinerary based on the def opcode and alignment. The caller will ensure that
2769 /// adjusted latency is at least one cycle.
2770 static int adjustDefLatency(const ARMSubtarget &Subtarget,
2771 const MachineInstr *DefMI,
2772 const MCInstrDesc *DefMCID, unsigned DefAlign) {
2774 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) {
2775 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2776 // variants are one cycle cheaper.
2777 switch (DefMCID->getOpcode()) {
2781 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2782 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2784 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2791 case ARM::t2LDRSHs: {
2792 // Thumb2 mode: lsl only.
2793 unsigned ShAmt = DefMI->getOperand(3).getImm();
2794 if (ShAmt == 0 || ShAmt == 2)
2801 if (DefAlign < 8 && Subtarget.isCortexA9()) {
2802 switch (DefMCID->getOpcode()) {
2808 case ARM::VLD1q8wb_fixed:
2809 case ARM::VLD1q16wb_fixed:
2810 case ARM::VLD1q32wb_fixed:
2811 case ARM::VLD1q64wb_fixed:
2812 case ARM::VLD1q8wb_register:
2813 case ARM::VLD1q16wb_register:
2814 case ARM::VLD1q32wb_register:
2815 case ARM::VLD1q64wb_register:
2822 case ARM::VLD2d8wb_fixed:
2823 case ARM::VLD2d16wb_fixed:
2824 case ARM::VLD2d32wb_fixed:
2825 case ARM::VLD2q8wb_fixed:
2826 case ARM::VLD2q16wb_fixed:
2827 case ARM::VLD2q32wb_fixed:
2828 case ARM::VLD2d8wb_register:
2829 case ARM::VLD2d16wb_register:
2830 case ARM::VLD2d32wb_register:
2831 case ARM::VLD2q8wb_register:
2832 case ARM::VLD2q16wb_register:
2833 case ARM::VLD2q32wb_register:
2838 case ARM::VLD3d8_UPD:
2839 case ARM::VLD3d16_UPD:
2840 case ARM::VLD3d32_UPD:
2841 case ARM::VLD1d64Twb_fixed:
2842 case ARM::VLD1d64Twb_register:
2843 case ARM::VLD3q8_UPD:
2844 case ARM::VLD3q16_UPD:
2845 case ARM::VLD3q32_UPD:
2850 case ARM::VLD4d8_UPD:
2851 case ARM::VLD4d16_UPD:
2852 case ARM::VLD4d32_UPD:
2853 case ARM::VLD1d64Qwb_fixed:
2854 case ARM::VLD1d64Qwb_register:
2855 case ARM::VLD4q8_UPD:
2856 case ARM::VLD4q16_UPD:
2857 case ARM::VLD4q32_UPD:
2858 case ARM::VLD1DUPq8:
2859 case ARM::VLD1DUPq16:
2860 case ARM::VLD1DUPq32:
2861 case ARM::VLD1DUPq8wb_fixed:
2862 case ARM::VLD1DUPq16wb_fixed:
2863 case ARM::VLD1DUPq32wb_fixed:
2864 case ARM::VLD1DUPq8wb_register:
2865 case ARM::VLD1DUPq16wb_register:
2866 case ARM::VLD1DUPq32wb_register:
2867 case ARM::VLD2DUPd8:
2868 case ARM::VLD2DUPd16:
2869 case ARM::VLD2DUPd32:
2870 case ARM::VLD2DUPd8wb_fixed:
2871 case ARM::VLD2DUPd16wb_fixed:
2872 case ARM::VLD2DUPd32wb_fixed:
2873 case ARM::VLD2DUPd8wb_register:
2874 case ARM::VLD2DUPd16wb_register:
2875 case ARM::VLD2DUPd32wb_register:
2876 case ARM::VLD4DUPd8:
2877 case ARM::VLD4DUPd16:
2878 case ARM::VLD4DUPd32:
2879 case ARM::VLD4DUPd8_UPD:
2880 case ARM::VLD4DUPd16_UPD:
2881 case ARM::VLD4DUPd32_UPD:
2883 case ARM::VLD1LNd16:
2884 case ARM::VLD1LNd32:
2885 case ARM::VLD1LNd8_UPD:
2886 case ARM::VLD1LNd16_UPD:
2887 case ARM::VLD1LNd32_UPD:
2889 case ARM::VLD2LNd16:
2890 case ARM::VLD2LNd32:
2891 case ARM::VLD2LNq16:
2892 case ARM::VLD2LNq32:
2893 case ARM::VLD2LNd8_UPD:
2894 case ARM::VLD2LNd16_UPD:
2895 case ARM::VLD2LNd32_UPD:
2896 case ARM::VLD2LNq16_UPD:
2897 case ARM::VLD2LNq32_UPD:
2899 case ARM::VLD4LNd16:
2900 case ARM::VLD4LNd32:
2901 case ARM::VLD4LNq16:
2902 case ARM::VLD4LNq32:
2903 case ARM::VLD4LNd8_UPD:
2904 case ARM::VLD4LNd16_UPD:
2905 case ARM::VLD4LNd32_UPD:
2906 case ARM::VLD4LNq16_UPD:
2907 case ARM::VLD4LNq32_UPD:
2908 // If the address is not 64-bit aligned, the latencies of these
2909 // instructions increases by one.
2920 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2921 const MachineInstr *DefMI, unsigned DefIdx,
2922 const MachineInstr *UseMI,
2923 unsigned UseIdx) const {
2924 // No operand latency. The caller may fall back to getInstrLatency.
2925 if (!ItinData || ItinData->isEmpty())
2928 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2929 unsigned Reg = DefMO.getReg();
2930 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2931 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2933 unsigned DefAdj = 0;
2934 if (DefMI->isBundle()) {
2935 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2936 DefMCID = &DefMI->getDesc();
2938 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2939 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
2943 unsigned UseAdj = 0;
2944 if (UseMI->isBundle()) {
2946 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2947 Reg, NewUseIdx, UseAdj);
2953 UseMCID = &UseMI->getDesc();
2956 if (Reg == ARM::CPSR) {
2957 if (DefMI->getOpcode() == ARM::FMSTAT) {
2958 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2959 return Subtarget.isCortexA9() ? 1 : 20;
2962 // CPSR set and branch can be paired in the same cycle.
2963 if (UseMI->isBranch())
2966 // Otherwise it takes the instruction latency (generally one).
2967 unsigned Latency = getInstrLatency(ItinData, DefMI);
2969 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2970 // its uses. Instructions which are otherwise scheduled between them may
2971 // incur a code size penalty (not able to use the CPSR setting 16-bit
2973 if (Latency > 0 && Subtarget.isThumb2()) {
2974 const MachineFunction *MF = DefMI->getParent()->getParent();
2975 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2981 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
2984 unsigned DefAlign = DefMI->hasOneMemOperand()
2985 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2986 unsigned UseAlign = UseMI->hasOneMemOperand()
2987 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2989 // Get the itinerary's latency if possible, and handle variable_ops.
2990 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2991 *UseMCID, UseIdx, UseAlign);
2992 // Unable to find operand latency. The caller may resort to getInstrLatency.
2996 // Adjust for IT block position.
2997 int Adj = DefAdj + UseAdj;
2999 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3000 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3001 if (Adj >= 0 || (int)Latency > -Adj) {
3002 return Latency + Adj;
3004 // Return the itinerary latency, which may be zero but not less than zero.
3009 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3010 SDNode *DefNode, unsigned DefIdx,
3011 SDNode *UseNode, unsigned UseIdx) const {
3012 if (!DefNode->isMachineOpcode())
3015 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3017 if (isZeroCost(DefMCID.Opcode))
3020 if (!ItinData || ItinData->isEmpty())
3021 return DefMCID.mayLoad() ? 3 : 1;
3023 if (!UseNode->isMachineOpcode()) {
3024 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3025 if (Subtarget.isCortexA9())
3026 return Latency <= 2 ? 1 : Latency - 1;
3028 return Latency <= 3 ? 1 : Latency - 2;
3031 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3032 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3033 unsigned DefAlign = !DefMN->memoperands_empty()
3034 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3035 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3036 unsigned UseAlign = !UseMN->memoperands_empty()
3037 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3038 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3039 UseMCID, UseIdx, UseAlign);
3042 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
3043 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3044 // variants are one cycle cheaper.
3045 switch (DefMCID.getOpcode()) {
3050 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3051 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3053 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3060 case ARM::t2LDRSHs: {
3061 // Thumb2 mode: lsl only.
3063 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3064 if (ShAmt == 0 || ShAmt == 2)
3071 if (DefAlign < 8 && Subtarget.isCortexA9())
3072 switch (DefMCID.getOpcode()) {
3078 case ARM::VLD1q8wb_register:
3079 case ARM::VLD1q16wb_register:
3080 case ARM::VLD1q32wb_register:
3081 case ARM::VLD1q64wb_register:
3082 case ARM::VLD1q8wb_fixed:
3083 case ARM::VLD1q16wb_fixed:
3084 case ARM::VLD1q32wb_fixed:
3085 case ARM::VLD1q64wb_fixed:
3089 case ARM::VLD2q8Pseudo:
3090 case ARM::VLD2q16Pseudo:
3091 case ARM::VLD2q32Pseudo:
3092 case ARM::VLD2d8wb_fixed:
3093 case ARM::VLD2d16wb_fixed:
3094 case ARM::VLD2d32wb_fixed:
3095 case ARM::VLD2q8PseudoWB_fixed:
3096 case ARM::VLD2q16PseudoWB_fixed:
3097 case ARM::VLD2q32PseudoWB_fixed:
3098 case ARM::VLD2d8wb_register:
3099 case ARM::VLD2d16wb_register:
3100 case ARM::VLD2d32wb_register:
3101 case ARM::VLD2q8PseudoWB_register:
3102 case ARM::VLD2q16PseudoWB_register:
3103 case ARM::VLD2q32PseudoWB_register:
3104 case ARM::VLD3d8Pseudo:
3105 case ARM::VLD3d16Pseudo:
3106 case ARM::VLD3d32Pseudo:
3107 case ARM::VLD1d64TPseudo:
3108 case ARM::VLD3d8Pseudo_UPD:
3109 case ARM::VLD3d16Pseudo_UPD:
3110 case ARM::VLD3d32Pseudo_UPD:
3111 case ARM::VLD3q8Pseudo_UPD:
3112 case ARM::VLD3q16Pseudo_UPD:
3113 case ARM::VLD3q32Pseudo_UPD:
3114 case ARM::VLD3q8oddPseudo:
3115 case ARM::VLD3q16oddPseudo:
3116 case ARM::VLD3q32oddPseudo:
3117 case ARM::VLD3q8oddPseudo_UPD:
3118 case ARM::VLD3q16oddPseudo_UPD:
3119 case ARM::VLD3q32oddPseudo_UPD:
3120 case ARM::VLD4d8Pseudo:
3121 case ARM::VLD4d16Pseudo:
3122 case ARM::VLD4d32Pseudo:
3123 case ARM::VLD1d64QPseudo:
3124 case ARM::VLD4d8Pseudo_UPD:
3125 case ARM::VLD4d16Pseudo_UPD:
3126 case ARM::VLD4d32Pseudo_UPD:
3127 case ARM::VLD4q8Pseudo_UPD:
3128 case ARM::VLD4q16Pseudo_UPD:
3129 case ARM::VLD4q32Pseudo_UPD:
3130 case ARM::VLD4q8oddPseudo:
3131 case ARM::VLD4q16oddPseudo:
3132 case ARM::VLD4q32oddPseudo:
3133 case ARM::VLD4q8oddPseudo_UPD:
3134 case ARM::VLD4q16oddPseudo_UPD:
3135 case ARM::VLD4q32oddPseudo_UPD:
3136 case ARM::VLD1DUPq8:
3137 case ARM::VLD1DUPq16:
3138 case ARM::VLD1DUPq32:
3139 case ARM::VLD1DUPq8wb_fixed:
3140 case ARM::VLD1DUPq16wb_fixed:
3141 case ARM::VLD1DUPq32wb_fixed:
3142 case ARM::VLD1DUPq8wb_register:
3143 case ARM::VLD1DUPq16wb_register:
3144 case ARM::VLD1DUPq32wb_register:
3145 case ARM::VLD2DUPd8:
3146 case ARM::VLD2DUPd16:
3147 case ARM::VLD2DUPd32:
3148 case ARM::VLD2DUPd8wb_fixed:
3149 case ARM::VLD2DUPd16wb_fixed:
3150 case ARM::VLD2DUPd32wb_fixed:
3151 case ARM::VLD2DUPd8wb_register:
3152 case ARM::VLD2DUPd16wb_register:
3153 case ARM::VLD2DUPd32wb_register:
3154 case ARM::VLD4DUPd8Pseudo:
3155 case ARM::VLD4DUPd16Pseudo:
3156 case ARM::VLD4DUPd32Pseudo:
3157 case ARM::VLD4DUPd8Pseudo_UPD:
3158 case ARM::VLD4DUPd16Pseudo_UPD:
3159 case ARM::VLD4DUPd32Pseudo_UPD:
3160 case ARM::VLD1LNq8Pseudo:
3161 case ARM::VLD1LNq16Pseudo:
3162 case ARM::VLD1LNq32Pseudo:
3163 case ARM::VLD1LNq8Pseudo_UPD:
3164 case ARM::VLD1LNq16Pseudo_UPD:
3165 case ARM::VLD1LNq32Pseudo_UPD:
3166 case ARM::VLD2LNd8Pseudo:
3167 case ARM::VLD2LNd16Pseudo:
3168 case ARM::VLD2LNd32Pseudo:
3169 case ARM::VLD2LNq16Pseudo:
3170 case ARM::VLD2LNq32Pseudo:
3171 case ARM::VLD2LNd8Pseudo_UPD:
3172 case ARM::VLD2LNd16Pseudo_UPD:
3173 case ARM::VLD2LNd32Pseudo_UPD:
3174 case ARM::VLD2LNq16Pseudo_UPD:
3175 case ARM::VLD2LNq32Pseudo_UPD:
3176 case ARM::VLD4LNd8Pseudo:
3177 case ARM::VLD4LNd16Pseudo:
3178 case ARM::VLD4LNd32Pseudo:
3179 case ARM::VLD4LNq16Pseudo:
3180 case ARM::VLD4LNq32Pseudo:
3181 case ARM::VLD4LNd8Pseudo_UPD:
3182 case ARM::VLD4LNd16Pseudo_UPD:
3183 case ARM::VLD4LNd32Pseudo_UPD:
3184 case ARM::VLD4LNq16Pseudo_UPD:
3185 case ARM::VLD4LNq32Pseudo_UPD:
3186 // If the address is not 64-bit aligned, the latencies of these
3187 // instructions increases by one.
3196 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
3197 const MachineInstr *DefMI, unsigned DefIdx,
3198 const MachineInstr *DepMI) const {
3199 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
3200 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
3203 // If the second MI is predicated, then there is an implicit use dependency.
3204 return getInstrLatency(ItinData, DefMI);
3207 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3208 const MachineInstr *MI,
3209 unsigned *PredCost) const {
3210 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3211 MI->isRegSequence() || MI->isImplicitDef())
3214 // An instruction scheduler typically runs on unbundled instructions, however
3215 // other passes may query the latency of a bundled instruction.
3216 if (MI->isBundle()) {
3217 unsigned Latency = 0;
3218 MachineBasicBlock::const_instr_iterator I = MI;
3219 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3220 while (++I != E && I->isInsideBundle()) {
3221 if (I->getOpcode() != ARM::t2IT)
3222 Latency += getInstrLatency(ItinData, I, PredCost);
3227 const MCInstrDesc &MCID = MI->getDesc();
3228 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3229 // When predicated, CPSR is an additional source operand for CPSR updating
3230 // instructions, this apparently increases their latencies.
3233 // Be sure to call getStageLatency for an empty itinerary in case it has a
3234 // valid MinLatency property.
3236 return MI->mayLoad() ? 3 : 1;
3238 unsigned Class = MCID.getSchedClass();
3240 // For instructions with variable uops, use uops as latency.
3241 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3242 return getNumMicroOps(ItinData, MI);
3244 // For the common case, fall back on the itinerary's latency.
3245 unsigned Latency = ItinData->getStageLatency(Class);
3247 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3248 unsigned DefAlign = MI->hasOneMemOperand()
3249 ? (*MI->memoperands_begin())->getAlignment() : 0;
3250 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3251 if (Adj >= 0 || (int)Latency > -Adj) {
3252 return Latency + Adj;
3257 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3258 SDNode *Node) const {
3259 if (!Node->isMachineOpcode())
3262 if (!ItinData || ItinData->isEmpty())
3265 unsigned Opcode = Node->getMachineOpcode();
3268 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3275 bool ARMBaseInstrInfo::
3276 hasHighOperandLatency(const InstrItineraryData *ItinData,
3277 const MachineRegisterInfo *MRI,
3278 const MachineInstr *DefMI, unsigned DefIdx,
3279 const MachineInstr *UseMI, unsigned UseIdx) const {
3280 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3281 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3282 if (Subtarget.isCortexA8() &&
3283 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3284 // CortexA8 VFP instructions are not pipelined.
3287 // Hoist VFP / NEON instructions with 4 or higher latency.
3288 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3291 Latency = getInstrLatency(ItinData, DefMI);
3294 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3295 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3298 bool ARMBaseInstrInfo::
3299 hasLowDefLatency(const InstrItineraryData *ItinData,
3300 const MachineInstr *DefMI, unsigned DefIdx) const {
3301 if (!ItinData || ItinData->isEmpty())
3304 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3305 if (DDomain == ARMII::DomainGeneral) {
3306 unsigned DefClass = DefMI->getDesc().getSchedClass();
3307 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3308 return (DefCycle != -1 && DefCycle <= 2);
3313 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3314 StringRef &ErrInfo) const {
3315 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3316 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3323 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3324 unsigned &AddSubOpc,
3325 bool &NegAcc, bool &HasLane) const {
3326 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3327 if (I == MLxEntryMap.end())
3330 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3331 MulOpc = Entry.MulOpc;
3332 AddSubOpc = Entry.AddSubOpc;
3333 NegAcc = Entry.NegAcc;
3334 HasLane = Entry.HasLane;
3338 //===----------------------------------------------------------------------===//
3339 // Execution domains.
3340 //===----------------------------------------------------------------------===//
3342 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3343 // and some can go down both. The vmov instructions go down the VFP pipeline,
3344 // but they can be changed to vorr equivalents that are executed by the NEON
3347 // We use the following execution domain numbering:
3355 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3357 std::pair<uint16_t, uint16_t>
3358 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3359 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3360 // if they are not predicated.
3361 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3362 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3364 // Cortex-A9 is particularly picky about mixing the two and wants these
3366 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3367 (MI->getOpcode() == ARM::VMOVRS ||
3368 MI->getOpcode() == ARM::VMOVSR))
3369 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3371 // No other instructions can be swizzled, so just determine their domain.
3372 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3374 if (Domain & ARMII::DomainNEON)
3375 return std::make_pair(ExeNEON, 0);
3377 // Certain instructions can go either way on Cortex-A8.
3378 // Treat them as NEON instructions.
3379 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3380 return std::make_pair(ExeNEON, 0);
3382 if (Domain & ARMII::DomainVFP)
3383 return std::make_pair(ExeVFP, 0);
3385 return std::make_pair(ExeGeneric, 0);
3389 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3390 unsigned DstReg, SrcReg, DReg;
3392 MachineInstrBuilder MIB(MI);
3393 const TargetRegisterInfo *TRI = &getRegisterInfo();
3395 switch (MI->getOpcode()) {
3397 llvm_unreachable("cannot handle opcode!");
3400 if (Domain != ExeNEON)
3403 // Zap the predicate operands.
3404 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3405 MI->RemoveOperand(3);
3406 MI->RemoveOperand(2);
3408 // Change to a VORRd which requires two identical use operands.
3409 MI->setDesc(get(ARM::VORRd));
3411 // Add the extra source operand and new predicates.
3412 // This will go before any implicit ops.
3413 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
3416 if (Domain != ExeNEON)
3418 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3420 DstReg = MI->getOperand(0).getReg();
3421 SrcReg = MI->getOperand(1).getReg();
3423 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, &ARM::DPRRegClass);
3425 if (DReg == ARM::NoRegister) {
3426 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_1, &ARM::DPRRegClass);
3428 assert(DReg && "S-register with no D super-register?");
3431 MI->RemoveOperand(3);
3432 MI->RemoveOperand(2);
3433 MI->RemoveOperand(1);
3435 MI->setDesc(get(ARM::VGETLNi32));
3439 MIB->getOperand(1).setIsUndef();
3440 MIB.addReg(SrcReg, RegState::Implicit);
3442 AddDefaultPred(MIB);
3445 if (Domain != ExeNEON)
3447 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3449 DstReg = MI->getOperand(0).getReg();
3450 SrcReg = MI->getOperand(1).getReg();
3451 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass);
3453 if (DReg == ARM::NoRegister) {
3454 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass);
3456 assert(DReg && "S-register with no D super-register?");
3458 isKill = MI->getOperand(0).isKill();
3460 MI->RemoveOperand(3);
3461 MI->RemoveOperand(2);
3462 MI->RemoveOperand(1);
3463 MI->RemoveOperand(0);
3465 MI->setDesc(get(ARM::VSETLNi32));
3466 MIB.addReg(DReg, RegState::Define);
3467 MIB.addReg(DReg, RegState::Undef);
3472 MIB->addRegisterKilled(DstReg, TRI, true);
3473 MIB->addRegisterDefined(DstReg, TRI);
3475 AddDefaultPred(MIB);
3481 bool ARMBaseInstrInfo::hasNOP() const {
3482 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;