1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineJumpTableInfo.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/BranchProbability.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 static cl::opt<unsigned>
53 SwiftPartialUpdateClearance("swift-partial-update-clearance",
54 cl::Hidden, cl::init(12),
55 cl::desc("Clearance before partial register updates"));
57 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
59 uint16_t MLxOpc; // MLA / MLS opcode
60 uint16_t MulOpc; // Expanded multiplication opcode
61 uint16_t AddSubOpc; // Expanded add / sub opcode
62 bool NegAcc; // True if the acc is negated before the add / sub.
63 bool HasLane; // True if instruction has an extra "lane" operand.
66 static const ARM_MLxEntry ARM_MLxTable[] = {
67 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
69 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
70 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
71 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
72 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
73 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
74 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
75 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
76 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
79 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
80 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
81 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
82 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
83 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
84 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
85 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
86 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
89 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
90 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
92 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
93 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
94 assert(false && "Duplicated entries?");
95 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
96 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
100 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
101 // currently defaults to no prepass hazard recognizer.
102 ScheduleHazardRecognizer *ARMBaseInstrInfo::
103 CreateTargetHazardRecognizer(const TargetMachine *TM,
104 const ScheduleDAG *DAG) const {
105 if (usePreRAHazardRecognizer()) {
106 const InstrItineraryData *II = TM->getInstrItineraryData();
107 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
109 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
112 ScheduleHazardRecognizer *ARMBaseInstrInfo::
113 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
114 const ScheduleDAG *DAG) const {
115 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
116 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
117 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
121 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
122 MachineBasicBlock::iterator &MBBI,
123 LiveVariables *LV) const {
124 // FIXME: Thumb2 support.
129 MachineInstr *MI = MBBI;
130 MachineFunction &MF = *MI->getParent()->getParent();
131 uint64_t TSFlags = MI->getDesc().TSFlags;
133 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
134 default: return NULL;
135 case ARMII::IndexModePre:
138 case ARMII::IndexModePost:
142 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
144 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
148 MachineInstr *UpdateMI = NULL;
149 MachineInstr *MemMI = NULL;
150 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
151 const MCInstrDesc &MCID = MI->getDesc();
152 unsigned NumOps = MCID.getNumOperands();
153 bool isLoad = !MI->mayStore();
154 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
155 const MachineOperand &Base = MI->getOperand(2);
156 const MachineOperand &Offset = MI->getOperand(NumOps-3);
157 unsigned WBReg = WB.getReg();
158 unsigned BaseReg = Base.getReg();
159 unsigned OffReg = Offset.getReg();
160 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
161 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
163 default: llvm_unreachable("Unknown indexed op!");
164 case ARMII::AddrMode2: {
165 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
166 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
168 if (ARM_AM::getSOImmVal(Amt) == -1)
169 // Can't encode it in a so_imm operand. This transformation will
170 // add more than 1 instruction. Abandon!
172 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
173 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
174 .addReg(BaseReg).addImm(Amt)
175 .addImm(Pred).addReg(0).addReg(0);
176 } else if (Amt != 0) {
177 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
178 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
181 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
182 .addImm(Pred).addReg(0).addReg(0);
184 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
186 .addReg(BaseReg).addReg(OffReg)
187 .addImm(Pred).addReg(0).addReg(0);
190 case ARMII::AddrMode3 : {
191 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
192 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
194 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
195 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
196 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
197 .addReg(BaseReg).addImm(Amt)
198 .addImm(Pred).addReg(0).addReg(0);
200 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
202 .addReg(BaseReg).addReg(OffReg)
203 .addImm(Pred).addReg(0).addReg(0);
208 std::vector<MachineInstr*> NewMIs;
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc), MI->getOperand(0).getReg())
213 .addReg(WBReg).addImm(0).addImm(Pred);
215 MemMI = BuildMI(MF, MI->getDebugLoc(),
216 get(MemOpc)).addReg(MI->getOperand(1).getReg())
217 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
218 NewMIs.push_back(MemMI);
219 NewMIs.push_back(UpdateMI);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc), MI->getOperand(0).getReg())
224 .addReg(BaseReg).addImm(0).addImm(Pred);
226 MemMI = BuildMI(MF, MI->getDebugLoc(),
227 get(MemOpc)).addReg(MI->getOperand(1).getReg())
228 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
230 UpdateMI->getOperand(0).setIsDead();
231 NewMIs.push_back(UpdateMI);
232 NewMIs.push_back(MemMI);
235 // Transfer LiveVariables states, kill / dead info.
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 MachineOperand &MO = MI->getOperand(i);
239 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
240 unsigned Reg = MO.getReg();
242 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
244 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
246 LV->addVirtualRegisterDead(Reg, NewMI);
248 if (MO.isUse() && MO.isKill()) {
249 for (unsigned j = 0; j < 2; ++j) {
250 // Look at the two new MI's in reverse order.
251 MachineInstr *NewMI = NewMIs[j];
252 if (!NewMI->readsRegister(Reg))
254 LV->addVirtualRegisterKilled(Reg, NewMI);
255 if (VI.removeKill(MI))
256 VI.Kills.push_back(NewMI);
264 MFI->insert(MBBI, NewMIs[1]);
265 MFI->insert(MBBI, NewMIs[0]);
271 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
272 MachineBasicBlock *&FBB,
273 SmallVectorImpl<MachineOperand> &Cond,
274 bool AllowModify) const {
275 // If the block has no terminators, it just falls into the block after it.
276 MachineBasicBlock::iterator I = MBB.end();
277 if (I == MBB.begin())
280 while (I->isDebugValue()) {
281 if (I == MBB.begin())
286 // Get the last instruction in the block.
287 MachineInstr *LastInst = I;
288 unsigned LastOpc = LastInst->getOpcode();
290 // Check if it's an indirect branch first, this should return 'unanalyzable'
291 // even if it's predicated.
292 if (isIndirectBranchOpcode(LastOpc))
295 if (!isUnpredicatedTerminator(I))
298 // If there is only one terminator instruction, process it.
299 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
300 if (isUncondBranchOpcode(LastOpc)) {
301 TBB = LastInst->getOperand(0).getMBB();
304 if (isCondBranchOpcode(LastOpc)) {
305 // Block ends with fall-through condbranch.
306 TBB = LastInst->getOperand(0).getMBB();
307 Cond.push_back(LastInst->getOperand(1));
308 Cond.push_back(LastInst->getOperand(2));
311 return true; // Can't handle indirect branch.
314 // Get the instruction before it if it is a terminator.
315 MachineInstr *SecondLastInst = I;
316 unsigned SecondLastOpc = SecondLastInst->getOpcode();
318 // If AllowModify is true and the block ends with two or more unconditional
319 // branches, delete all but the first unconditional branch.
320 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
321 while (isUncondBranchOpcode(SecondLastOpc)) {
322 LastInst->eraseFromParent();
323 LastInst = SecondLastInst;
324 LastOpc = LastInst->getOpcode();
325 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
326 // Return now the only terminator is an unconditional branch.
327 TBB = LastInst->getOperand(0).getMBB();
331 SecondLastOpc = SecondLastInst->getOpcode();
336 // If there are three terminators, we don't know what sort of block this is.
337 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
340 // If the block ends with a B and a Bcc, handle it.
341 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
343 Cond.push_back(SecondLastInst->getOperand(1));
344 Cond.push_back(SecondLastInst->getOperand(2));
345 FBB = LastInst->getOperand(0).getMBB();
349 // If the block ends with two unconditional branches, handle it. The second
350 // one is not executed, so remove it.
351 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
352 TBB = SecondLastInst->getOperand(0).getMBB();
355 I->eraseFromParent();
359 // ...likewise if it ends with a branch table followed by an unconditional
360 // branch. The branch folder can create these, and we must get rid of them for
361 // correctness of Thumb constant islands.
362 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
363 isIndirectBranchOpcode(SecondLastOpc)) &&
364 isUncondBranchOpcode(LastOpc)) {
367 I->eraseFromParent();
371 // Otherwise, can't handle this.
376 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
377 MachineBasicBlock::iterator I = MBB.end();
378 if (I == MBB.begin()) return 0;
380 while (I->isDebugValue()) {
381 if (I == MBB.begin())
385 if (!isUncondBranchOpcode(I->getOpcode()) &&
386 !isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
394 if (I == MBB.begin()) return 1;
396 if (!isCondBranchOpcode(I->getOpcode()))
399 // Remove the branch.
400 I->eraseFromParent();
405 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
406 MachineBasicBlock *FBB,
407 const SmallVectorImpl<MachineOperand> &Cond,
409 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
410 int BOpc = !AFI->isThumbFunction()
411 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
412 int BccOpc = !AFI->isThumbFunction()
413 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
414 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
416 // Shouldn't be a fall through.
417 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
418 assert((Cond.size() == 2 || Cond.size() == 0) &&
419 "ARM branch conditions have two components!");
422 if (Cond.empty()) { // Unconditional branch?
424 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
426 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
428 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
429 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
433 // Two-way conditional branch.
434 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
435 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
437 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
439 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
443 bool ARMBaseInstrInfo::
444 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
445 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
446 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
450 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
451 if (MI->isBundle()) {
452 MachineBasicBlock::const_instr_iterator I = MI;
453 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
454 while (++I != E && I->isInsideBundle()) {
455 int PIdx = I->findFirstPredOperandIdx();
456 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
462 int PIdx = MI->findFirstPredOperandIdx();
463 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
466 bool ARMBaseInstrInfo::
467 PredicateInstruction(MachineInstr *MI,
468 const SmallVectorImpl<MachineOperand> &Pred) const {
469 unsigned Opc = MI->getOpcode();
470 if (isUncondBranchOpcode(Opc)) {
471 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
472 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
473 .addImm(Pred[0].getImm())
474 .addReg(Pred[1].getReg());
478 int PIdx = MI->findFirstPredOperandIdx();
480 MachineOperand &PMO = MI->getOperand(PIdx);
481 PMO.setImm(Pred[0].getImm());
482 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
488 bool ARMBaseInstrInfo::
489 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
490 const SmallVectorImpl<MachineOperand> &Pred2) const {
491 if (Pred1.size() > 2 || Pred2.size() > 2)
494 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
495 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
505 return CC2 == ARMCC::HI;
507 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
509 return CC2 == ARMCC::GT;
511 return CC2 == ARMCC::LT;
515 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
516 std::vector<MachineOperand> &Pred) const {
518 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
519 const MachineOperand &MO = MI->getOperand(i);
520 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
521 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
530 /// isPredicable - Return true if the specified instruction can be predicated.
531 /// By default, this returns true for every instruction with a
532 /// PredicateOperand.
533 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
534 if (!MI->isPredicable())
537 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
538 ARMFunctionInfo *AFI =
539 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
540 return AFI->isThumb2Function();
545 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
546 LLVM_ATTRIBUTE_NOINLINE
547 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
549 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
551 assert(JTI < JT.size());
552 return JT[JTI].MBBs.size();
555 /// GetInstSize - Return the size of the specified MachineInstr.
557 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
558 const MachineBasicBlock &MBB = *MI->getParent();
559 const MachineFunction *MF = MBB.getParent();
560 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
562 const MCInstrDesc &MCID = MI->getDesc();
564 return MCID.getSize();
566 // If this machine instr is an inline asm, measure it.
567 if (MI->getOpcode() == ARM::INLINEASM)
568 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
571 unsigned Opc = MI->getOpcode();
573 case TargetOpcode::IMPLICIT_DEF:
574 case TargetOpcode::KILL:
575 case TargetOpcode::PROLOG_LABEL:
576 case TargetOpcode::EH_LABEL:
577 case TargetOpcode::DBG_VALUE:
579 case TargetOpcode::BUNDLE:
580 return getInstBundleLength(MI);
581 case ARM::MOVi16_ga_pcrel:
582 case ARM::MOVTi16_ga_pcrel:
583 case ARM::t2MOVi16_ga_pcrel:
584 case ARM::t2MOVTi16_ga_pcrel:
587 case ARM::t2MOVi32imm:
589 case ARM::CONSTPOOL_ENTRY:
590 // If this machine instr is a constant pool entry, its size is recorded as
592 return MI->getOperand(2).getImm();
593 case ARM::Int_eh_sjlj_longjmp:
595 case ARM::tInt_eh_sjlj_longjmp:
597 case ARM::Int_eh_sjlj_setjmp:
598 case ARM::Int_eh_sjlj_setjmp_nofp:
600 case ARM::tInt_eh_sjlj_setjmp:
601 case ARM::t2Int_eh_sjlj_setjmp:
602 case ARM::t2Int_eh_sjlj_setjmp_nofp:
610 case ARM::t2TBH_JT: {
611 // These are jumptable branches, i.e. a branch followed by an inlined
612 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
613 // entry is one byte; TBH two byte each.
614 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
615 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
616 unsigned NumOps = MCID.getNumOperands();
617 MachineOperand JTOP =
618 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
619 unsigned JTI = JTOP.getIndex();
620 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
622 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
623 assert(JTI < JT.size());
624 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
625 // 4 aligned. The assembler / linker may add 2 byte padding just before
626 // the JT entries. The size does not include this padding; the
627 // constant islands pass does separate bookkeeping for it.
628 // FIXME: If we know the size of the function is less than (1 << 16) *2
629 // bytes, we can use 16-bit entries instead. Then there won't be an
631 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
632 unsigned NumEntries = getNumJTEntries(JT, JTI);
633 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
634 // Make sure the instruction that follows TBB is 2-byte aligned.
635 // FIXME: Constant island pass should insert an "ALIGN" instruction
638 return NumEntries * EntrySize + InstSize;
641 // Otherwise, pseudo-instruction sizes are zero.
646 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
648 MachineBasicBlock::const_instr_iterator I = MI;
649 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
650 while (++I != E && I->isInsideBundle()) {
651 assert(!I->isBundle() && "No nested bundle!");
652 Size += GetInstSizeInBytes(&*I);
657 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
658 MachineBasicBlock::iterator I, DebugLoc DL,
659 unsigned DestReg, unsigned SrcReg,
660 bool KillSrc) const {
661 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
662 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
664 if (GPRDest && GPRSrc) {
665 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
666 .addReg(SrcReg, getKillRegState(KillSrc))));
670 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
671 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
674 if (SPRDest && SPRSrc)
676 else if (GPRDest && SPRSrc)
678 else if (SPRDest && GPRSrc)
680 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
682 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
686 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
687 MIB.addReg(SrcReg, getKillRegState(KillSrc));
688 if (Opc == ARM::VORRq)
689 MIB.addReg(SrcReg, getKillRegState(KillSrc));
694 // Handle register classes that require multiple instructions.
695 unsigned BeginIdx = 0;
696 unsigned SubRegs = 0;
699 // Use VORRq when possible.
700 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
701 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
702 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
703 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
704 // Fall back to VMOVD.
705 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
707 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
708 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
709 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
710 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
711 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg))
712 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
714 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
715 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
716 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
717 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
718 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
719 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
721 assert(Opc && "Impossible reg-to-reg copy");
723 const TargetRegisterInfo *TRI = &getRegisterInfo();
724 MachineInstrBuilder Mov;
726 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
727 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
728 BeginIdx = BeginIdx + ((SubRegs-1)*Spacing);
732 SmallSet<unsigned, 4> DstRegs;
734 for (unsigned i = 0; i != SubRegs; ++i) {
735 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
736 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
737 assert(Dst && Src && "Bad sub-register");
739 assert(!DstRegs.count(Src) && "destructive vector copy");
742 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
744 // VORR takes two source operands.
745 if (Opc == ARM::VORRq)
747 Mov = AddDefaultPred(Mov);
749 // Add implicit super-register defs and kills to the last instruction.
750 Mov->addRegisterDefined(DestReg, TRI);
752 Mov->addRegisterKilled(SrcReg, TRI);
755 const MachineInstrBuilder &
756 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
757 unsigned SubIdx, unsigned State,
758 const TargetRegisterInfo *TRI) const {
760 return MIB.addReg(Reg, State);
762 if (TargetRegisterInfo::isPhysicalRegister(Reg))
763 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
764 return MIB.addReg(Reg, State, SubIdx);
767 void ARMBaseInstrInfo::
768 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
769 unsigned SrcReg, bool isKill, int FI,
770 const TargetRegisterClass *RC,
771 const TargetRegisterInfo *TRI) const {
773 if (I != MBB.end()) DL = I->getDebugLoc();
774 MachineFunction &MF = *MBB.getParent();
775 MachineFrameInfo &MFI = *MF.getFrameInfo();
776 unsigned Align = MFI.getObjectAlignment(FI);
778 MachineMemOperand *MMO =
779 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
780 MachineMemOperand::MOStore,
781 MFI.getObjectSize(FI),
784 switch (RC->getSize()) {
786 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
788 .addReg(SrcReg, getKillRegState(isKill))
789 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
790 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
791 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
792 .addReg(SrcReg, getKillRegState(isKill))
793 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
795 llvm_unreachable("Unknown reg class!");
798 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
799 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
800 .addReg(SrcReg, getKillRegState(isKill))
801 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
802 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
803 if (Subtarget.hasV5TEOps()) {
804 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
805 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
806 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
807 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
811 // Fallback to STM instruction, which has existed since the dawn of
813 MachineInstrBuilder MIB =
814 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
815 .addFrameIndex(FI).addMemOperand(MMO));
816 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
817 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
820 llvm_unreachable("Unknown reg class!");
823 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
824 // Use aligned spills if the stack can be realigned.
825 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
826 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
827 .addFrameIndex(FI).addImm(16)
828 .addReg(SrcReg, getKillRegState(isKill))
829 .addMemOperand(MMO));
831 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
832 .addReg(SrcReg, getKillRegState(isKill))
834 .addMemOperand(MMO));
837 llvm_unreachable("Unknown reg class!");
840 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
841 // Use aligned spills if the stack can be realigned.
842 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
843 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
844 .addFrameIndex(FI).addImm(16)
845 .addReg(SrcReg, getKillRegState(isKill))
846 .addMemOperand(MMO));
848 MachineInstrBuilder MIB =
849 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
852 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
853 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
854 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
857 llvm_unreachable("Unknown reg class!");
860 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
861 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
862 // FIXME: It's possible to only store part of the QQ register if the
863 // spilled def has a sub-register index.
864 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
865 .addFrameIndex(FI).addImm(16)
866 .addReg(SrcReg, getKillRegState(isKill))
867 .addMemOperand(MMO));
869 MachineInstrBuilder MIB =
870 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
873 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
874 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
875 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
876 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
879 llvm_unreachable("Unknown reg class!");
882 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
883 MachineInstrBuilder MIB =
884 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
887 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
888 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
889 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
890 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
891 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
892 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
893 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
894 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
896 llvm_unreachable("Unknown reg class!");
899 llvm_unreachable("Unknown reg class!");
904 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
905 int &FrameIndex) const {
906 switch (MI->getOpcode()) {
909 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
910 if (MI->getOperand(1).isFI() &&
911 MI->getOperand(2).isReg() &&
912 MI->getOperand(3).isImm() &&
913 MI->getOperand(2).getReg() == 0 &&
914 MI->getOperand(3).getImm() == 0) {
915 FrameIndex = MI->getOperand(1).getIndex();
916 return MI->getOperand(0).getReg();
924 if (MI->getOperand(1).isFI() &&
925 MI->getOperand(2).isImm() &&
926 MI->getOperand(2).getImm() == 0) {
927 FrameIndex = MI->getOperand(1).getIndex();
928 return MI->getOperand(0).getReg();
932 case ARM::VST1d64TPseudo:
933 case ARM::VST1d64QPseudo:
934 if (MI->getOperand(0).isFI() &&
935 MI->getOperand(2).getSubReg() == 0) {
936 FrameIndex = MI->getOperand(0).getIndex();
937 return MI->getOperand(2).getReg();
941 if (MI->getOperand(1).isFI() &&
942 MI->getOperand(0).getSubReg() == 0) {
943 FrameIndex = MI->getOperand(1).getIndex();
944 return MI->getOperand(0).getReg();
952 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
953 int &FrameIndex) const {
954 const MachineMemOperand *Dummy;
955 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
958 void ARMBaseInstrInfo::
959 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
960 unsigned DestReg, int FI,
961 const TargetRegisterClass *RC,
962 const TargetRegisterInfo *TRI) const {
964 if (I != MBB.end()) DL = I->getDebugLoc();
965 MachineFunction &MF = *MBB.getParent();
966 MachineFrameInfo &MFI = *MF.getFrameInfo();
967 unsigned Align = MFI.getObjectAlignment(FI);
968 MachineMemOperand *MMO =
969 MF.getMachineMemOperand(
970 MachinePointerInfo::getFixedStack(FI),
971 MachineMemOperand::MOLoad,
972 MFI.getObjectSize(FI),
975 switch (RC->getSize()) {
977 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
978 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
979 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
981 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
982 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
983 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
985 llvm_unreachable("Unknown reg class!");
988 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
989 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
990 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
991 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
992 MachineInstrBuilder MIB;
994 if (Subtarget.hasV5TEOps()) {
995 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
996 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
997 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
998 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1000 AddDefaultPred(MIB);
1002 // Fallback to LDM instruction, which has existed since the dawn of
1004 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1005 .addFrameIndex(FI).addMemOperand(MMO));
1006 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1007 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1010 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1011 MIB.addReg(DestReg, RegState::ImplicitDefine);
1013 llvm_unreachable("Unknown reg class!");
1016 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1017 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1018 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1019 .addFrameIndex(FI).addImm(16)
1020 .addMemOperand(MMO));
1022 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1024 .addMemOperand(MMO));
1027 llvm_unreachable("Unknown reg class!");
1030 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1031 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1032 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1033 .addFrameIndex(FI).addImm(16)
1034 .addMemOperand(MMO));
1036 MachineInstrBuilder MIB =
1037 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1039 .addMemOperand(MMO));
1040 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1041 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1042 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1043 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1044 MIB.addReg(DestReg, RegState::ImplicitDefine);
1047 llvm_unreachable("Unknown reg class!");
1050 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1051 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1052 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1053 .addFrameIndex(FI).addImm(16)
1054 .addMemOperand(MMO));
1056 MachineInstrBuilder MIB =
1057 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1059 .addMemOperand(MMO);
1060 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1061 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1062 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1063 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1064 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1065 MIB.addReg(DestReg, RegState::ImplicitDefine);
1068 llvm_unreachable("Unknown reg class!");
1071 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1072 MachineInstrBuilder MIB =
1073 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1075 .addMemOperand(MMO);
1076 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1077 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1078 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1079 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1080 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1081 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1082 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1083 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1084 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1085 MIB.addReg(DestReg, RegState::ImplicitDefine);
1087 llvm_unreachable("Unknown reg class!");
1090 llvm_unreachable("Unknown regclass!");
1095 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1096 int &FrameIndex) const {
1097 switch (MI->getOpcode()) {
1100 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1101 if (MI->getOperand(1).isFI() &&
1102 MI->getOperand(2).isReg() &&
1103 MI->getOperand(3).isImm() &&
1104 MI->getOperand(2).getReg() == 0 &&
1105 MI->getOperand(3).getImm() == 0) {
1106 FrameIndex = MI->getOperand(1).getIndex();
1107 return MI->getOperand(0).getReg();
1115 if (MI->getOperand(1).isFI() &&
1116 MI->getOperand(2).isImm() &&
1117 MI->getOperand(2).getImm() == 0) {
1118 FrameIndex = MI->getOperand(1).getIndex();
1119 return MI->getOperand(0).getReg();
1123 case ARM::VLD1d64TPseudo:
1124 case ARM::VLD1d64QPseudo:
1125 if (MI->getOperand(1).isFI() &&
1126 MI->getOperand(0).getSubReg() == 0) {
1127 FrameIndex = MI->getOperand(1).getIndex();
1128 return MI->getOperand(0).getReg();
1132 if (MI->getOperand(1).isFI() &&
1133 MI->getOperand(0).getSubReg() == 0) {
1134 FrameIndex = MI->getOperand(1).getIndex();
1135 return MI->getOperand(0).getReg();
1143 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1144 int &FrameIndex) const {
1145 const MachineMemOperand *Dummy;
1146 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1149 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1150 // This hook gets to expand COPY instructions before they become
1151 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1152 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1153 // changed into a VORR that can go down the NEON pipeline.
1154 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1157 // Look for a copy between even S-registers. That is where we keep floats
1158 // when using NEON v2f32 instructions for f32 arithmetic.
1159 unsigned DstRegS = MI->getOperand(0).getReg();
1160 unsigned SrcRegS = MI->getOperand(1).getReg();
1161 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1164 const TargetRegisterInfo *TRI = &getRegisterInfo();
1165 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1167 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1169 if (!DstRegD || !SrcRegD)
1172 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1173 // legal if the COPY already defines the full DstRegD, and it isn't a
1174 // sub-register insertion.
1175 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1178 // A dead copy shouldn't show up here, but reject it just in case.
1179 if (MI->getOperand(0).isDead())
1182 // All clear, widen the COPY.
1183 DEBUG(dbgs() << "widening: " << *MI);
1184 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1186 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1187 // or some other super-register.
1188 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1189 if (ImpDefIdx != -1)
1190 MI->RemoveOperand(ImpDefIdx);
1192 // Change the opcode and operands.
1193 MI->setDesc(get(ARM::VMOVD));
1194 MI->getOperand(0).setReg(DstRegD);
1195 MI->getOperand(1).setReg(SrcRegD);
1196 AddDefaultPred(MIB);
1198 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1199 // register scavenger and machine verifier, so we need to indicate that we
1200 // are reading an undefined value from SrcRegD, but a proper value from
1202 MI->getOperand(1).setIsUndef();
1203 MIB.addReg(SrcRegS, RegState::Implicit);
1205 // SrcRegD may actually contain an unrelated value in the ssub_1
1206 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1207 if (MI->getOperand(1).isKill()) {
1208 MI->getOperand(1).setIsKill(false);
1209 MI->addRegisterKilled(SrcRegS, TRI, true);
1212 DEBUG(dbgs() << "replaced by: " << *MI);
1216 /// Create a copy of a const pool value. Update CPI to the new index and return
1218 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1219 MachineConstantPool *MCP = MF.getConstantPool();
1220 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1222 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1223 assert(MCPE.isMachineConstantPoolEntry() &&
1224 "Expecting a machine constantpool entry!");
1225 ARMConstantPoolValue *ACPV =
1226 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1228 unsigned PCLabelId = AFI->createPICLabelUId();
1229 ARMConstantPoolValue *NewCPV = 0;
1230 // FIXME: The below assumes PIC relocation model and that the function
1231 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1232 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1233 // instructions, so that's probably OK, but is PIC always correct when
1235 if (ACPV->isGlobalValue())
1236 NewCPV = ARMConstantPoolConstant::
1237 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1239 else if (ACPV->isExtSymbol())
1240 NewCPV = ARMConstantPoolSymbol::
1241 Create(MF.getFunction()->getContext(),
1242 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1243 else if (ACPV->isBlockAddress())
1244 NewCPV = ARMConstantPoolConstant::
1245 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1246 ARMCP::CPBlockAddress, 4);
1247 else if (ACPV->isLSDA())
1248 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1250 else if (ACPV->isMachineBasicBlock())
1251 NewCPV = ARMConstantPoolMBB::
1252 Create(MF.getFunction()->getContext(),
1253 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1255 llvm_unreachable("Unexpected ARM constantpool value type!!");
1256 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1260 void ARMBaseInstrInfo::
1261 reMaterialize(MachineBasicBlock &MBB,
1262 MachineBasicBlock::iterator I,
1263 unsigned DestReg, unsigned SubIdx,
1264 const MachineInstr *Orig,
1265 const TargetRegisterInfo &TRI) const {
1266 unsigned Opcode = Orig->getOpcode();
1269 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1270 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1274 case ARM::tLDRpci_pic:
1275 case ARM::t2LDRpci_pic: {
1276 MachineFunction &MF = *MBB.getParent();
1277 unsigned CPI = Orig->getOperand(1).getIndex();
1278 unsigned PCLabelId = duplicateCPV(MF, CPI);
1279 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1281 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1282 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1289 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1290 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1291 switch(Orig->getOpcode()) {
1292 case ARM::tLDRpci_pic:
1293 case ARM::t2LDRpci_pic: {
1294 unsigned CPI = Orig->getOperand(1).getIndex();
1295 unsigned PCLabelId = duplicateCPV(MF, CPI);
1296 Orig->getOperand(1).setIndex(CPI);
1297 Orig->getOperand(2).setImm(PCLabelId);
1304 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1305 const MachineInstr *MI1,
1306 const MachineRegisterInfo *MRI) const {
1307 int Opcode = MI0->getOpcode();
1308 if (Opcode == ARM::t2LDRpci ||
1309 Opcode == ARM::t2LDRpci_pic ||
1310 Opcode == ARM::tLDRpci ||
1311 Opcode == ARM::tLDRpci_pic ||
1312 Opcode == ARM::MOV_ga_dyn ||
1313 Opcode == ARM::MOV_ga_pcrel ||
1314 Opcode == ARM::MOV_ga_pcrel_ldr ||
1315 Opcode == ARM::t2MOV_ga_dyn ||
1316 Opcode == ARM::t2MOV_ga_pcrel) {
1317 if (MI1->getOpcode() != Opcode)
1319 if (MI0->getNumOperands() != MI1->getNumOperands())
1322 const MachineOperand &MO0 = MI0->getOperand(1);
1323 const MachineOperand &MO1 = MI1->getOperand(1);
1324 if (MO0.getOffset() != MO1.getOffset())
1327 if (Opcode == ARM::MOV_ga_dyn ||
1328 Opcode == ARM::MOV_ga_pcrel ||
1329 Opcode == ARM::MOV_ga_pcrel_ldr ||
1330 Opcode == ARM::t2MOV_ga_dyn ||
1331 Opcode == ARM::t2MOV_ga_pcrel)
1332 // Ignore the PC labels.
1333 return MO0.getGlobal() == MO1.getGlobal();
1335 const MachineFunction *MF = MI0->getParent()->getParent();
1336 const MachineConstantPool *MCP = MF->getConstantPool();
1337 int CPI0 = MO0.getIndex();
1338 int CPI1 = MO1.getIndex();
1339 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1340 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1341 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1342 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1343 if (isARMCP0 && isARMCP1) {
1344 ARMConstantPoolValue *ACPV0 =
1345 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1346 ARMConstantPoolValue *ACPV1 =
1347 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1348 return ACPV0->hasSameValue(ACPV1);
1349 } else if (!isARMCP0 && !isARMCP1) {
1350 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1353 } else if (Opcode == ARM::PICLDR) {
1354 if (MI1->getOpcode() != Opcode)
1356 if (MI0->getNumOperands() != MI1->getNumOperands())
1359 unsigned Addr0 = MI0->getOperand(1).getReg();
1360 unsigned Addr1 = MI1->getOperand(1).getReg();
1361 if (Addr0 != Addr1) {
1363 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1364 !TargetRegisterInfo::isVirtualRegister(Addr1))
1367 // This assumes SSA form.
1368 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1369 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1370 // Check if the loaded value, e.g. a constantpool of a global address, are
1372 if (!produceSameValue(Def0, Def1, MRI))
1376 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1377 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1378 const MachineOperand &MO0 = MI0->getOperand(i);
1379 const MachineOperand &MO1 = MI1->getOperand(i);
1380 if (!MO0.isIdenticalTo(MO1))
1386 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1389 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1390 /// determine if two loads are loading from the same base address. It should
1391 /// only return true if the base pointers are the same and the only differences
1392 /// between the two addresses is the offset. It also returns the offsets by
1395 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1396 /// is permanently disabled.
1397 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1399 int64_t &Offset2) const {
1400 // Don't worry about Thumb: just ARM and Thumb2.
1401 if (Subtarget.isThumb1Only()) return false;
1403 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1406 switch (Load1->getMachineOpcode()) {
1419 case ARM::t2LDRSHi8:
1421 case ARM::t2LDRSHi12:
1425 switch (Load2->getMachineOpcode()) {
1437 case ARM::t2LDRSHi8:
1439 case ARM::t2LDRSHi12:
1443 // Check if base addresses and chain operands match.
1444 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1445 Load1->getOperand(4) != Load2->getOperand(4))
1448 // Index should be Reg0.
1449 if (Load1->getOperand(3) != Load2->getOperand(3))
1452 // Determine the offsets.
1453 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1454 isa<ConstantSDNode>(Load2->getOperand(1))) {
1455 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1456 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1463 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1464 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1465 /// be scheduled togther. On some targets if two loads are loading from
1466 /// addresses in the same cache line, it's better if they are scheduled
1467 /// together. This function takes two integers that represent the load offsets
1468 /// from the common base address. It returns true if it decides it's desirable
1469 /// to schedule the two loads together. "NumLoads" is the number of loads that
1470 /// have already been scheduled after Load1.
1472 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1473 /// is permanently disabled.
1474 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1475 int64_t Offset1, int64_t Offset2,
1476 unsigned NumLoads) const {
1477 // Don't worry about Thumb: just ARM and Thumb2.
1478 if (Subtarget.isThumb1Only()) return false;
1480 assert(Offset2 > Offset1);
1482 if ((Offset2 - Offset1) / 8 > 64)
1485 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1486 return false; // FIXME: overly conservative?
1488 // Four loads in a row should be sufficient.
1495 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1496 const MachineBasicBlock *MBB,
1497 const MachineFunction &MF) const {
1498 // Debug info is never a scheduling boundary. It's necessary to be explicit
1499 // due to the special treatment of IT instructions below, otherwise a
1500 // dbg_value followed by an IT will result in the IT instruction being
1501 // considered a scheduling hazard, which is wrong. It should be the actual
1502 // instruction preceding the dbg_value instruction(s), just like it is
1503 // when debug info is not present.
1504 if (MI->isDebugValue())
1507 // Terminators and labels can't be scheduled around.
1508 if (MI->isTerminator() || MI->isLabel())
1511 // Treat the start of the IT block as a scheduling boundary, but schedule
1512 // t2IT along with all instructions following it.
1513 // FIXME: This is a big hammer. But the alternative is to add all potential
1514 // true and anti dependencies to IT block instructions as implicit operands
1515 // to the t2IT instruction. The added compile time and complexity does not
1517 MachineBasicBlock::const_iterator I = MI;
1518 // Make sure to skip any dbg_value instructions
1519 while (++I != MBB->end() && I->isDebugValue())
1521 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1524 // Don't attempt to schedule around any instruction that defines
1525 // a stack-oriented pointer, as it's unlikely to be profitable. This
1526 // saves compile time, because it doesn't require every single
1527 // stack slot reference to depend on the instruction that does the
1529 // Calls don't actually change the stack pointer, even if they have imp-defs.
1530 // No ARM calling conventions change the stack pointer. (X86 calling
1531 // conventions sometimes do).
1532 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1538 bool ARMBaseInstrInfo::
1539 isProfitableToIfCvt(MachineBasicBlock &MBB,
1540 unsigned NumCycles, unsigned ExtraPredCycles,
1541 const BranchProbability &Probability) const {
1545 // Attempt to estimate the relative costs of predication versus branching.
1546 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1547 UnpredCost /= Probability.getDenominator();
1548 UnpredCost += 1; // The branch itself
1549 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1551 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1554 bool ARMBaseInstrInfo::
1555 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1556 unsigned TCycles, unsigned TExtra,
1557 MachineBasicBlock &FMBB,
1558 unsigned FCycles, unsigned FExtra,
1559 const BranchProbability &Probability) const {
1560 if (!TCycles || !FCycles)
1563 // Attempt to estimate the relative costs of predication versus branching.
1564 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1565 TUnpredCost /= Probability.getDenominator();
1567 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1568 unsigned FUnpredCost = Comp * FCycles;
1569 FUnpredCost /= Probability.getDenominator();
1571 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1572 UnpredCost += 1; // The branch itself
1573 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1575 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1579 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1580 MachineBasicBlock &FMBB) const {
1581 // Reduce false anti-dependencies to let Swift's out-of-order execution
1582 // engine do its thing.
1583 return Subtarget.isSwift();
1586 /// getInstrPredicate - If instruction is predicated, returns its predicate
1587 /// condition, otherwise returns AL. It also returns the condition code
1588 /// register by reference.
1590 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1591 int PIdx = MI->findFirstPredOperandIdx();
1597 PredReg = MI->getOperand(PIdx+1).getReg();
1598 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1602 int llvm::getMatchingCondBranchOpcode(int Opc) {
1607 if (Opc == ARM::t2B)
1610 llvm_unreachable("Unknown unconditional branch opcode!");
1613 /// commuteInstruction - Handle commutable instructions.
1615 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1616 switch (MI->getOpcode()) {
1618 case ARM::t2MOVCCr: {
1619 // MOVCC can be commuted by inverting the condition.
1620 unsigned PredReg = 0;
1621 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1622 // MOVCC AL can't be inverted. Shouldn't happen.
1623 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1625 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1628 // After swapping the MOVCC operands, also invert the condition.
1629 MI->getOperand(MI->findFirstPredOperandIdx())
1630 .setImm(ARMCC::getOppositeCondition(CC));
1634 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1637 /// Identify instructions that can be folded into a MOVCC instruction, and
1638 /// return the defining instruction.
1639 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1640 const MachineRegisterInfo &MRI,
1641 const TargetInstrInfo *TII) {
1642 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1644 if (!MRI.hasOneNonDBGUse(Reg))
1646 MachineInstr *MI = MRI.getVRegDef(Reg);
1649 // MI is folded into the MOVCC by predicating it.
1650 if (!MI->isPredicable())
1652 // Check if MI has any non-dead defs or physreg uses. This also detects
1653 // predicated instructions which will be reading CPSR.
1654 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1655 const MachineOperand &MO = MI->getOperand(i);
1656 // Reject frame index operands, PEI can't handle the predicated pseudos.
1657 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1661 // MI can't have any tied operands, that would conflict with predication.
1664 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1666 if (MO.isDef() && !MO.isDead())
1669 bool DontMoveAcrossStores = true;
1670 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1675 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1676 SmallVectorImpl<MachineOperand> &Cond,
1677 unsigned &TrueOp, unsigned &FalseOp,
1678 bool &Optimizable) const {
1679 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1680 "Unknown select instruction");
1685 // 3: Condition code.
1689 Cond.push_back(MI->getOperand(3));
1690 Cond.push_back(MI->getOperand(4));
1691 // We can always fold a def.
1696 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1697 bool PreferFalse) const {
1698 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1699 "Unknown select instruction");
1700 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1701 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1702 bool Invert = !DefMI;
1704 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1708 // Create a new predicated version of DefMI.
1709 // Rfalse is the first use.
1710 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1712 MI->getOperand(0).getReg());
1714 // Copy all the DefMI operands, excluding its (null) predicate.
1715 const MCInstrDesc &DefDesc = DefMI->getDesc();
1716 for (unsigned i = 1, e = DefDesc.getNumOperands();
1717 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1718 NewMI.addOperand(DefMI->getOperand(i));
1720 unsigned CondCode = MI->getOperand(3).getImm();
1722 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1724 NewMI.addImm(CondCode);
1725 NewMI.addOperand(MI->getOperand(4));
1727 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1728 if (NewMI->hasOptionalDef())
1729 AddDefaultCC(NewMI);
1731 // The output register value when the predicate is false is an implicit
1732 // register operand tied to the first def.
1733 // The tie makes the register allocator ensure the FalseReg is allocated the
1734 // same register as operand 0.
1735 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1736 FalseReg.setImplicit();
1737 NewMI.addOperand(FalseReg);
1738 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1740 // The caller will erase MI, but not DefMI.
1741 DefMI->eraseFromParent();
1745 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1746 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1749 /// This will go away once we can teach tblgen how to set the optional CPSR def
1751 struct AddSubFlagsOpcodePair {
1753 uint16_t MachineOpc;
1756 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1757 {ARM::ADDSri, ARM::ADDri},
1758 {ARM::ADDSrr, ARM::ADDrr},
1759 {ARM::ADDSrsi, ARM::ADDrsi},
1760 {ARM::ADDSrsr, ARM::ADDrsr},
1762 {ARM::SUBSri, ARM::SUBri},
1763 {ARM::SUBSrr, ARM::SUBrr},
1764 {ARM::SUBSrsi, ARM::SUBrsi},
1765 {ARM::SUBSrsr, ARM::SUBrsr},
1767 {ARM::RSBSri, ARM::RSBri},
1768 {ARM::RSBSrsi, ARM::RSBrsi},
1769 {ARM::RSBSrsr, ARM::RSBrsr},
1771 {ARM::t2ADDSri, ARM::t2ADDri},
1772 {ARM::t2ADDSrr, ARM::t2ADDrr},
1773 {ARM::t2ADDSrs, ARM::t2ADDrs},
1775 {ARM::t2SUBSri, ARM::t2SUBri},
1776 {ARM::t2SUBSrr, ARM::t2SUBrr},
1777 {ARM::t2SUBSrs, ARM::t2SUBrs},
1779 {ARM::t2RSBSri, ARM::t2RSBri},
1780 {ARM::t2RSBSrs, ARM::t2RSBrs},
1783 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1784 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1785 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1786 return AddSubFlagsOpcodeMap[i].MachineOpc;
1790 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1791 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1792 unsigned DestReg, unsigned BaseReg, int NumBytes,
1793 ARMCC::CondCodes Pred, unsigned PredReg,
1794 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1795 bool isSub = NumBytes < 0;
1796 if (isSub) NumBytes = -NumBytes;
1799 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1800 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1801 assert(ThisVal && "Didn't extract field correctly");
1803 // We will handle these bits from offset, clear them.
1804 NumBytes &= ~ThisVal;
1806 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1808 // Build the new ADD / SUB.
1809 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1810 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1811 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1812 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1813 .setMIFlags(MIFlags);
1818 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1819 unsigned FrameReg, int &Offset,
1820 const ARMBaseInstrInfo &TII) {
1821 unsigned Opcode = MI.getOpcode();
1822 const MCInstrDesc &Desc = MI.getDesc();
1823 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1826 // Memory operands in inline assembly always use AddrMode2.
1827 if (Opcode == ARM::INLINEASM)
1828 AddrMode = ARMII::AddrMode2;
1830 if (Opcode == ARM::ADDri) {
1831 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1833 // Turn it into a move.
1834 MI.setDesc(TII.get(ARM::MOVr));
1835 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1836 MI.RemoveOperand(FrameRegIdx+1);
1839 } else if (Offset < 0) {
1842 MI.setDesc(TII.get(ARM::SUBri));
1845 // Common case: small offset, fits into instruction.
1846 if (ARM_AM::getSOImmVal(Offset) != -1) {
1847 // Replace the FrameIndex with sp / fp
1848 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1849 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1854 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1856 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1857 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1859 // We will handle these bits from offset, clear them.
1860 Offset &= ~ThisImmVal;
1862 // Get the properly encoded SOImmVal field.
1863 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1864 "Bit extraction didn't work?");
1865 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1867 unsigned ImmIdx = 0;
1869 unsigned NumBits = 0;
1872 case ARMII::AddrMode_i12: {
1873 ImmIdx = FrameRegIdx + 1;
1874 InstrOffs = MI.getOperand(ImmIdx).getImm();
1878 case ARMII::AddrMode2: {
1879 ImmIdx = FrameRegIdx+2;
1880 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1881 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1886 case ARMII::AddrMode3: {
1887 ImmIdx = FrameRegIdx+2;
1888 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1889 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1894 case ARMII::AddrMode4:
1895 case ARMII::AddrMode6:
1896 // Can't fold any offset even if it's zero.
1898 case ARMII::AddrMode5: {
1899 ImmIdx = FrameRegIdx+1;
1900 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1901 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1908 llvm_unreachable("Unsupported addressing mode!");
1911 Offset += InstrOffs * Scale;
1912 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1918 // Attempt to fold address comp. if opcode has offset bits
1920 // Common case: small offset, fits into instruction.
1921 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1922 int ImmedOffset = Offset / Scale;
1923 unsigned Mask = (1 << NumBits) - 1;
1924 if ((unsigned)Offset <= Mask * Scale) {
1925 // Replace the FrameIndex with sp
1926 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1927 // FIXME: When addrmode2 goes away, this will simplify (like the
1928 // T2 version), as the LDR.i12 versions don't need the encoding
1929 // tricks for the offset value.
1931 if (AddrMode == ARMII::AddrMode_i12)
1932 ImmedOffset = -ImmedOffset;
1934 ImmedOffset |= 1 << NumBits;
1936 ImmOp.ChangeToImmediate(ImmedOffset);
1941 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1942 ImmedOffset = ImmedOffset & Mask;
1944 if (AddrMode == ARMII::AddrMode_i12)
1945 ImmedOffset = -ImmedOffset;
1947 ImmedOffset |= 1 << NumBits;
1949 ImmOp.ChangeToImmediate(ImmedOffset);
1950 Offset &= ~(Mask*Scale);
1954 Offset = (isSub) ? -Offset : Offset;
1958 /// analyzeCompare - For a comparison instruction, return the source registers
1959 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1960 /// compares against in CmpValue. Return true if the comparison instruction
1961 /// can be analyzed.
1962 bool ARMBaseInstrInfo::
1963 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1964 int &CmpMask, int &CmpValue) const {
1965 switch (MI->getOpcode()) {
1969 SrcReg = MI->getOperand(0).getReg();
1972 CmpValue = MI->getOperand(1).getImm();
1976 SrcReg = MI->getOperand(0).getReg();
1977 SrcReg2 = MI->getOperand(1).getReg();
1983 SrcReg = MI->getOperand(0).getReg();
1985 CmpMask = MI->getOperand(1).getImm();
1993 /// isSuitableForMask - Identify a suitable 'and' instruction that
1994 /// operates on the given source register and applies the same mask
1995 /// as a 'tst' instruction. Provide a limited look-through for copies.
1996 /// When successful, MI will hold the found instruction.
1997 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1998 int CmpMask, bool CommonUse) {
1999 switch (MI->getOpcode()) {
2002 if (CmpMask != MI->getOperand(2).getImm())
2004 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2008 // Walk down one instruction which is potentially an 'and'.
2009 const MachineInstr &Copy = *MI;
2010 MachineBasicBlock::iterator AND(
2011 llvm::next(MachineBasicBlock::iterator(MI)));
2012 if (AND == MI->getParent()->end()) return false;
2014 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2022 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2023 /// the condition code if we modify the instructions such that flags are
2025 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2027 default: return ARMCC::AL;
2028 case ARMCC::EQ: return ARMCC::EQ;
2029 case ARMCC::NE: return ARMCC::NE;
2030 case ARMCC::HS: return ARMCC::LS;
2031 case ARMCC::LO: return ARMCC::HI;
2032 case ARMCC::HI: return ARMCC::LO;
2033 case ARMCC::LS: return ARMCC::HS;
2034 case ARMCC::GE: return ARMCC::LE;
2035 case ARMCC::LT: return ARMCC::GT;
2036 case ARMCC::GT: return ARMCC::LT;
2037 case ARMCC::LE: return ARMCC::GE;
2041 /// isRedundantFlagInstr - check whether the first instruction, whose only
2042 /// purpose is to update flags, can be made redundant.
2043 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2044 /// CMPri can be made redundant by SUBri if the operands are the same.
2045 /// This function can be extended later on.
2046 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2047 unsigned SrcReg2, int ImmValue,
2049 if ((CmpI->getOpcode() == ARM::CMPrr ||
2050 CmpI->getOpcode() == ARM::t2CMPrr) &&
2051 (OI->getOpcode() == ARM::SUBrr ||
2052 OI->getOpcode() == ARM::t2SUBrr) &&
2053 ((OI->getOperand(1).getReg() == SrcReg &&
2054 OI->getOperand(2).getReg() == SrcReg2) ||
2055 (OI->getOperand(1).getReg() == SrcReg2 &&
2056 OI->getOperand(2).getReg() == SrcReg)))
2059 if ((CmpI->getOpcode() == ARM::CMPri ||
2060 CmpI->getOpcode() == ARM::t2CMPri) &&
2061 (OI->getOpcode() == ARM::SUBri ||
2062 OI->getOpcode() == ARM::t2SUBri) &&
2063 OI->getOperand(1).getReg() == SrcReg &&
2064 OI->getOperand(2).getImm() == ImmValue)
2069 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2070 /// comparison into one that sets the zero bit in the flags register;
2071 /// Remove a redundant Compare instruction if an earlier instruction can set the
2072 /// flags in the same way as Compare.
2073 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2074 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2075 /// condition code of instructions which use the flags.
2076 bool ARMBaseInstrInfo::
2077 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2078 int CmpMask, int CmpValue,
2079 const MachineRegisterInfo *MRI) const {
2080 // Get the unique definition of SrcReg.
2081 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2082 if (!MI) return false;
2084 // Masked compares sometimes use the same register as the corresponding 'and'.
2085 if (CmpMask != ~0) {
2086 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2088 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2089 UE = MRI->use_end(); UI != UE; ++UI) {
2090 if (UI->getParent() != CmpInstr->getParent()) continue;
2091 MachineInstr *PotentialAND = &*UI;
2092 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2093 isPredicated(PotentialAND))
2098 if (!MI) return false;
2102 // Get ready to iterate backward from CmpInstr.
2103 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2104 B = CmpInstr->getParent()->begin();
2106 // Early exit if CmpInstr is at the beginning of the BB.
2107 if (I == B) return false;
2109 // There are two possible candidates which can be changed to set CPSR:
2110 // One is MI, the other is a SUB instruction.
2111 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2112 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2113 MachineInstr *Sub = NULL;
2115 // MI is not a candidate for CMPrr.
2117 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2118 // Conservatively refuse to convert an instruction which isn't in the same
2119 // BB as the comparison.
2120 // For CMPri, we need to check Sub, thus we can't return here.
2121 if (CmpInstr->getOpcode() == ARM::CMPri ||
2122 CmpInstr->getOpcode() == ARM::t2CMPri)
2128 // Check that CPSR isn't set between the comparison instruction and the one we
2129 // want to change. At the same time, search for Sub.
2130 const TargetRegisterInfo *TRI = &getRegisterInfo();
2132 for (; I != E; --I) {
2133 const MachineInstr &Instr = *I;
2135 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2136 Instr.readsRegister(ARM::CPSR, TRI))
2137 // This instruction modifies or uses CPSR after the one we want to
2138 // change. We can't do this transformation.
2141 // Check whether CmpInstr can be made redundant by the current instruction.
2142 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2148 // The 'and' is below the comparison instruction.
2152 // Return false if no candidates exist.
2156 // The single candidate is called MI.
2159 // We can't use a predicated instruction - it doesn't always write the flags.
2160 if (isPredicated(MI))
2163 switch (MI->getOpcode()) {
2197 case ARM::t2EORri: {
2198 // Scan forward for the use of CPSR
2199 // When checking against MI: if it's a conditional code requires
2200 // checking of V bit, then this is not safe to do.
2201 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2202 // If we are done with the basic block, we need to check whether CPSR is
2204 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2206 bool isSafe = false;
2208 E = CmpInstr->getParent()->end();
2209 while (!isSafe && ++I != E) {
2210 const MachineInstr &Instr = *I;
2211 for (unsigned IO = 0, EO = Instr.getNumOperands();
2212 !isSafe && IO != EO; ++IO) {
2213 const MachineOperand &MO = Instr.getOperand(IO);
2214 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2218 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2224 // Condition code is after the operand before CPSR.
2225 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2227 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2228 if (NewCC == ARMCC::AL)
2230 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2231 // on CMP needs to be updated to be based on SUB.
2232 // Push the condition code operands to OperandsToUpdate.
2233 // If it is safe to remove CmpInstr, the condition code of these
2234 // operands will be modified.
2235 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2236 Sub->getOperand(2).getReg() == SrcReg)
2237 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2243 // CPSR can be used multiple times, we should continue.
2256 // If CPSR is not killed nor re-defined, we should check whether it is
2257 // live-out. If it is live-out, do not optimize.
2259 MachineBasicBlock *MBB = CmpInstr->getParent();
2260 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2261 SE = MBB->succ_end(); SI != SE; ++SI)
2262 if ((*SI)->isLiveIn(ARM::CPSR))
2266 // Toggle the optional operand to CPSR.
2267 MI->getOperand(5).setReg(ARM::CPSR);
2268 MI->getOperand(5).setIsDef(true);
2269 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2270 CmpInstr->eraseFromParent();
2272 // Modify the condition code of operands in OperandsToUpdate.
2273 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2274 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2275 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2276 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2284 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2285 MachineInstr *DefMI, unsigned Reg,
2286 MachineRegisterInfo *MRI) const {
2287 // Fold large immediates into add, sub, or, xor.
2288 unsigned DefOpc = DefMI->getOpcode();
2289 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2291 if (!DefMI->getOperand(1).isImm())
2292 // Could be t2MOVi32imm <ga:xx>
2295 if (!MRI->hasOneNonDBGUse(Reg))
2298 const MCInstrDesc &DefMCID = DefMI->getDesc();
2299 if (DefMCID.hasOptionalDef()) {
2300 unsigned NumOps = DefMCID.getNumOperands();
2301 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2302 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2303 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2308 const MCInstrDesc &UseMCID = UseMI->getDesc();
2309 if (UseMCID.hasOptionalDef()) {
2310 unsigned NumOps = UseMCID.getNumOperands();
2311 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2312 // If the instruction sets the flag, do not attempt this optimization
2313 // since it may change the semantics of the code.
2317 unsigned UseOpc = UseMI->getOpcode();
2318 unsigned NewUseOpc = 0;
2319 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2320 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2321 bool Commute = false;
2323 default: return false;
2331 case ARM::t2EORrr: {
2332 Commute = UseMI->getOperand(2).getReg() != Reg;
2339 NewUseOpc = ARM::SUBri;
2345 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2347 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2348 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2351 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2352 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2353 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2357 case ARM::t2SUBrr: {
2361 NewUseOpc = ARM::t2SUBri;
2366 case ARM::t2EORrr: {
2367 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2369 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2370 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2373 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2374 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2375 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2383 unsigned OpIdx = Commute ? 2 : 1;
2384 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2385 bool isKill = UseMI->getOperand(OpIdx).isKill();
2386 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2387 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2388 UseMI, UseMI->getDebugLoc(),
2389 get(NewUseOpc), NewReg)
2390 .addReg(Reg1, getKillRegState(isKill))
2391 .addImm(SOImmValV1)));
2392 UseMI->setDesc(get(NewUseOpc));
2393 UseMI->getOperand(1).setReg(NewReg);
2394 UseMI->getOperand(1).setIsKill();
2395 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2396 DefMI->eraseFromParent();
2400 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2401 const MachineInstr *MI) {
2402 switch (MI->getOpcode()) {
2404 const MCInstrDesc &Desc = MI->getDesc();
2405 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2406 assert(UOps >= 0 && "bad # UOps");
2414 unsigned ShOpVal = MI->getOperand(3).getImm();
2415 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2416 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2419 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2420 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2427 if (!MI->getOperand(2).getReg())
2430 unsigned ShOpVal = MI->getOperand(3).getImm();
2431 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2432 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2435 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2436 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2443 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2445 case ARM::LDRSB_POST:
2446 case ARM::LDRSH_POST: {
2447 unsigned Rt = MI->getOperand(0).getReg();
2448 unsigned Rm = MI->getOperand(3).getReg();
2449 return (Rt == Rm) ? 4 : 3;
2452 case ARM::LDR_PRE_REG:
2453 case ARM::LDRB_PRE_REG: {
2454 unsigned Rt = MI->getOperand(0).getReg();
2455 unsigned Rm = MI->getOperand(3).getReg();
2458 unsigned ShOpVal = MI->getOperand(4).getImm();
2459 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2460 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2463 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2464 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2469 case ARM::STR_PRE_REG:
2470 case ARM::STRB_PRE_REG: {
2471 unsigned ShOpVal = MI->getOperand(4).getImm();
2472 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2473 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2476 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2477 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2483 case ARM::STRH_PRE: {
2484 unsigned Rt = MI->getOperand(0).getReg();
2485 unsigned Rm = MI->getOperand(3).getReg();
2490 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2494 case ARM::LDR_POST_REG:
2495 case ARM::LDRB_POST_REG:
2496 case ARM::LDRH_POST: {
2497 unsigned Rt = MI->getOperand(0).getReg();
2498 unsigned Rm = MI->getOperand(3).getReg();
2499 return (Rt == Rm) ? 3 : 2;
2502 case ARM::LDR_PRE_IMM:
2503 case ARM::LDRB_PRE_IMM:
2504 case ARM::LDR_POST_IMM:
2505 case ARM::LDRB_POST_IMM:
2506 case ARM::STRB_POST_IMM:
2507 case ARM::STRB_POST_REG:
2508 case ARM::STRB_PRE_IMM:
2509 case ARM::STRH_POST:
2510 case ARM::STR_POST_IMM:
2511 case ARM::STR_POST_REG:
2512 case ARM::STR_PRE_IMM:
2515 case ARM::LDRSB_PRE:
2516 case ARM::LDRSH_PRE: {
2517 unsigned Rm = MI->getOperand(3).getReg();
2520 unsigned Rt = MI->getOperand(0).getReg();
2523 unsigned ShOpVal = MI->getOperand(4).getImm();
2524 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2525 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2528 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2529 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2535 unsigned Rt = MI->getOperand(0).getReg();
2536 unsigned Rn = MI->getOperand(2).getReg();
2537 unsigned Rm = MI->getOperand(3).getReg();
2539 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2540 return (Rt == Rn) ? 3 : 2;
2544 unsigned Rm = MI->getOperand(3).getReg();
2546 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2550 case ARM::LDRD_POST:
2551 case ARM::t2LDRD_POST:
2554 case ARM::STRD_POST:
2555 case ARM::t2STRD_POST:
2558 case ARM::LDRD_PRE: {
2559 unsigned Rt = MI->getOperand(0).getReg();
2560 unsigned Rn = MI->getOperand(3).getReg();
2561 unsigned Rm = MI->getOperand(4).getReg();
2563 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2564 return (Rt == Rn) ? 4 : 3;
2567 case ARM::t2LDRD_PRE: {
2568 unsigned Rt = MI->getOperand(0).getReg();
2569 unsigned Rn = MI->getOperand(3).getReg();
2570 return (Rt == Rn) ? 4 : 3;
2573 case ARM::STRD_PRE: {
2574 unsigned Rm = MI->getOperand(4).getReg();
2576 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2580 case ARM::t2STRD_PRE:
2583 case ARM::t2LDR_POST:
2584 case ARM::t2LDRB_POST:
2585 case ARM::t2LDRB_PRE:
2586 case ARM::t2LDRSBi12:
2587 case ARM::t2LDRSBi8:
2588 case ARM::t2LDRSBpci:
2590 case ARM::t2LDRH_POST:
2591 case ARM::t2LDRH_PRE:
2593 case ARM::t2LDRSB_POST:
2594 case ARM::t2LDRSB_PRE:
2595 case ARM::t2LDRSH_POST:
2596 case ARM::t2LDRSH_PRE:
2597 case ARM::t2LDRSHi12:
2598 case ARM::t2LDRSHi8:
2599 case ARM::t2LDRSHpci:
2603 case ARM::t2LDRDi8: {
2604 unsigned Rt = MI->getOperand(0).getReg();
2605 unsigned Rn = MI->getOperand(2).getReg();
2606 return (Rt == Rn) ? 3 : 2;
2609 case ARM::t2STRB_POST:
2610 case ARM::t2STRB_PRE:
2613 case ARM::t2STRH_POST:
2614 case ARM::t2STRH_PRE:
2616 case ARM::t2STR_POST:
2617 case ARM::t2STR_PRE:
2623 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2624 // can't be easily determined return 0 (missing MachineMemOperand).
2626 // FIXME: The current MachineInstr design does not support relying on machine
2627 // mem operands to determine the width of a memory access. Instead, we expect
2628 // the target to provide this information based on the instruction opcode and
2629 // operands. However, using MachineMemOperand is a the best solution now for
2632 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2633 // operands. This is much more dangerous than using the MachineMemOperand
2634 // sizes because CodeGen passes can insert/remove optional machine operands. In
2635 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2636 // postRA passes as well.
2638 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2639 // machine model that calls this should handle the unknown (zero size) case.
2641 // Long term, we should require a target hook that verifies MachineMemOperand
2642 // sizes during MC lowering. That target hook should be local to MC lowering
2643 // because we can't ensure that it is aware of other MI forms. Doing this will
2644 // ensure that MachineMemOperands are correctly propagated through all passes.
2645 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2647 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2648 E = MI->memoperands_end(); I != E; ++I) {
2649 Size += (*I)->getSize();
2655 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2656 const MachineInstr *MI) const {
2657 if (!ItinData || ItinData->isEmpty())
2660 const MCInstrDesc &Desc = MI->getDesc();
2661 unsigned Class = Desc.getSchedClass();
2662 int ItinUOps = ItinData->getNumMicroOps(Class);
2663 if (ItinUOps >= 0) {
2664 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2665 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2670 unsigned Opc = MI->getOpcode();
2673 llvm_unreachable("Unexpected multi-uops instruction!");
2678 // The number of uOps for load / store multiple are determined by the number
2681 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2682 // same cycle. The scheduling for the first load / store must be done
2683 // separately by assuming the address is not 64-bit aligned.
2685 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2686 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2687 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2689 case ARM::VLDMDIA_UPD:
2690 case ARM::VLDMDDB_UPD:
2692 case ARM::VLDMSIA_UPD:
2693 case ARM::VLDMSDB_UPD:
2695 case ARM::VSTMDIA_UPD:
2696 case ARM::VSTMDDB_UPD:
2698 case ARM::VSTMSIA_UPD:
2699 case ARM::VSTMSDB_UPD: {
2700 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2701 return (NumRegs / 2) + (NumRegs % 2) + 1;
2704 case ARM::LDMIA_RET:
2709 case ARM::LDMIA_UPD:
2710 case ARM::LDMDA_UPD:
2711 case ARM::LDMDB_UPD:
2712 case ARM::LDMIB_UPD:
2717 case ARM::STMIA_UPD:
2718 case ARM::STMDA_UPD:
2719 case ARM::STMDB_UPD:
2720 case ARM::STMIB_UPD:
2722 case ARM::tLDMIA_UPD:
2723 case ARM::tSTMIA_UPD:
2727 case ARM::t2LDMIA_RET:
2730 case ARM::t2LDMIA_UPD:
2731 case ARM::t2LDMDB_UPD:
2734 case ARM::t2STMIA_UPD:
2735 case ARM::t2STMDB_UPD: {
2736 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2737 if (Subtarget.isSwift()) {
2738 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2741 case ARM::VLDMDIA_UPD:
2742 case ARM::VLDMDDB_UPD:
2743 case ARM::VLDMSIA_UPD:
2744 case ARM::VLDMSDB_UPD:
2745 case ARM::VSTMDIA_UPD:
2746 case ARM::VSTMDDB_UPD:
2747 case ARM::VSTMSIA_UPD:
2748 case ARM::VSTMSDB_UPD:
2749 case ARM::LDMIA_UPD:
2750 case ARM::LDMDA_UPD:
2751 case ARM::LDMDB_UPD:
2752 case ARM::LDMIB_UPD:
2753 case ARM::STMIA_UPD:
2754 case ARM::STMDA_UPD:
2755 case ARM::STMDB_UPD:
2756 case ARM::STMIB_UPD:
2757 case ARM::tLDMIA_UPD:
2758 case ARM::tSTMIA_UPD:
2759 case ARM::t2LDMIA_UPD:
2760 case ARM::t2LDMDB_UPD:
2761 case ARM::t2STMIA_UPD:
2762 case ARM::t2STMDB_UPD:
2763 ++UOps; // One for base register writeback.
2765 case ARM::LDMIA_RET:
2767 case ARM::t2LDMIA_RET:
2768 UOps += 2; // One for base reg wb, one for write to pc.
2772 } else if (Subtarget.isCortexA8()) {
2775 // 4 registers would be issued: 2, 2.
2776 // 5 registers would be issued: 2, 2, 1.
2777 int A8UOps = (NumRegs / 2);
2781 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2782 int A9UOps = (NumRegs / 2);
2783 // If there are odd number of registers or if it's not 64-bit aligned,
2784 // then it takes an extra AGU (Address Generation Unit) cycle.
2785 if ((NumRegs % 2) ||
2786 !MI->hasOneMemOperand() ||
2787 (*MI->memoperands_begin())->getAlignment() < 8)
2791 // Assume the worst.
2799 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2800 const MCInstrDesc &DefMCID,
2802 unsigned DefIdx, unsigned DefAlign) const {
2803 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2805 // Def is the address writeback.
2806 return ItinData->getOperandCycle(DefClass, DefIdx);
2809 if (Subtarget.isCortexA8()) {
2810 // (regno / 2) + (regno % 2) + 1
2811 DefCycle = RegNo / 2 + 1;
2814 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2816 bool isSLoad = false;
2818 switch (DefMCID.getOpcode()) {
2821 case ARM::VLDMSIA_UPD:
2822 case ARM::VLDMSDB_UPD:
2827 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2828 // then it takes an extra cycle.
2829 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2832 // Assume the worst.
2833 DefCycle = RegNo + 2;
2840 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2841 const MCInstrDesc &DefMCID,
2843 unsigned DefIdx, unsigned DefAlign) const {
2844 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2846 // Def is the address writeback.
2847 return ItinData->getOperandCycle(DefClass, DefIdx);
2850 if (Subtarget.isCortexA8()) {
2851 // 4 registers would be issued: 1, 2, 1.
2852 // 5 registers would be issued: 1, 2, 2.
2853 DefCycle = RegNo / 2;
2856 // Result latency is issue cycle + 2: E2.
2858 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2859 DefCycle = (RegNo / 2);
2860 // If there are odd number of registers or if it's not 64-bit aligned,
2861 // then it takes an extra AGU (Address Generation Unit) cycle.
2862 if ((RegNo % 2) || DefAlign < 8)
2864 // Result latency is AGU cycles + 2.
2867 // Assume the worst.
2868 DefCycle = RegNo + 2;
2875 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2876 const MCInstrDesc &UseMCID,
2878 unsigned UseIdx, unsigned UseAlign) const {
2879 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2881 return ItinData->getOperandCycle(UseClass, UseIdx);
2884 if (Subtarget.isCortexA8()) {
2885 // (regno / 2) + (regno % 2) + 1
2886 UseCycle = RegNo / 2 + 1;
2889 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2891 bool isSStore = false;
2893 switch (UseMCID.getOpcode()) {
2896 case ARM::VSTMSIA_UPD:
2897 case ARM::VSTMSDB_UPD:
2902 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2903 // then it takes an extra cycle.
2904 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2907 // Assume the worst.
2908 UseCycle = RegNo + 2;
2915 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2916 const MCInstrDesc &UseMCID,
2918 unsigned UseIdx, unsigned UseAlign) const {
2919 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2921 return ItinData->getOperandCycle(UseClass, UseIdx);
2924 if (Subtarget.isCortexA8()) {
2925 UseCycle = RegNo / 2;
2930 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2931 UseCycle = (RegNo / 2);
2932 // If there are odd number of registers or if it's not 64-bit aligned,
2933 // then it takes an extra AGU (Address Generation Unit) cycle.
2934 if ((RegNo % 2) || UseAlign < 8)
2937 // Assume the worst.
2944 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2945 const MCInstrDesc &DefMCID,
2946 unsigned DefIdx, unsigned DefAlign,
2947 const MCInstrDesc &UseMCID,
2948 unsigned UseIdx, unsigned UseAlign) const {
2949 unsigned DefClass = DefMCID.getSchedClass();
2950 unsigned UseClass = UseMCID.getSchedClass();
2952 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2953 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2955 // This may be a def / use of a variable_ops instruction, the operand
2956 // latency might be determinable dynamically. Let the target try to
2959 bool LdmBypass = false;
2960 switch (DefMCID.getOpcode()) {
2962 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2966 case ARM::VLDMDIA_UPD:
2967 case ARM::VLDMDDB_UPD:
2969 case ARM::VLDMSIA_UPD:
2970 case ARM::VLDMSDB_UPD:
2971 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2974 case ARM::LDMIA_RET:
2979 case ARM::LDMIA_UPD:
2980 case ARM::LDMDA_UPD:
2981 case ARM::LDMDB_UPD:
2982 case ARM::LDMIB_UPD:
2984 case ARM::tLDMIA_UPD:
2986 case ARM::t2LDMIA_RET:
2989 case ARM::t2LDMIA_UPD:
2990 case ARM::t2LDMDB_UPD:
2992 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2997 // We can't seem to determine the result latency of the def, assume it's 2.
3001 switch (UseMCID.getOpcode()) {
3003 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3007 case ARM::VSTMDIA_UPD:
3008 case ARM::VSTMDDB_UPD:
3010 case ARM::VSTMSIA_UPD:
3011 case ARM::VSTMSDB_UPD:
3012 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3019 case ARM::STMIA_UPD:
3020 case ARM::STMDA_UPD:
3021 case ARM::STMDB_UPD:
3022 case ARM::STMIB_UPD:
3023 case ARM::tSTMIA_UPD:
3028 case ARM::t2STMIA_UPD:
3029 case ARM::t2STMDB_UPD:
3030 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3035 // Assume it's read in the first stage.
3038 UseCycle = DefCycle - UseCycle + 1;
3041 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3042 // first def operand.
3043 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3046 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3047 UseClass, UseIdx)) {
3055 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3056 const MachineInstr *MI, unsigned Reg,
3057 unsigned &DefIdx, unsigned &Dist) {
3060 MachineBasicBlock::const_iterator I = MI; ++I;
3061 MachineBasicBlock::const_instr_iterator II =
3062 llvm::prior(I.getInstrIterator());
3063 assert(II->isInsideBundle() && "Empty bundle?");
3066 while (II->isInsideBundle()) {
3067 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3074 assert(Idx != -1 && "Cannot find bundled definition!");
3079 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3080 const MachineInstr *MI, unsigned Reg,
3081 unsigned &UseIdx, unsigned &Dist) {
3084 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3085 assert(II->isInsideBundle() && "Empty bundle?");
3086 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3088 // FIXME: This doesn't properly handle multiple uses.
3090 while (II != E && II->isInsideBundle()) {
3091 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3094 if (II->getOpcode() != ARM::t2IT)
3108 /// Return the number of cycles to add to (or subtract from) the static
3109 /// itinerary based on the def opcode and alignment. The caller will ensure that
3110 /// adjusted latency is at least one cycle.
3111 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3112 const MachineInstr *DefMI,
3113 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3115 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3116 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3117 // variants are one cycle cheaper.
3118 switch (DefMCID->getOpcode()) {
3122 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3123 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3125 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3132 case ARM::t2LDRSHs: {
3133 // Thumb2 mode: lsl only.
3134 unsigned ShAmt = DefMI->getOperand(3).getImm();
3135 if (ShAmt == 0 || ShAmt == 2)
3140 } else if (Subtarget.isSwift()) {
3141 // FIXME: Properly handle all of the latency adjustments for address
3143 switch (DefMCID->getOpcode()) {
3147 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3148 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3149 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3152 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3153 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3156 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3163 case ARM::t2LDRSHs: {
3164 // Thumb2 mode: lsl only.
3165 unsigned ShAmt = DefMI->getOperand(3).getImm();
3166 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3173 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3174 switch (DefMCID->getOpcode()) {
3180 case ARM::VLD1q8wb_fixed:
3181 case ARM::VLD1q16wb_fixed:
3182 case ARM::VLD1q32wb_fixed:
3183 case ARM::VLD1q64wb_fixed:
3184 case ARM::VLD1q8wb_register:
3185 case ARM::VLD1q16wb_register:
3186 case ARM::VLD1q32wb_register:
3187 case ARM::VLD1q64wb_register:
3194 case ARM::VLD2d8wb_fixed:
3195 case ARM::VLD2d16wb_fixed:
3196 case ARM::VLD2d32wb_fixed:
3197 case ARM::VLD2q8wb_fixed:
3198 case ARM::VLD2q16wb_fixed:
3199 case ARM::VLD2q32wb_fixed:
3200 case ARM::VLD2d8wb_register:
3201 case ARM::VLD2d16wb_register:
3202 case ARM::VLD2d32wb_register:
3203 case ARM::VLD2q8wb_register:
3204 case ARM::VLD2q16wb_register:
3205 case ARM::VLD2q32wb_register:
3210 case ARM::VLD3d8_UPD:
3211 case ARM::VLD3d16_UPD:
3212 case ARM::VLD3d32_UPD:
3213 case ARM::VLD1d64Twb_fixed:
3214 case ARM::VLD1d64Twb_register:
3215 case ARM::VLD3q8_UPD:
3216 case ARM::VLD3q16_UPD:
3217 case ARM::VLD3q32_UPD:
3222 case ARM::VLD4d8_UPD:
3223 case ARM::VLD4d16_UPD:
3224 case ARM::VLD4d32_UPD:
3225 case ARM::VLD1d64Qwb_fixed:
3226 case ARM::VLD1d64Qwb_register:
3227 case ARM::VLD4q8_UPD:
3228 case ARM::VLD4q16_UPD:
3229 case ARM::VLD4q32_UPD:
3230 case ARM::VLD1DUPq8:
3231 case ARM::VLD1DUPq16:
3232 case ARM::VLD1DUPq32:
3233 case ARM::VLD1DUPq8wb_fixed:
3234 case ARM::VLD1DUPq16wb_fixed:
3235 case ARM::VLD1DUPq32wb_fixed:
3236 case ARM::VLD1DUPq8wb_register:
3237 case ARM::VLD1DUPq16wb_register:
3238 case ARM::VLD1DUPq32wb_register:
3239 case ARM::VLD2DUPd8:
3240 case ARM::VLD2DUPd16:
3241 case ARM::VLD2DUPd32:
3242 case ARM::VLD2DUPd8wb_fixed:
3243 case ARM::VLD2DUPd16wb_fixed:
3244 case ARM::VLD2DUPd32wb_fixed:
3245 case ARM::VLD2DUPd8wb_register:
3246 case ARM::VLD2DUPd16wb_register:
3247 case ARM::VLD2DUPd32wb_register:
3248 case ARM::VLD4DUPd8:
3249 case ARM::VLD4DUPd16:
3250 case ARM::VLD4DUPd32:
3251 case ARM::VLD4DUPd8_UPD:
3252 case ARM::VLD4DUPd16_UPD:
3253 case ARM::VLD4DUPd32_UPD:
3255 case ARM::VLD1LNd16:
3256 case ARM::VLD1LNd32:
3257 case ARM::VLD1LNd8_UPD:
3258 case ARM::VLD1LNd16_UPD:
3259 case ARM::VLD1LNd32_UPD:
3261 case ARM::VLD2LNd16:
3262 case ARM::VLD2LNd32:
3263 case ARM::VLD2LNq16:
3264 case ARM::VLD2LNq32:
3265 case ARM::VLD2LNd8_UPD:
3266 case ARM::VLD2LNd16_UPD:
3267 case ARM::VLD2LNd32_UPD:
3268 case ARM::VLD2LNq16_UPD:
3269 case ARM::VLD2LNq32_UPD:
3271 case ARM::VLD4LNd16:
3272 case ARM::VLD4LNd32:
3273 case ARM::VLD4LNq16:
3274 case ARM::VLD4LNq32:
3275 case ARM::VLD4LNd8_UPD:
3276 case ARM::VLD4LNd16_UPD:
3277 case ARM::VLD4LNd32_UPD:
3278 case ARM::VLD4LNq16_UPD:
3279 case ARM::VLD4LNq32_UPD:
3280 // If the address is not 64-bit aligned, the latencies of these
3281 // instructions increases by one.
3292 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3293 const MachineInstr *DefMI, unsigned DefIdx,
3294 const MachineInstr *UseMI,
3295 unsigned UseIdx) const {
3296 // No operand latency. The caller may fall back to getInstrLatency.
3297 if (!ItinData || ItinData->isEmpty())
3300 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3301 unsigned Reg = DefMO.getReg();
3302 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3303 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3305 unsigned DefAdj = 0;
3306 if (DefMI->isBundle()) {
3307 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3308 DefMCID = &DefMI->getDesc();
3310 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3311 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3315 unsigned UseAdj = 0;
3316 if (UseMI->isBundle()) {
3318 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3319 Reg, NewUseIdx, UseAdj);
3325 UseMCID = &UseMI->getDesc();
3328 if (Reg == ARM::CPSR) {
3329 if (DefMI->getOpcode() == ARM::FMSTAT) {
3330 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3331 return Subtarget.isLikeA9() ? 1 : 20;
3334 // CPSR set and branch can be paired in the same cycle.
3335 if (UseMI->isBranch())
3338 // Otherwise it takes the instruction latency (generally one).
3339 unsigned Latency = getInstrLatency(ItinData, DefMI);
3341 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3342 // its uses. Instructions which are otherwise scheduled between them may
3343 // incur a code size penalty (not able to use the CPSR setting 16-bit
3345 if (Latency > 0 && Subtarget.isThumb2()) {
3346 const MachineFunction *MF = DefMI->getParent()->getParent();
3347 if (MF->getFunction()->getAttributes().
3348 hasAttribute(AttributeSet::FunctionIndex,
3349 Attribute::OptimizeForSize))
3355 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3358 unsigned DefAlign = DefMI->hasOneMemOperand()
3359 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3360 unsigned UseAlign = UseMI->hasOneMemOperand()
3361 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3363 // Get the itinerary's latency if possible, and handle variable_ops.
3364 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3365 *UseMCID, UseIdx, UseAlign);
3366 // Unable to find operand latency. The caller may resort to getInstrLatency.
3370 // Adjust for IT block position.
3371 int Adj = DefAdj + UseAdj;
3373 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3374 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3375 if (Adj >= 0 || (int)Latency > -Adj) {
3376 return Latency + Adj;
3378 // Return the itinerary latency, which may be zero but not less than zero.
3383 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3384 SDNode *DefNode, unsigned DefIdx,
3385 SDNode *UseNode, unsigned UseIdx) const {
3386 if (!DefNode->isMachineOpcode())
3389 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3391 if (isZeroCost(DefMCID.Opcode))
3394 if (!ItinData || ItinData->isEmpty())
3395 return DefMCID.mayLoad() ? 3 : 1;
3397 if (!UseNode->isMachineOpcode()) {
3398 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3399 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3400 return Latency <= 2 ? 1 : Latency - 1;
3402 return Latency <= 3 ? 1 : Latency - 2;
3405 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3406 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3407 unsigned DefAlign = !DefMN->memoperands_empty()
3408 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3409 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3410 unsigned UseAlign = !UseMN->memoperands_empty()
3411 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3412 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3413 UseMCID, UseIdx, UseAlign);
3416 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3417 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3418 // variants are one cycle cheaper.
3419 switch (DefMCID.getOpcode()) {
3424 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3425 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3427 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3434 case ARM::t2LDRSHs: {
3435 // Thumb2 mode: lsl only.
3437 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3438 if (ShAmt == 0 || ShAmt == 2)
3443 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3444 // FIXME: Properly handle all of the latency adjustments for address
3446 switch (DefMCID.getOpcode()) {
3451 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3452 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3454 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3455 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3457 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3464 case ARM::t2LDRSHs: {
3465 // Thumb2 mode: lsl 0-3 only.
3472 if (DefAlign < 8 && Subtarget.isLikeA9())
3473 switch (DefMCID.getOpcode()) {
3479 case ARM::VLD1q8wb_register:
3480 case ARM::VLD1q16wb_register:
3481 case ARM::VLD1q32wb_register:
3482 case ARM::VLD1q64wb_register:
3483 case ARM::VLD1q8wb_fixed:
3484 case ARM::VLD1q16wb_fixed:
3485 case ARM::VLD1q32wb_fixed:
3486 case ARM::VLD1q64wb_fixed:
3490 case ARM::VLD2q8Pseudo:
3491 case ARM::VLD2q16Pseudo:
3492 case ARM::VLD2q32Pseudo:
3493 case ARM::VLD2d8wb_fixed:
3494 case ARM::VLD2d16wb_fixed:
3495 case ARM::VLD2d32wb_fixed:
3496 case ARM::VLD2q8PseudoWB_fixed:
3497 case ARM::VLD2q16PseudoWB_fixed:
3498 case ARM::VLD2q32PseudoWB_fixed:
3499 case ARM::VLD2d8wb_register:
3500 case ARM::VLD2d16wb_register:
3501 case ARM::VLD2d32wb_register:
3502 case ARM::VLD2q8PseudoWB_register:
3503 case ARM::VLD2q16PseudoWB_register:
3504 case ARM::VLD2q32PseudoWB_register:
3505 case ARM::VLD3d8Pseudo:
3506 case ARM::VLD3d16Pseudo:
3507 case ARM::VLD3d32Pseudo:
3508 case ARM::VLD1d64TPseudo:
3509 case ARM::VLD3d8Pseudo_UPD:
3510 case ARM::VLD3d16Pseudo_UPD:
3511 case ARM::VLD3d32Pseudo_UPD:
3512 case ARM::VLD3q8Pseudo_UPD:
3513 case ARM::VLD3q16Pseudo_UPD:
3514 case ARM::VLD3q32Pseudo_UPD:
3515 case ARM::VLD3q8oddPseudo:
3516 case ARM::VLD3q16oddPseudo:
3517 case ARM::VLD3q32oddPseudo:
3518 case ARM::VLD3q8oddPseudo_UPD:
3519 case ARM::VLD3q16oddPseudo_UPD:
3520 case ARM::VLD3q32oddPseudo_UPD:
3521 case ARM::VLD4d8Pseudo:
3522 case ARM::VLD4d16Pseudo:
3523 case ARM::VLD4d32Pseudo:
3524 case ARM::VLD1d64QPseudo:
3525 case ARM::VLD4d8Pseudo_UPD:
3526 case ARM::VLD4d16Pseudo_UPD:
3527 case ARM::VLD4d32Pseudo_UPD:
3528 case ARM::VLD4q8Pseudo_UPD:
3529 case ARM::VLD4q16Pseudo_UPD:
3530 case ARM::VLD4q32Pseudo_UPD:
3531 case ARM::VLD4q8oddPseudo:
3532 case ARM::VLD4q16oddPseudo:
3533 case ARM::VLD4q32oddPseudo:
3534 case ARM::VLD4q8oddPseudo_UPD:
3535 case ARM::VLD4q16oddPseudo_UPD:
3536 case ARM::VLD4q32oddPseudo_UPD:
3537 case ARM::VLD1DUPq8:
3538 case ARM::VLD1DUPq16:
3539 case ARM::VLD1DUPq32:
3540 case ARM::VLD1DUPq8wb_fixed:
3541 case ARM::VLD1DUPq16wb_fixed:
3542 case ARM::VLD1DUPq32wb_fixed:
3543 case ARM::VLD1DUPq8wb_register:
3544 case ARM::VLD1DUPq16wb_register:
3545 case ARM::VLD1DUPq32wb_register:
3546 case ARM::VLD2DUPd8:
3547 case ARM::VLD2DUPd16:
3548 case ARM::VLD2DUPd32:
3549 case ARM::VLD2DUPd8wb_fixed:
3550 case ARM::VLD2DUPd16wb_fixed:
3551 case ARM::VLD2DUPd32wb_fixed:
3552 case ARM::VLD2DUPd8wb_register:
3553 case ARM::VLD2DUPd16wb_register:
3554 case ARM::VLD2DUPd32wb_register:
3555 case ARM::VLD4DUPd8Pseudo:
3556 case ARM::VLD4DUPd16Pseudo:
3557 case ARM::VLD4DUPd32Pseudo:
3558 case ARM::VLD4DUPd8Pseudo_UPD:
3559 case ARM::VLD4DUPd16Pseudo_UPD:
3560 case ARM::VLD4DUPd32Pseudo_UPD:
3561 case ARM::VLD1LNq8Pseudo:
3562 case ARM::VLD1LNq16Pseudo:
3563 case ARM::VLD1LNq32Pseudo:
3564 case ARM::VLD1LNq8Pseudo_UPD:
3565 case ARM::VLD1LNq16Pseudo_UPD:
3566 case ARM::VLD1LNq32Pseudo_UPD:
3567 case ARM::VLD2LNd8Pseudo:
3568 case ARM::VLD2LNd16Pseudo:
3569 case ARM::VLD2LNd32Pseudo:
3570 case ARM::VLD2LNq16Pseudo:
3571 case ARM::VLD2LNq32Pseudo:
3572 case ARM::VLD2LNd8Pseudo_UPD:
3573 case ARM::VLD2LNd16Pseudo_UPD:
3574 case ARM::VLD2LNd32Pseudo_UPD:
3575 case ARM::VLD2LNq16Pseudo_UPD:
3576 case ARM::VLD2LNq32Pseudo_UPD:
3577 case ARM::VLD4LNd8Pseudo:
3578 case ARM::VLD4LNd16Pseudo:
3579 case ARM::VLD4LNd32Pseudo:
3580 case ARM::VLD4LNq16Pseudo:
3581 case ARM::VLD4LNq32Pseudo:
3582 case ARM::VLD4LNd8Pseudo_UPD:
3583 case ARM::VLD4LNd16Pseudo_UPD:
3584 case ARM::VLD4LNd32Pseudo_UPD:
3585 case ARM::VLD4LNq16Pseudo_UPD:
3586 case ARM::VLD4LNq32Pseudo_UPD:
3587 // If the address is not 64-bit aligned, the latencies of these
3588 // instructions increases by one.
3596 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3597 const MachineInstr *MI,
3598 unsigned *PredCost) const {
3599 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3600 MI->isRegSequence() || MI->isImplicitDef())
3603 // An instruction scheduler typically runs on unbundled instructions, however
3604 // other passes may query the latency of a bundled instruction.
3605 if (MI->isBundle()) {
3606 unsigned Latency = 0;
3607 MachineBasicBlock::const_instr_iterator I = MI;
3608 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3609 while (++I != E && I->isInsideBundle()) {
3610 if (I->getOpcode() != ARM::t2IT)
3611 Latency += getInstrLatency(ItinData, I, PredCost);
3616 const MCInstrDesc &MCID = MI->getDesc();
3617 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3618 // When predicated, CPSR is an additional source operand for CPSR updating
3619 // instructions, this apparently increases their latencies.
3622 // Be sure to call getStageLatency for an empty itinerary in case it has a
3623 // valid MinLatency property.
3625 return MI->mayLoad() ? 3 : 1;
3627 unsigned Class = MCID.getSchedClass();
3629 // For instructions with variable uops, use uops as latency.
3630 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3631 return getNumMicroOps(ItinData, MI);
3633 // For the common case, fall back on the itinerary's latency.
3634 unsigned Latency = ItinData->getStageLatency(Class);
3636 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3637 unsigned DefAlign = MI->hasOneMemOperand()
3638 ? (*MI->memoperands_begin())->getAlignment() : 0;
3639 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3640 if (Adj >= 0 || (int)Latency > -Adj) {
3641 return Latency + Adj;
3646 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3647 SDNode *Node) const {
3648 if (!Node->isMachineOpcode())
3651 if (!ItinData || ItinData->isEmpty())
3654 unsigned Opcode = Node->getMachineOpcode();
3657 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3664 bool ARMBaseInstrInfo::
3665 hasHighOperandLatency(const InstrItineraryData *ItinData,
3666 const MachineRegisterInfo *MRI,
3667 const MachineInstr *DefMI, unsigned DefIdx,
3668 const MachineInstr *UseMI, unsigned UseIdx) const {
3669 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3670 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3671 if (Subtarget.isCortexA8() &&
3672 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3673 // CortexA8 VFP instructions are not pipelined.
3676 // Hoist VFP / NEON instructions with 4 or higher latency.
3677 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3679 Latency = getInstrLatency(ItinData, DefMI);
3682 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3683 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3686 bool ARMBaseInstrInfo::
3687 hasLowDefLatency(const InstrItineraryData *ItinData,
3688 const MachineInstr *DefMI, unsigned DefIdx) const {
3689 if (!ItinData || ItinData->isEmpty())
3692 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3693 if (DDomain == ARMII::DomainGeneral) {
3694 unsigned DefClass = DefMI->getDesc().getSchedClass();
3695 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3696 return (DefCycle != -1 && DefCycle <= 2);
3701 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3702 StringRef &ErrInfo) const {
3703 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3704 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3711 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3712 unsigned &AddSubOpc,
3713 bool &NegAcc, bool &HasLane) const {
3714 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3715 if (I == MLxEntryMap.end())
3718 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3719 MulOpc = Entry.MulOpc;
3720 AddSubOpc = Entry.AddSubOpc;
3721 NegAcc = Entry.NegAcc;
3722 HasLane = Entry.HasLane;
3726 //===----------------------------------------------------------------------===//
3727 // Execution domains.
3728 //===----------------------------------------------------------------------===//
3730 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3731 // and some can go down both. The vmov instructions go down the VFP pipeline,
3732 // but they can be changed to vorr equivalents that are executed by the NEON
3735 // We use the following execution domain numbering:
3743 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3745 std::pair<uint16_t, uint16_t>
3746 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3747 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3748 // if they are not predicated.
3749 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3750 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3752 // CortexA9 is particularly picky about mixing the two and wants these
3754 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3755 (MI->getOpcode() == ARM::VMOVRS ||
3756 MI->getOpcode() == ARM::VMOVSR ||
3757 MI->getOpcode() == ARM::VMOVS))
3758 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3760 // No other instructions can be swizzled, so just determine their domain.
3761 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3763 if (Domain & ARMII::DomainNEON)
3764 return std::make_pair(ExeNEON, 0);
3766 // Certain instructions can go either way on Cortex-A8.
3767 // Treat them as NEON instructions.
3768 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3769 return std::make_pair(ExeNEON, 0);
3771 if (Domain & ARMII::DomainVFP)
3772 return std::make_pair(ExeVFP, 0);
3774 return std::make_pair(ExeGeneric, 0);
3777 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3778 unsigned SReg, unsigned &Lane) {
3779 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3782 if (DReg != ARM::NoRegister)
3786 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3788 assert(DReg && "S-register with no D super-register?");
3792 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
3793 /// set ImplicitSReg to a register number that must be marked as implicit-use or
3794 /// zero if no register needs to be defined as implicit-use.
3796 /// If the function cannot determine if an SPR should be marked implicit use or
3797 /// not, it returns false.
3799 /// This function handles cases where an instruction is being modified from taking
3800 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
3801 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
3802 /// lane of the DPR).
3804 /// If the other SPR is defined, an implicit-use of it should be added. Else,
3805 /// (including the case where the DPR itself is defined), it should not.
3807 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
3809 unsigned DReg, unsigned Lane,
3810 unsigned &ImplicitSReg) {
3811 // If the DPR is defined or used already, the other SPR lane will be chained
3812 // correctly, so there is nothing to be done.
3813 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
3818 // Otherwise we need to go searching to see if the SPR is set explicitly.
3819 ImplicitSReg = TRI->getSubReg(DReg,
3820 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
3821 MachineBasicBlock::LivenessQueryResult LQR =
3822 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
3824 if (LQR == MachineBasicBlock::LQR_Live)
3826 else if (LQR == MachineBasicBlock::LQR_Unknown)
3829 // If the register is known not to be live, there is no need to add an
3836 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3837 unsigned DstReg, SrcReg, DReg;
3839 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3840 const TargetRegisterInfo *TRI = &getRegisterInfo();
3841 switch (MI->getOpcode()) {
3843 llvm_unreachable("cannot handle opcode!");
3846 if (Domain != ExeNEON)
3849 // Zap the predicate operands.
3850 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3852 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
3853 DstReg = MI->getOperand(0).getReg();
3854 SrcReg = MI->getOperand(1).getReg();
3856 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3857 MI->RemoveOperand(i-1);
3859 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
3860 MI->setDesc(get(ARM::VORRd));
3861 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3866 if (Domain != ExeNEON)
3868 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3870 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
3871 DstReg = MI->getOperand(0).getReg();
3872 SrcReg = MI->getOperand(1).getReg();
3874 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3875 MI->RemoveOperand(i-1);
3877 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
3879 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
3880 // Note that DSrc has been widened and the other lane may be undef, which
3881 // contaminates the entire register.
3882 MI->setDesc(get(ARM::VGETLNi32));
3883 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3884 .addReg(DReg, RegState::Undef)
3887 // The old source should be an implicit use, otherwise we might think it
3888 // was dead before here.
3889 MIB.addReg(SrcReg, RegState::Implicit);
3892 if (Domain != ExeNEON)
3894 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3896 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
3897 DstReg = MI->getOperand(0).getReg();
3898 SrcReg = MI->getOperand(1).getReg();
3900 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
3902 unsigned ImplicitSReg;
3903 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
3906 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3907 MI->RemoveOperand(i-1);
3909 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
3910 // Again DDst may be undefined at the beginning of this instruction.
3911 MI->setDesc(get(ARM::VSETLNi32));
3912 MIB.addReg(DReg, RegState::Define)
3913 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
3916 AddDefaultPred(MIB);
3918 // The narrower destination must be marked as set to keep previous chains
3920 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3921 if (ImplicitSReg != 0)
3922 MIB.addReg(ImplicitSReg, RegState::Implicit);
3926 if (Domain != ExeNEON)
3929 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
3930 DstReg = MI->getOperand(0).getReg();
3931 SrcReg = MI->getOperand(1).getReg();
3933 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
3934 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
3935 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
3937 unsigned ImplicitSReg;
3938 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
3941 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3942 MI->RemoveOperand(i-1);
3945 // Destination can be:
3946 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
3947 MI->setDesc(get(ARM::VDUPLN32d));
3948 MIB.addReg(DDst, RegState::Define)
3949 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
3951 AddDefaultPred(MIB);
3953 // Neither the source or the destination are naturally represented any
3954 // more, so add them in manually.
3955 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3956 MIB.addReg(SrcReg, RegState::Implicit);
3957 if (ImplicitSReg != 0)
3958 MIB.addReg(ImplicitSReg, RegState::Implicit);
3962 // In general there's no single instruction that can perform an S <-> S
3963 // move in NEON space, but a pair of VEXT instructions *can* do the
3964 // job. It turns out that the VEXTs needed will only use DSrc once, with
3965 // the position based purely on the combination of lane-0 and lane-1
3966 // involved. For example
3967 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
3968 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
3969 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
3970 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
3972 // Pattern of the MachineInstrs is:
3973 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
3974 MachineInstrBuilder NewMIB;
3975 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
3976 get(ARM::VEXTd32), DDst);
3978 // On the first instruction, both DSrc and DDst may be <undef> if present.
3979 // Specifically when the original instruction didn't have them as an
3981 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
3982 bool CurUndef = !MI->readsRegister(CurReg, TRI);
3983 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
3985 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
3986 CurUndef = !MI->readsRegister(CurReg, TRI);
3987 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
3990 AddDefaultPred(NewMIB);
3992 if (SrcLane == DstLane)
3993 NewMIB.addReg(SrcReg, RegState::Implicit);
3995 MI->setDesc(get(ARM::VEXTd32));
3996 MIB.addReg(DDst, RegState::Define);
3998 // On the second instruction, DDst has definitely been defined above, so
3999 // it is not <undef>. DSrc, if present, can be <undef> as above.
4000 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4001 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4002 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4004 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4005 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4006 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4009 AddDefaultPred(MIB);
4011 if (SrcLane != DstLane)
4012 MIB.addReg(SrcReg, RegState::Implicit);
4014 // As before, the original destination is no longer represented, add it
4016 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4017 if (ImplicitSReg != 0)
4018 MIB.addReg(ImplicitSReg, RegState::Implicit);
4025 //===----------------------------------------------------------------------===//
4026 // Partial register updates
4027 //===----------------------------------------------------------------------===//
4029 // Swift renames NEON registers with 64-bit granularity. That means any
4030 // instruction writing an S-reg implicitly reads the containing D-reg. The
4031 // problem is mostly avoided by translating f32 operations to v2f32 operations
4032 // on D-registers, but f32 loads are still a problem.
4034 // These instructions can load an f32 into a NEON register:
4036 // VLDRS - Only writes S, partial D update.
4037 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4038 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4040 // FCONSTD can be used as a dependency-breaking instruction.
4041 unsigned ARMBaseInstrInfo::
4042 getPartialRegUpdateClearance(const MachineInstr *MI,
4044 const TargetRegisterInfo *TRI) const {
4045 if (!SwiftPartialUpdateClearance ||
4046 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4049 assert(TRI && "Need TRI instance");
4051 const MachineOperand &MO = MI->getOperand(OpNum);
4054 unsigned Reg = MO.getReg();
4057 switch(MI->getOpcode()) {
4058 // Normal instructions writing only an S-register.
4063 case ARM::VMOVv4i16:
4064 case ARM::VMOVv2i32:
4065 case ARM::VMOVv2f32:
4066 case ARM::VMOVv1i64:
4067 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4070 // Explicitly reads the dependency.
4071 case ARM::VLD1LNd32:
4078 // If this instruction actually reads a value from Reg, there is no unwanted
4080 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4083 // We must be able to clobber the whole D-reg.
4084 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4085 // Virtual register must be a foo:ssub_0<def,undef> operand.
4086 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4088 } else if (ARM::SPRRegClass.contains(Reg)) {
4089 // Physical register: MI must define the full D-reg.
4090 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4092 if (!DReg || !MI->definesRegister(DReg, TRI))
4096 // MI has an unwanted D-register dependency.
4097 // Avoid defs in the previous N instructrions.
4098 return SwiftPartialUpdateClearance;
4101 // Break a partial register dependency after getPartialRegUpdateClearance
4102 // returned non-zero.
4103 void ARMBaseInstrInfo::
4104 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4106 const TargetRegisterInfo *TRI) const {
4107 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4108 assert(TRI && "Need TRI instance");
4110 const MachineOperand &MO = MI->getOperand(OpNum);
4111 unsigned Reg = MO.getReg();
4112 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4113 "Can't break virtual register dependencies.");
4114 unsigned DReg = Reg;
4116 // If MI defines an S-reg, find the corresponding D super-register.
4117 if (ARM::SPRRegClass.contains(Reg)) {
4118 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4119 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4122 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4123 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4125 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4126 // the full D-register by loading the same value to both lanes. The
4127 // instruction is micro-coded with 2 uops, so don't do this until we can
4128 // properly schedule micro-coded instuctions. The dispatcher stalls cause
4129 // too big regressions.
4131 // Insert the dependency-breaking FCONSTD before MI.
4132 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4133 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4134 get(ARM::FCONSTD), DReg).addImm(96));
4135 MI->addRegisterKilled(DReg, TRI, true);
4138 bool ARMBaseInstrInfo::hasNOP() const {
4139 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4142 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4143 if (MI->getNumOperands() < 4)
4145 unsigned ShOpVal = MI->getOperand(3).getImm();
4146 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4147 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4148 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4149 ((ShImm == 1 || ShImm == 2) &&
4150 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))