1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMGenInstrInfo.inc"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231 storeRegToStackSlot(MBB, MI, Reg, isKill,
232 CSI[i].getFrameIdx(), RC, TRI);
239 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240 MachineBasicBlock *&FBB,
241 SmallVectorImpl<MachineOperand> &Cond,
242 bool AllowModify) const {
243 // If the block has no terminators, it just falls into the block after it.
244 MachineBasicBlock::iterator I = MBB.end();
245 if (I == MBB.begin())
248 while (I->isDebugValue()) {
249 if (I == MBB.begin())
253 if (!isUnpredicatedTerminator(I))
256 // Get the last instruction in the block.
257 MachineInstr *LastInst = I;
259 // If there is only one terminator instruction, process it.
260 unsigned LastOpc = LastInst->getOpcode();
261 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262 if (isUncondBranchOpcode(LastOpc)) {
263 TBB = LastInst->getOperand(0).getMBB();
266 if (isCondBranchOpcode(LastOpc)) {
267 // Block ends with fall-through condbranch.
268 TBB = LastInst->getOperand(0).getMBB();
269 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(LastInst->getOperand(2));
273 return true; // Can't handle indirect branch.
276 // Get the instruction before it if it is a terminator.
277 MachineInstr *SecondLastInst = I;
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
283 // If the block ends with a B and a Bcc, handle it.
284 unsigned SecondLastOpc = SecondLastInst->getOpcode();
285 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286 TBB = SecondLastInst->getOperand(0).getMBB();
287 Cond.push_back(SecondLastInst->getOperand(1));
288 Cond.push_back(SecondLastInst->getOperand(2));
289 FBB = LastInst->getOperand(0).getMBB();
293 // If the block ends with two unconditional branches, handle it. The second
294 // one is not executed, so remove it.
295 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296 TBB = SecondLastInst->getOperand(0).getMBB();
299 I->eraseFromParent();
303 // ...likewise if it ends with a branch table followed by an unconditional
304 // branch. The branch folder can create these, and we must get rid of them for
305 // correctness of Thumb constant islands.
306 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307 isIndirectBranchOpcode(SecondLastOpc)) &&
308 isUncondBranchOpcode(LastOpc)) {
311 I->eraseFromParent();
315 // Otherwise, can't handle this.
320 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 while (I->isDebugValue()) {
325 if (I == MBB.begin())
329 if (!isUncondBranchOpcode(I->getOpcode()) &&
330 !isCondBranchOpcode(I->getOpcode()))
333 // Remove the branch.
334 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 if (!isCondBranchOpcode(I->getOpcode()))
343 // Remove the branch.
344 I->eraseFromParent();
349 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350 MachineBasicBlock *FBB,
351 const SmallVectorImpl<MachineOperand> &Cond,
353 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354 int BOpc = !AFI->isThumbFunction()
355 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356 int BccOpc = !AFI->isThumbFunction()
357 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
359 // Shouldn't be a fall through.
360 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361 assert((Cond.size() == 2 || Cond.size() == 0) &&
362 "ARM branch conditions have two components!");
365 if (Cond.empty()) // Unconditional branch?
366 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
368 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
373 // Two-way conditional branch.
374 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
380 bool ARMBaseInstrInfo::
381 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
387 bool ARMBaseInstrInfo::
388 PredicateInstruction(MachineInstr *MI,
389 const SmallVectorImpl<MachineOperand> &Pred) const {
390 unsigned Opc = MI->getOpcode();
391 if (isUncondBranchOpcode(Opc)) {
392 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
398 int PIdx = MI->findFirstPredOperandIdx();
400 MachineOperand &PMO = MI->getOperand(PIdx);
401 PMO.setImm(Pred[0].getImm());
402 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
408 bool ARMBaseInstrInfo::
409 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410 const SmallVectorImpl<MachineOperand> &Pred2) const {
411 if (Pred1.size() > 2 || Pred2.size() > 2)
414 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
425 return CC2 == ARMCC::HI;
427 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
429 return CC2 == ARMCC::GT;
431 return CC2 == ARMCC::LT;
435 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436 std::vector<MachineOperand> &Pred) const {
437 // FIXME: This confuses implicit_def with optional CPSR def.
438 const TargetInstrDesc &TID = MI->getDesc();
439 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
443 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444 const MachineOperand &MO = MI->getOperand(i);
445 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
454 /// isPredicable - Return true if the specified instruction can be predicated.
455 /// By default, this returns true for every instruction with a
456 /// PredicateOperand.
457 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458 const TargetInstrDesc &TID = MI->getDesc();
459 if (!TID.isPredicable())
462 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463 ARMFunctionInfo *AFI =
464 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465 return AFI->isThumb2Function();
470 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
472 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
474 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
476 assert(JTI < JT.size());
477 return JT[JTI].MBBs.size();
480 /// GetInstSize - Return the size of the specified MachineInstr.
482 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483 const MachineBasicBlock &MBB = *MI->getParent();
484 const MachineFunction *MF = MBB.getParent();
485 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
487 // Basic size info comes from the TSFlags field.
488 const TargetInstrDesc &TID = MI->getDesc();
489 uint64_t TSFlags = TID.TSFlags;
491 unsigned Opc = MI->getOpcode();
492 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
494 // If this machine instr is an inline asm, measure it.
495 if (MI->getOpcode() == ARM::INLINEASM)
496 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
501 llvm_unreachable("Unknown or unset size field for instr!");
502 case TargetOpcode::IMPLICIT_DEF:
503 case TargetOpcode::KILL:
504 case TargetOpcode::PROLOG_LABEL:
505 case TargetOpcode::EH_LABEL:
506 case TargetOpcode::DBG_VALUE:
511 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
512 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
513 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
514 case ARMII::SizeSpecial: {
516 case ARM::CONSTPOOL_ENTRY:
517 // If this machine instr is a constant pool entry, its size is recorded as
519 return MI->getOperand(2).getImm();
520 case ARM::Int_eh_sjlj_longjmp:
522 case ARM::tInt_eh_sjlj_longjmp:
524 case ARM::Int_eh_sjlj_setjmp:
525 case ARM::Int_eh_sjlj_setjmp_nofp:
527 case ARM::tInt_eh_sjlj_setjmp:
528 case ARM::t2Int_eh_sjlj_setjmp:
529 case ARM::t2Int_eh_sjlj_setjmp_nofp:
538 // These are jumptable branches, i.e. a branch followed by an inlined
539 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540 // entry is one byte; TBH two byte each.
541 unsigned EntrySize = (Opc == ARM::t2TBB)
542 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543 unsigned NumOps = TID.getNumOperands();
544 MachineOperand JTOP =
545 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546 unsigned JTI = JTOP.getIndex();
547 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
549 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550 assert(JTI < JT.size());
551 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552 // 4 aligned. The assembler / linker may add 2 byte padding just before
553 // the JT entries. The size does not include this padding; the
554 // constant islands pass does separate bookkeeping for it.
555 // FIXME: If we know the size of the function is less than (1 << 16) *2
556 // bytes, we can use 16-bit entries instead. Then there won't be an
558 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559 unsigned NumEntries = getNumJTEntries(JT, JTI);
560 if (Opc == ARM::t2TBB && (NumEntries & 1))
561 // Make sure the instruction that follows TBB is 2-byte aligned.
562 // FIXME: Constant island pass should insert an "ALIGN" instruction
565 return NumEntries * EntrySize + InstSize;
568 // Otherwise, pseudo-instruction sizes are zero.
573 return 0; // Not reached
577 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
578 int &FrameIndex) const {
579 switch (MI->getOpcode()) {
582 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
583 if (MI->getOperand(1).isFI() &&
584 MI->getOperand(2).isReg() &&
585 MI->getOperand(3).isImm() &&
586 MI->getOperand(2).getReg() == 0 &&
587 MI->getOperand(3).getImm() == 0) {
588 FrameIndex = MI->getOperand(1).getIndex();
589 return MI->getOperand(0).getReg();
594 if (MI->getOperand(1).isFI() &&
595 MI->getOperand(2).isImm() &&
596 MI->getOperand(2).getImm() == 0) {
597 FrameIndex = MI->getOperand(1).getIndex();
598 return MI->getOperand(0).getReg();
603 if (MI->getOperand(1).isFI() &&
604 MI->getOperand(2).isImm() &&
605 MI->getOperand(2).getImm() == 0) {
606 FrameIndex = MI->getOperand(1).getIndex();
607 return MI->getOperand(0).getReg();
616 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
617 int &FrameIndex) const {
618 switch (MI->getOpcode()) {
621 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
622 if (MI->getOperand(1).isFI() &&
623 MI->getOperand(2).isReg() &&
624 MI->getOperand(3).isImm() &&
625 MI->getOperand(2).getReg() == 0 &&
626 MI->getOperand(3).getImm() == 0) {
627 FrameIndex = MI->getOperand(1).getIndex();
628 return MI->getOperand(0).getReg();
633 if (MI->getOperand(1).isFI() &&
634 MI->getOperand(2).isImm() &&
635 MI->getOperand(2).getImm() == 0) {
636 FrameIndex = MI->getOperand(1).getIndex();
637 return MI->getOperand(0).getReg();
642 if (MI->getOperand(1).isFI() &&
643 MI->getOperand(2).isImm() &&
644 MI->getOperand(2).getImm() == 0) {
645 FrameIndex = MI->getOperand(1).getIndex();
646 return MI->getOperand(0).getReg();
654 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator I, DebugLoc DL,
656 unsigned DestReg, unsigned SrcReg,
657 bool KillSrc) const {
658 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
659 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
661 if (GPRDest && GPRSrc) {
662 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
663 .addReg(SrcReg, getKillRegState(KillSrc))));
667 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
668 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
671 if (SPRDest && SPRSrc)
673 else if (GPRDest && SPRSrc)
675 else if (SPRDest && GPRSrc)
677 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
679 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
681 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
683 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
686 llvm_unreachable("Impossible reg-to-reg copy");
688 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
689 MIB.addReg(SrcReg, getKillRegState(KillSrc));
690 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
695 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
696 unsigned Reg, unsigned SubIdx, unsigned State,
697 const TargetRegisterInfo *TRI) {
699 return MIB.addReg(Reg, State);
701 if (TargetRegisterInfo::isPhysicalRegister(Reg))
702 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
703 return MIB.addReg(Reg, State, SubIdx);
706 void ARMBaseInstrInfo::
707 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
708 unsigned SrcReg, bool isKill, int FI,
709 const TargetRegisterClass *RC,
710 const TargetRegisterInfo *TRI) const {
712 if (I != MBB.end()) DL = I->getDebugLoc();
713 MachineFunction &MF = *MBB.getParent();
714 MachineFrameInfo &MFI = *MF.getFrameInfo();
715 unsigned Align = MFI.getObjectAlignment(FI);
717 MachineMemOperand *MMO =
718 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
719 MachineMemOperand::MOStore, 0,
720 MFI.getObjectSize(FI),
723 // tGPR is used sometimes in ARM instructions that need to avoid using
724 // certain registers. Just treat it as GPR here. Likewise, rGPR.
725 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
726 || RC == ARM::rGPRRegisterClass)
727 RC = ARM::GPRRegisterClass;
729 switch (RC->getID()) {
730 case ARM::GPRRegClassID:
731 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
732 .addReg(SrcReg, getKillRegState(isKill))
733 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
735 case ARM::SPRRegClassID:
736 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
737 .addReg(SrcReg, getKillRegState(isKill))
738 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
740 case ARM::DPRRegClassID:
741 case ARM::DPR_VFP2RegClassID:
742 case ARM::DPR_8RegClassID:
743 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
744 .addReg(SrcReg, getKillRegState(isKill))
745 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
747 case ARM::QPRRegClassID:
748 case ARM::QPR_VFP2RegClassID:
749 case ARM::QPR_8RegClassID:
750 // FIXME: Neon instructions should support predicates
751 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
752 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
753 .addFrameIndex(FI).addImm(16)
754 .addReg(SrcReg, getKillRegState(isKill))
755 .addMemOperand(MMO));
757 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
758 .addReg(SrcReg, getKillRegState(isKill))
760 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
761 .addMemOperand(MMO));
764 case ARM::QQPRRegClassID:
765 case ARM::QQPR_VFP2RegClassID:
766 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
767 // FIXME: It's possible to only store part of the QQ register if the
768 // spilled def has a sub-register index.
769 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1d64Q))
770 .addFrameIndex(FI).addImm(16);
771 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
772 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
773 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
774 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
775 AddDefaultPred(MIB.addMemOperand(MMO));
777 MachineInstrBuilder MIB =
778 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
780 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
782 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
783 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
784 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
785 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
788 case ARM::QQQQPRRegClassID: {
789 MachineInstrBuilder MIB =
790 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
792 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
794 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
795 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
796 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
797 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
798 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
799 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
800 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
801 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
805 llvm_unreachable("Unknown regclass!");
809 void ARMBaseInstrInfo::
810 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
811 unsigned DestReg, int FI,
812 const TargetRegisterClass *RC,
813 const TargetRegisterInfo *TRI) const {
815 if (I != MBB.end()) DL = I->getDebugLoc();
816 MachineFunction &MF = *MBB.getParent();
817 MachineFrameInfo &MFI = *MF.getFrameInfo();
818 unsigned Align = MFI.getObjectAlignment(FI);
819 MachineMemOperand *MMO =
820 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
821 MachineMemOperand::MOLoad, 0,
822 MFI.getObjectSize(FI),
825 // tGPR is used sometimes in ARM instructions that need to avoid using
826 // certain registers. Just treat it as GPR here.
827 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
828 || RC == ARM::rGPRRegisterClass)
829 RC = ARM::GPRRegisterClass;
831 switch (RC->getID()) {
832 case ARM::GPRRegClassID:
833 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
834 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
836 case ARM::SPRRegClassID:
837 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
838 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
840 case ARM::DPRRegClassID:
841 case ARM::DPR_VFP2RegClassID:
842 case ARM::DPR_8RegClassID:
843 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
844 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
846 case ARM::QPRRegClassID:
847 case ARM::QPR_VFP2RegClassID:
848 case ARM::QPR_8RegClassID:
849 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
850 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
851 .addFrameIndex(FI).addImm(16)
852 .addMemOperand(MMO));
854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
856 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
857 .addMemOperand(MMO));
860 case ARM::QQPRRegClassID:
861 case ARM::QQPR_VFP2RegClassID:
862 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
863 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1d64Q));
864 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
865 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
866 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
867 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
868 AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO));
870 MachineInstrBuilder MIB =
871 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
873 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
875 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
876 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
877 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
878 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
881 case ARM::QQQQPRRegClassID: {
882 MachineInstrBuilder MIB =
883 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
885 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
887 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
888 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
889 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
890 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
891 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
892 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
893 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
894 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
898 llvm_unreachable("Unknown regclass!");
903 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
904 int FrameIx, uint64_t Offset,
907 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
908 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
912 /// Create a copy of a const pool value. Update CPI to the new index and return
914 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
915 MachineConstantPool *MCP = MF.getConstantPool();
916 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
918 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
919 assert(MCPE.isMachineConstantPoolEntry() &&
920 "Expecting a machine constantpool entry!");
921 ARMConstantPoolValue *ACPV =
922 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
924 unsigned PCLabelId = AFI->createConstPoolEntryUId();
925 ARMConstantPoolValue *NewCPV = 0;
926 if (ACPV->isGlobalValue())
927 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
929 else if (ACPV->isExtSymbol())
930 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
931 ACPV->getSymbol(), PCLabelId, 4);
932 else if (ACPV->isBlockAddress())
933 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
934 ARMCP::CPBlockAddress, 4);
936 llvm_unreachable("Unexpected ARM constantpool value type!!");
937 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
941 void ARMBaseInstrInfo::
942 reMaterialize(MachineBasicBlock &MBB,
943 MachineBasicBlock::iterator I,
944 unsigned DestReg, unsigned SubIdx,
945 const MachineInstr *Orig,
946 const TargetRegisterInfo &TRI) const {
947 unsigned Opcode = Orig->getOpcode();
950 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
951 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
955 case ARM::tLDRpci_pic:
956 case ARM::t2LDRpci_pic: {
957 MachineFunction &MF = *MBB.getParent();
958 unsigned CPI = Orig->getOperand(1).getIndex();
959 unsigned PCLabelId = duplicateCPV(MF, CPI);
960 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
962 .addConstantPoolIndex(CPI).addImm(PCLabelId);
963 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
970 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
971 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
972 switch(Orig->getOpcode()) {
973 case ARM::tLDRpci_pic:
974 case ARM::t2LDRpci_pic: {
975 unsigned CPI = Orig->getOperand(1).getIndex();
976 unsigned PCLabelId = duplicateCPV(MF, CPI);
977 Orig->getOperand(1).setIndex(CPI);
978 Orig->getOperand(2).setImm(PCLabelId);
985 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
986 const MachineInstr *MI1) const {
987 int Opcode = MI0->getOpcode();
988 if (Opcode == ARM::t2LDRpci ||
989 Opcode == ARM::t2LDRpci_pic ||
990 Opcode == ARM::tLDRpci ||
991 Opcode == ARM::tLDRpci_pic) {
992 if (MI1->getOpcode() != Opcode)
994 if (MI0->getNumOperands() != MI1->getNumOperands())
997 const MachineOperand &MO0 = MI0->getOperand(1);
998 const MachineOperand &MO1 = MI1->getOperand(1);
999 if (MO0.getOffset() != MO1.getOffset())
1002 const MachineFunction *MF = MI0->getParent()->getParent();
1003 const MachineConstantPool *MCP = MF->getConstantPool();
1004 int CPI0 = MO0.getIndex();
1005 int CPI1 = MO1.getIndex();
1006 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1007 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1008 ARMConstantPoolValue *ACPV0 =
1009 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1010 ARMConstantPoolValue *ACPV1 =
1011 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1012 return ACPV0->hasSameValue(ACPV1);
1015 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1018 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1019 /// determine if two loads are loading from the same base address. It should
1020 /// only return true if the base pointers are the same and the only differences
1021 /// between the two addresses is the offset. It also returns the offsets by
1023 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1025 int64_t &Offset2) const {
1026 // Don't worry about Thumb: just ARM and Thumb2.
1027 if (Subtarget.isThumb1Only()) return false;
1029 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1032 switch (Load1->getMachineOpcode()) {
1045 case ARM::t2LDRSHi8:
1047 case ARM::t2LDRSHi12:
1051 switch (Load2->getMachineOpcode()) {
1064 case ARM::t2LDRSHi8:
1066 case ARM::t2LDRSHi12:
1070 // Check if base addresses and chain operands match.
1071 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1072 Load1->getOperand(4) != Load2->getOperand(4))
1075 // Index should be Reg0.
1076 if (Load1->getOperand(3) != Load2->getOperand(3))
1079 // Determine the offsets.
1080 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1081 isa<ConstantSDNode>(Load2->getOperand(1))) {
1082 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1083 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1090 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1091 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1092 /// be scheduled togther. On some targets if two loads are loading from
1093 /// addresses in the same cache line, it's better if they are scheduled
1094 /// together. This function takes two integers that represent the load offsets
1095 /// from the common base address. It returns true if it decides it's desirable
1096 /// to schedule the two loads together. "NumLoads" is the number of loads that
1097 /// have already been scheduled after Load1.
1098 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1099 int64_t Offset1, int64_t Offset2,
1100 unsigned NumLoads) const {
1101 // Don't worry about Thumb: just ARM and Thumb2.
1102 if (Subtarget.isThumb1Only()) return false;
1104 assert(Offset2 > Offset1);
1106 if ((Offset2 - Offset1) / 8 > 64)
1109 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1110 return false; // FIXME: overly conservative?
1112 // Four loads in a row should be sufficient.
1119 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1120 const MachineBasicBlock *MBB,
1121 const MachineFunction &MF) const {
1122 // Debug info is never a scheduling boundary. It's necessary to be explicit
1123 // due to the special treatment of IT instructions below, otherwise a
1124 // dbg_value followed by an IT will result in the IT instruction being
1125 // considered a scheduling hazard, which is wrong. It should be the actual
1126 // instruction preceding the dbg_value instruction(s), just like it is
1127 // when debug info is not present.
1128 if (MI->isDebugValue())
1131 // Terminators and labels can't be scheduled around.
1132 if (MI->getDesc().isTerminator() || MI->isLabel())
1135 // Treat the start of the IT block as a scheduling boundary, but schedule
1136 // t2IT along with all instructions following it.
1137 // FIXME: This is a big hammer. But the alternative is to add all potential
1138 // true and anti dependencies to IT block instructions as implicit operands
1139 // to the t2IT instruction. The added compile time and complexity does not
1141 MachineBasicBlock::const_iterator I = MI;
1142 // Make sure to skip any dbg_value instructions
1143 while (++I != MBB->end() && I->isDebugValue())
1145 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1148 // Don't attempt to schedule around any instruction that defines
1149 // a stack-oriented pointer, as it's unlikely to be profitable. This
1150 // saves compile time, because it doesn't require every single
1151 // stack slot reference to depend on the instruction that does the
1153 if (MI->definesRegister(ARM::SP))
1159 bool ARMBaseInstrInfo::
1160 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
1163 if (Subtarget.getCPUString() == "generic")
1164 // Generic (and overly aggressive) if-conversion limits for testing.
1165 return NumInstrs <= 10;
1166 else if (Subtarget.hasV7Ops())
1167 return NumInstrs <= 3;
1168 return NumInstrs <= 2;
1171 bool ARMBaseInstrInfo::
1172 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1173 MachineBasicBlock &FMBB, unsigned NumF) const {
1174 return NumT && NumF && NumT <= 2 && NumF <= 2;
1177 /// getInstrPredicate - If instruction is predicated, returns its predicate
1178 /// condition, otherwise returns AL. It also returns the condition code
1179 /// register by reference.
1181 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1182 int PIdx = MI->findFirstPredOperandIdx();
1188 PredReg = MI->getOperand(PIdx+1).getReg();
1189 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1193 int llvm::getMatchingCondBranchOpcode(int Opc) {
1196 else if (Opc == ARM::tB)
1198 else if (Opc == ARM::t2B)
1201 llvm_unreachable("Unknown unconditional branch opcode!");
1206 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1207 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1208 unsigned DestReg, unsigned BaseReg, int NumBytes,
1209 ARMCC::CondCodes Pred, unsigned PredReg,
1210 const ARMBaseInstrInfo &TII) {
1211 bool isSub = NumBytes < 0;
1212 if (isSub) NumBytes = -NumBytes;
1215 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1216 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1217 assert(ThisVal && "Didn't extract field correctly");
1219 // We will handle these bits from offset, clear them.
1220 NumBytes &= ~ThisVal;
1222 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1224 // Build the new ADD / SUB.
1225 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1226 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1227 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1228 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1233 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1234 unsigned FrameReg, int &Offset,
1235 const ARMBaseInstrInfo &TII) {
1236 unsigned Opcode = MI.getOpcode();
1237 const TargetInstrDesc &Desc = MI.getDesc();
1238 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1241 // Memory operands in inline assembly always use AddrMode2.
1242 if (Opcode == ARM::INLINEASM)
1243 AddrMode = ARMII::AddrMode2;
1245 if (Opcode == ARM::ADDri) {
1246 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1248 // Turn it into a move.
1249 MI.setDesc(TII.get(ARM::MOVr));
1250 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1251 MI.RemoveOperand(FrameRegIdx+1);
1254 } else if (Offset < 0) {
1257 MI.setDesc(TII.get(ARM::SUBri));
1260 // Common case: small offset, fits into instruction.
1261 if (ARM_AM::getSOImmVal(Offset) != -1) {
1262 // Replace the FrameIndex with sp / fp
1263 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1264 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1269 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1271 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1272 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1274 // We will handle these bits from offset, clear them.
1275 Offset &= ~ThisImmVal;
1277 // Get the properly encoded SOImmVal field.
1278 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1279 "Bit extraction didn't work?");
1280 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1282 unsigned ImmIdx = 0;
1284 unsigned NumBits = 0;
1287 case ARMII::AddrMode2: {
1288 ImmIdx = FrameRegIdx+2;
1289 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1290 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1295 case ARMII::AddrMode3: {
1296 ImmIdx = FrameRegIdx+2;
1297 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1298 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1303 case ARMII::AddrMode4:
1304 case ARMII::AddrMode6:
1305 // Can't fold any offset even if it's zero.
1307 case ARMII::AddrMode5: {
1308 ImmIdx = FrameRegIdx+1;
1309 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1310 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1317 llvm_unreachable("Unsupported addressing mode!");
1321 Offset += InstrOffs * Scale;
1322 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1328 // Attempt to fold address comp. if opcode has offset bits
1330 // Common case: small offset, fits into instruction.
1331 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1332 int ImmedOffset = Offset / Scale;
1333 unsigned Mask = (1 << NumBits) - 1;
1334 if ((unsigned)Offset <= Mask * Scale) {
1335 // Replace the FrameIndex with sp
1336 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1338 ImmedOffset |= 1 << NumBits;
1339 ImmOp.ChangeToImmediate(ImmedOffset);
1344 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1345 ImmedOffset = ImmedOffset & Mask;
1347 ImmedOffset |= 1 << NumBits;
1348 ImmOp.ChangeToImmediate(ImmedOffset);
1349 Offset &= ~(Mask*Scale);
1353 Offset = (isSub) ? -Offset : Offset;
1357 bool ARMBaseInstrInfo::
1358 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
1359 switch (MI->getOpcode()) {
1365 SrcReg = MI->getOperand(0).getReg();
1366 CmpValue = MI->getOperand(1).getImm();
1373 /// ConvertToSetZeroFlag - Convert the instruction to set the "zero" flag so
1374 /// that we can remove a "comparison with zero".
1375 bool ARMBaseInstrInfo::
1376 ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
1377 // Conservatively refuse to convert an instruction which isn't in the same BB
1378 // as the comparison.
1379 if (MI->getParent() != CmpInstr->getParent())
1382 // Check that CPSR isn't set between the comparison instruction and the one we
1384 MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
1386 for (; I != E; --I) {
1387 const MachineInstr &Instr = *I;
1389 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1390 const MachineOperand &MO = Instr.getOperand(IO);
1391 if (!MO.isReg() || !MO.isDef()) continue;
1393 // This instruction modifies CPSR before the one we want to change. We
1394 // can't do this transformation.
1395 if (MO.getReg() == ARM::CPSR)
1400 // Set the "zero" bit in CPSR.
1401 switch (MI->getOpcode()) {
1407 MI->RemoveOperand(5);
1408 MachineInstrBuilder(MI)
1409 .addReg(ARM::CPSR, RegState::Define | RegState::Implicit);
1410 CmpInstr->eraseFromParent();