1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 unsigned LastOpc = LastInst->getOpcode();
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216 if (isUncondBranchOpcode(LastOpc)) {
217 TBB = LastInst->getOperand(0).getMBB();
220 if (isCondBranchOpcode(LastOpc)) {
221 // Block ends with fall-through condbranch.
222 TBB = LastInst->getOperand(0).getMBB();
223 Cond.push_back(LastInst->getOperand(1));
224 Cond.push_back(LastInst->getOperand(2));
227 return true; // Can't handle indirect branch.
230 // Get the instruction before it if it is a terminator.
231 MachineInstr *SecondLastInst = I;
233 // If there are three terminators, we don't know what sort of block this is.
234 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
237 // If the block ends with a B and a Bcc, handle it.
238 unsigned SecondLastOpc = SecondLastInst->getOpcode();
239 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240 TBB = SecondLastInst->getOperand(0).getMBB();
241 Cond.push_back(SecondLastInst->getOperand(1));
242 Cond.push_back(SecondLastInst->getOperand(2));
243 FBB = LastInst->getOperand(0).getMBB();
247 // If the block ends with two unconditional branches, handle it. The second
248 // one is not executed, so remove it.
249 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
250 TBB = SecondLastInst->getOperand(0).getMBB();
253 I->eraseFromParent();
257 // ...likewise if it ends with a branch table followed by an unconditional
258 // branch. The branch folder can create these, and we must get rid of them for
259 // correctness of Thumb constant islands.
260 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
261 isIndirectBranchOpcode(SecondLastOpc)) &&
262 isUncondBranchOpcode(LastOpc)) {
265 I->eraseFromParent();
269 // Otherwise, can't handle this.
274 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin()) return 0;
278 if (!isUncondBranchOpcode(I->getOpcode()) &&
279 !isCondBranchOpcode(I->getOpcode()))
282 // Remove the branch.
283 I->eraseFromParent();
287 if (I == MBB.begin()) return 1;
289 if (!isCondBranchOpcode(I->getOpcode()))
292 // Remove the branch.
293 I->eraseFromParent();
298 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
299 MachineBasicBlock *FBB,
300 const SmallVectorImpl<MachineOperand> &Cond) const {
301 // FIXME this should probably have a DebugLoc argument
302 DebugLoc dl = DebugLoc::getUnknownLoc();
304 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
305 int BOpc = !AFI->isThumbFunction()
306 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
307 int BccOpc = !AFI->isThumbFunction()
308 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
310 // Shouldn't be a fall through.
311 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
312 assert((Cond.size() == 2 || Cond.size() == 0) &&
313 "ARM branch conditions have two components!");
316 if (Cond.empty()) // Unconditional branch?
317 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
319 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
320 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
324 // Two-way conditional branch.
325 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
326 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
327 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
331 bool ARMBaseInstrInfo::
332 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
333 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
334 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
338 bool ARMBaseInstrInfo::
339 PredicateInstruction(MachineInstr *MI,
340 const SmallVectorImpl<MachineOperand> &Pred) const {
341 unsigned Opc = MI->getOpcode();
342 if (isUncondBranchOpcode(Opc)) {
343 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
344 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
345 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
349 int PIdx = MI->findFirstPredOperandIdx();
351 MachineOperand &PMO = MI->getOperand(PIdx);
352 PMO.setImm(Pred[0].getImm());
353 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
359 bool ARMBaseInstrInfo::
360 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
361 const SmallVectorImpl<MachineOperand> &Pred2) const {
362 if (Pred1.size() > 2 || Pred2.size() > 2)
365 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
366 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
376 return CC2 == ARMCC::HI;
378 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
380 return CC2 == ARMCC::GT;
382 return CC2 == ARMCC::LT;
386 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
387 std::vector<MachineOperand> &Pred) const {
388 // FIXME: This confuses implicit_def with optional CPSR def.
389 const TargetInstrDesc &TID = MI->getDesc();
390 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395 const MachineOperand &MO = MI->getOperand(i);
396 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
405 /// isPredicable - Return true if the specified instruction can be predicated.
406 /// By default, this returns true for every instruction with a
407 /// PredicateOperand.
408 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
409 const TargetInstrDesc &TID = MI->getDesc();
410 if (!TID.isPredicable())
413 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
414 ARMFunctionInfo *AFI =
415 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
416 return AFI->isThumb2Function();
421 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
423 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
425 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
427 assert(JTI < JT.size());
428 return JT[JTI].MBBs.size();
431 /// GetInstSize - Return the size of the specified MachineInstr.
433 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
434 const MachineBasicBlock &MBB = *MI->getParent();
435 const MachineFunction *MF = MBB.getParent();
436 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
438 // Basic size info comes from the TSFlags field.
439 const TargetInstrDesc &TID = MI->getDesc();
440 unsigned TSFlags = TID.TSFlags;
442 unsigned Opc = MI->getOpcode();
443 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
445 // If this machine instr is an inline asm, measure it.
446 if (MI->getOpcode() == ARM::INLINEASM)
447 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
452 llvm_unreachable("Unknown or unset size field for instr!");
453 case TargetOpcode::IMPLICIT_DEF:
454 case TargetOpcode::KILL:
455 case TargetOpcode::DBG_LABEL:
456 case TargetOpcode::EH_LABEL:
461 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
462 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
463 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
464 case ARMII::SizeSpecial: {
466 case ARM::CONSTPOOL_ENTRY:
467 // If this machine instr is a constant pool entry, its size is recorded as
469 return MI->getOperand(2).getImm();
470 case ARM::Int_eh_sjlj_setjmp:
472 case ARM::tInt_eh_sjlj_setjmp:
474 case ARM::t2Int_eh_sjlj_setjmp:
483 // These are jumptable branches, i.e. a branch followed by an inlined
484 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
485 // entry is one byte; TBH two byte each.
486 unsigned EntrySize = (Opc == ARM::t2TBB)
487 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
488 unsigned NumOps = TID.getNumOperands();
489 MachineOperand JTOP =
490 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
491 unsigned JTI = JTOP.getIndex();
492 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
494 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
495 assert(JTI < JT.size());
496 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
497 // 4 aligned. The assembler / linker may add 2 byte padding just before
498 // the JT entries. The size does not include this padding; the
499 // constant islands pass does separate bookkeeping for it.
500 // FIXME: If we know the size of the function is less than (1 << 16) *2
501 // bytes, we can use 16-bit entries instead. Then there won't be an
503 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
504 unsigned NumEntries = getNumJTEntries(JT, JTI);
505 if (Opc == ARM::t2TBB && (NumEntries & 1))
506 // Make sure the instruction that follows TBB is 2-byte aligned.
507 // FIXME: Constant island pass should insert an "ALIGN" instruction
510 return NumEntries * EntrySize + InstSize;
513 // Otherwise, pseudo-instruction sizes are zero.
518 return 0; // Not reached
521 /// Return true if the instruction is a register to register move and
522 /// leave the source and dest operands in the passed parameters.
525 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
526 unsigned &SrcReg, unsigned &DstReg,
527 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
528 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
530 switch (MI.getOpcode()) {
536 SrcReg = MI.getOperand(1).getReg();
537 DstReg = MI.getOperand(0).getReg();
542 case ARM::tMOVgpr2tgpr:
543 case ARM::tMOVtgpr2gpr:
544 case ARM::tMOVgpr2gpr:
546 assert(MI.getDesc().getNumOperands() >= 2 &&
547 MI.getOperand(0).isReg() &&
548 MI.getOperand(1).isReg() &&
549 "Invalid ARM MOV instruction");
550 SrcReg = MI.getOperand(1).getReg();
551 DstReg = MI.getOperand(0).getReg();
560 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
561 int &FrameIndex) const {
562 switch (MI->getOpcode()) {
565 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
566 if (MI->getOperand(1).isFI() &&
567 MI->getOperand(2).isReg() &&
568 MI->getOperand(3).isImm() &&
569 MI->getOperand(2).getReg() == 0 &&
570 MI->getOperand(3).getImm() == 0) {
571 FrameIndex = MI->getOperand(1).getIndex();
572 return MI->getOperand(0).getReg();
577 if (MI->getOperand(1).isFI() &&
578 MI->getOperand(2).isImm() &&
579 MI->getOperand(2).getImm() == 0) {
580 FrameIndex = MI->getOperand(1).getIndex();
581 return MI->getOperand(0).getReg();
586 if (MI->getOperand(1).isFI() &&
587 MI->getOperand(2).isImm() &&
588 MI->getOperand(2).getImm() == 0) {
589 FrameIndex = MI->getOperand(1).getIndex();
590 return MI->getOperand(0).getReg();
599 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
600 int &FrameIndex) const {
601 switch (MI->getOpcode()) {
604 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
605 if (MI->getOperand(1).isFI() &&
606 MI->getOperand(2).isReg() &&
607 MI->getOperand(3).isImm() &&
608 MI->getOperand(2).getReg() == 0 &&
609 MI->getOperand(3).getImm() == 0) {
610 FrameIndex = MI->getOperand(1).getIndex();
611 return MI->getOperand(0).getReg();
616 if (MI->getOperand(1).isFI() &&
617 MI->getOperand(2).isImm() &&
618 MI->getOperand(2).getImm() == 0) {
619 FrameIndex = MI->getOperand(1).getIndex();
620 return MI->getOperand(0).getReg();
625 if (MI->getOperand(1).isFI() &&
626 MI->getOperand(2).isImm() &&
627 MI->getOperand(2).getImm() == 0) {
628 FrameIndex = MI->getOperand(1).getIndex();
629 return MI->getOperand(0).getReg();
638 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
639 MachineBasicBlock::iterator I,
640 unsigned DestReg, unsigned SrcReg,
641 const TargetRegisterClass *DestRC,
642 const TargetRegisterClass *SrcRC) const {
643 DebugLoc DL = DebugLoc::getUnknownLoc();
644 if (I != MBB.end()) DL = I->getDebugLoc();
646 // tGPR is used sometimes in ARM instructions that need to avoid using
647 // certain registers. Just treat it as GPR here.
648 if (DestRC == ARM::tGPRRegisterClass)
649 DestRC = ARM::GPRRegisterClass;
650 if (SrcRC == ARM::tGPRRegisterClass)
651 SrcRC = ARM::GPRRegisterClass;
653 if (DestRC != SrcRC) {
654 if (DestRC->getSize() != SrcRC->getSize())
657 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
658 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
659 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
663 if (DestRC == ARM::GPRRegisterClass) {
664 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
665 DestReg).addReg(SrcReg)));
666 } else if (DestRC == ARM::SPRRegisterClass) {
667 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVS), DestReg)
669 } else if (DestRC == ARM::DPRRegisterClass) {
670 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg)
672 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
673 DestRC == ARM::DPR_8RegisterClass ||
674 SrcRC == ARM::DPR_VFP2RegisterClass ||
675 SrcRC == ARM::DPR_8RegisterClass) {
676 // Always use neon reg-reg move if source or dest is NEON-only regclass.
677 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon),
678 DestReg).addReg(SrcReg));
679 } else if (DestRC == ARM::QPRRegisterClass ||
680 DestRC == ARM::QPR_VFP2RegisterClass ||
681 DestRC == ARM::QPR_8RegisterClass) {
682 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ),
683 DestReg).addReg(SrcReg));
691 void ARMBaseInstrInfo::
692 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
693 unsigned SrcReg, bool isKill, int FI,
694 const TargetRegisterClass *RC) const {
695 DebugLoc DL = DebugLoc::getUnknownLoc();
696 if (I != MBB.end()) DL = I->getDebugLoc();
697 MachineFunction &MF = *MBB.getParent();
698 MachineFrameInfo &MFI = *MF.getFrameInfo();
699 unsigned Align = MFI.getObjectAlignment(FI);
701 MachineMemOperand *MMO =
702 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
703 MachineMemOperand::MOStore, 0,
704 MFI.getObjectSize(FI),
707 // tGPR is used sometimes in ARM instructions that need to avoid using
708 // certain registers. Just treat it as GPR here.
709 if (RC == ARM::tGPRRegisterClass)
710 RC = ARM::GPRRegisterClass;
712 if (RC == ARM::GPRRegisterClass) {
713 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
714 .addReg(SrcReg, getKillRegState(isKill))
715 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
716 } else if (RC == ARM::DPRRegisterClass ||
717 RC == ARM::DPR_VFP2RegisterClass ||
718 RC == ARM::DPR_8RegisterClass) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
720 .addReg(SrcReg, getKillRegState(isKill))
721 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
722 } else if (RC == ARM::SPRRegisterClass) {
723 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
724 .addReg(SrcReg, getKillRegState(isKill))
725 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
727 assert((RC == ARM::QPRRegisterClass ||
728 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
729 // FIXME: Neon instructions should support predicates
731 && (getRegisterInfo().canRealignStack(MF))) {
732 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
733 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
735 .addReg(SrcReg, getKillRegState(isKill)));
737 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
738 addReg(SrcReg, getKillRegState(isKill))
739 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
744 void ARMBaseInstrInfo::
745 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
746 unsigned DestReg, int FI,
747 const TargetRegisterClass *RC) const {
748 DebugLoc DL = DebugLoc::getUnknownLoc();
749 if (I != MBB.end()) DL = I->getDebugLoc();
750 MachineFunction &MF = *MBB.getParent();
751 MachineFrameInfo &MFI = *MF.getFrameInfo();
752 unsigned Align = MFI.getObjectAlignment(FI);
754 MachineMemOperand *MMO =
755 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
756 MachineMemOperand::MOLoad, 0,
757 MFI.getObjectSize(FI),
760 // tGPR is used sometimes in ARM instructions that need to avoid using
761 // certain registers. Just treat it as GPR here.
762 if (RC == ARM::tGPRRegisterClass)
763 RC = ARM::GPRRegisterClass;
765 if (RC == ARM::GPRRegisterClass) {
766 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
767 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
768 } else if (RC == ARM::DPRRegisterClass ||
769 RC == ARM::DPR_VFP2RegisterClass ||
770 RC == ARM::DPR_8RegisterClass) {
771 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
772 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
773 } else if (RC == ARM::SPRRegisterClass) {
774 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
775 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
777 assert((RC == ARM::QPRRegisterClass ||
778 RC == ARM::QPR_VFP2RegisterClass ||
779 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
781 && (getRegisterInfo().canRealignStack(MF))) {
782 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
783 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
784 .addMemOperand(MMO));
786 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg)
787 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
792 MachineInstr *ARMBaseInstrInfo::
793 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
794 const SmallVectorImpl<unsigned> &Ops, int FI) const {
795 if (Ops.size() != 1) return NULL;
797 unsigned OpNum = Ops[0];
798 unsigned Opc = MI->getOpcode();
799 MachineInstr *NewMI = NULL;
800 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
801 // If it is updating CPSR, then it cannot be folded.
802 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
804 unsigned Pred = MI->getOperand(2).getImm();
805 unsigned PredReg = MI->getOperand(3).getReg();
806 if (OpNum == 0) { // move -> store
807 unsigned SrcReg = MI->getOperand(1).getReg();
808 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
809 bool isKill = MI->getOperand(1).isKill();
810 bool isUndef = MI->getOperand(1).isUndef();
811 if (Opc == ARM::MOVr)
812 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
814 getKillRegState(isKill) | getUndefRegState(isUndef),
816 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
818 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
820 getKillRegState(isKill) | getUndefRegState(isUndef),
822 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
823 } else { // move -> load
824 unsigned DstReg = MI->getOperand(0).getReg();
825 unsigned DstSubReg = MI->getOperand(0).getSubReg();
826 bool isDead = MI->getOperand(0).isDead();
827 bool isUndef = MI->getOperand(0).isUndef();
828 if (Opc == ARM::MOVr)
829 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
832 getDeadRegState(isDead) |
833 getUndefRegState(isUndef), DstSubReg)
834 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
836 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
839 getDeadRegState(isDead) |
840 getUndefRegState(isUndef), DstSubReg)
841 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
843 } else if (Opc == ARM::tMOVgpr2gpr ||
844 Opc == ARM::tMOVtgpr2gpr ||
845 Opc == ARM::tMOVgpr2tgpr) {
846 if (OpNum == 0) { // move -> store
847 unsigned SrcReg = MI->getOperand(1).getReg();
848 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
849 bool isKill = MI->getOperand(1).isKill();
850 bool isUndef = MI->getOperand(1).isUndef();
851 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
853 getKillRegState(isKill) | getUndefRegState(isUndef),
855 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
856 } else { // move -> load
857 unsigned DstReg = MI->getOperand(0).getReg();
858 unsigned DstSubReg = MI->getOperand(0).getSubReg();
859 bool isDead = MI->getOperand(0).isDead();
860 bool isUndef = MI->getOperand(0).isUndef();
861 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
864 getDeadRegState(isDead) |
865 getUndefRegState(isUndef),
867 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
869 } else if (Opc == ARM::VMOVS) {
870 unsigned Pred = MI->getOperand(2).getImm();
871 unsigned PredReg = MI->getOperand(3).getReg();
872 if (OpNum == 0) { // move -> store
873 unsigned SrcReg = MI->getOperand(1).getReg();
874 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
875 bool isKill = MI->getOperand(1).isKill();
876 bool isUndef = MI->getOperand(1).isUndef();
877 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
878 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
881 .addImm(0).addImm(Pred).addReg(PredReg);
882 } else { // move -> load
883 unsigned DstReg = MI->getOperand(0).getReg();
884 unsigned DstSubReg = MI->getOperand(0).getSubReg();
885 bool isDead = MI->getOperand(0).isDead();
886 bool isUndef = MI->getOperand(0).isUndef();
887 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
890 getDeadRegState(isDead) |
891 getUndefRegState(isUndef),
893 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
896 else if (Opc == ARM::VMOVD) {
897 unsigned Pred = MI->getOperand(2).getImm();
898 unsigned PredReg = MI->getOperand(3).getReg();
899 if (OpNum == 0) { // move -> store
900 unsigned SrcReg = MI->getOperand(1).getReg();
901 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
902 bool isKill = MI->getOperand(1).isKill();
903 bool isUndef = MI->getOperand(1).isUndef();
904 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
906 getKillRegState(isKill) | getUndefRegState(isUndef),
908 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
909 } else { // move -> load
910 unsigned DstReg = MI->getOperand(0).getReg();
911 unsigned DstSubReg = MI->getOperand(0).getSubReg();
912 bool isDead = MI->getOperand(0).isDead();
913 bool isUndef = MI->getOperand(0).isUndef();
914 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
917 getDeadRegState(isDead) |
918 getUndefRegState(isUndef),
920 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
928 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
930 const SmallVectorImpl<unsigned> &Ops,
931 MachineInstr* LoadMI) const {
937 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
938 const SmallVectorImpl<unsigned> &Ops) const {
939 if (Ops.size() != 1) return false;
941 unsigned Opc = MI->getOpcode();
942 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
943 // If it is updating CPSR, then it cannot be folded.
944 return MI->getOperand(4).getReg() != ARM::CPSR ||
945 MI->getOperand(4).isDead();
946 } else if (Opc == ARM::tMOVgpr2gpr ||
947 Opc == ARM::tMOVtgpr2gpr ||
948 Opc == ARM::tMOVgpr2tgpr) {
950 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
952 } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
953 return false; // FIXME
959 /// Create a copy of a const pool value. Update CPI to the new index and return
961 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
962 MachineConstantPool *MCP = MF.getConstantPool();
963 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
965 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
966 assert(MCPE.isMachineConstantPoolEntry() &&
967 "Expecting a machine constantpool entry!");
968 ARMConstantPoolValue *ACPV =
969 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
971 unsigned PCLabelId = AFI->createConstPoolEntryUId();
972 ARMConstantPoolValue *NewCPV = 0;
973 if (ACPV->isGlobalValue())
974 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
976 else if (ACPV->isExtSymbol())
977 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
978 ACPV->getSymbol(), PCLabelId, 4);
979 else if (ACPV->isBlockAddress())
980 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
981 ARMCP::CPBlockAddress, 4);
983 llvm_unreachable("Unexpected ARM constantpool value type!!");
984 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
988 void ARMBaseInstrInfo::
989 reMaterialize(MachineBasicBlock &MBB,
990 MachineBasicBlock::iterator I,
991 unsigned DestReg, unsigned SubIdx,
992 const MachineInstr *Orig,
993 const TargetRegisterInfo *TRI) const {
994 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
995 DestReg = TRI->getSubReg(DestReg, SubIdx);
999 unsigned Opcode = Orig->getOpcode();
1002 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1003 MI->getOperand(0).setReg(DestReg);
1007 case ARM::tLDRpci_pic:
1008 case ARM::t2LDRpci_pic: {
1009 MachineFunction &MF = *MBB.getParent();
1010 unsigned CPI = Orig->getOperand(1).getIndex();
1011 unsigned PCLabelId = duplicateCPV(MF, CPI);
1012 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1014 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1015 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1020 MachineInstr *NewMI = prior(I);
1021 NewMI->getOperand(0).setSubReg(SubIdx);
1025 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1026 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1027 switch(Orig->getOpcode()) {
1028 case ARM::tLDRpci_pic:
1029 case ARM::t2LDRpci_pic: {
1030 unsigned CPI = Orig->getOperand(1).getIndex();
1031 unsigned PCLabelId = duplicateCPV(MF, CPI);
1032 Orig->getOperand(1).setIndex(CPI);
1033 Orig->getOperand(2).setImm(PCLabelId);
1040 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1041 const MachineInstr *MI1) const {
1042 int Opcode = MI0->getOpcode();
1043 if (Opcode == ARM::t2LDRpci ||
1044 Opcode == ARM::t2LDRpci_pic ||
1045 Opcode == ARM::tLDRpci ||
1046 Opcode == ARM::tLDRpci_pic) {
1047 if (MI1->getOpcode() != Opcode)
1049 if (MI0->getNumOperands() != MI1->getNumOperands())
1052 const MachineOperand &MO0 = MI0->getOperand(1);
1053 const MachineOperand &MO1 = MI1->getOperand(1);
1054 if (MO0.getOffset() != MO1.getOffset())
1057 const MachineFunction *MF = MI0->getParent()->getParent();
1058 const MachineConstantPool *MCP = MF->getConstantPool();
1059 int CPI0 = MO0.getIndex();
1060 int CPI1 = MO1.getIndex();
1061 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1062 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1063 ARMConstantPoolValue *ACPV0 =
1064 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1065 ARMConstantPoolValue *ACPV1 =
1066 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1067 return ACPV0->hasSameValue(ACPV1);
1070 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1073 /// getInstrPredicate - If instruction is predicated, returns its predicate
1074 /// condition, otherwise returns AL. It also returns the condition code
1075 /// register by reference.
1077 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1078 int PIdx = MI->findFirstPredOperandIdx();
1084 PredReg = MI->getOperand(PIdx+1).getReg();
1085 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1089 int llvm::getMatchingCondBranchOpcode(int Opc) {
1092 else if (Opc == ARM::tB)
1094 else if (Opc == ARM::t2B)
1097 llvm_unreachable("Unknown unconditional branch opcode!");
1102 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1103 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1104 unsigned DestReg, unsigned BaseReg, int NumBytes,
1105 ARMCC::CondCodes Pred, unsigned PredReg,
1106 const ARMBaseInstrInfo &TII) {
1107 bool isSub = NumBytes < 0;
1108 if (isSub) NumBytes = -NumBytes;
1111 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1112 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1113 assert(ThisVal && "Didn't extract field correctly");
1115 // We will handle these bits from offset, clear them.
1116 NumBytes &= ~ThisVal;
1118 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1120 // Build the new ADD / SUB.
1121 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1122 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1123 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1124 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1129 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1130 unsigned FrameReg, int &Offset,
1131 const ARMBaseInstrInfo &TII) {
1132 unsigned Opcode = MI.getOpcode();
1133 const TargetInstrDesc &Desc = MI.getDesc();
1134 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1137 // Memory operands in inline assembly always use AddrMode2.
1138 if (Opcode == ARM::INLINEASM)
1139 AddrMode = ARMII::AddrMode2;
1141 if (Opcode == ARM::ADDri) {
1142 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1144 // Turn it into a move.
1145 MI.setDesc(TII.get(ARM::MOVr));
1146 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1147 MI.RemoveOperand(FrameRegIdx+1);
1150 } else if (Offset < 0) {
1153 MI.setDesc(TII.get(ARM::SUBri));
1156 // Common case: small offset, fits into instruction.
1157 if (ARM_AM::getSOImmVal(Offset) != -1) {
1158 // Replace the FrameIndex with sp / fp
1159 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1160 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1165 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1167 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1168 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1170 // We will handle these bits from offset, clear them.
1171 Offset &= ~ThisImmVal;
1173 // Get the properly encoded SOImmVal field.
1174 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1175 "Bit extraction didn't work?");
1176 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1178 unsigned ImmIdx = 0;
1180 unsigned NumBits = 0;
1183 case ARMII::AddrMode2: {
1184 ImmIdx = FrameRegIdx+2;
1185 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1186 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1191 case ARMII::AddrMode3: {
1192 ImmIdx = FrameRegIdx+2;
1193 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1194 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1199 case ARMII::AddrMode4:
1200 case ARMII::AddrMode6:
1201 // Can't fold any offset even if it's zero.
1203 case ARMII::AddrMode5: {
1204 ImmIdx = FrameRegIdx+1;
1205 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1206 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1213 llvm_unreachable("Unsupported addressing mode!");
1217 Offset += InstrOffs * Scale;
1218 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1224 // Attempt to fold address comp. if opcode has offset bits
1226 // Common case: small offset, fits into instruction.
1227 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1228 int ImmedOffset = Offset / Scale;
1229 unsigned Mask = (1 << NumBits) - 1;
1230 if ((unsigned)Offset <= Mask * Scale) {
1231 // Replace the FrameIndex with sp
1232 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1234 ImmedOffset |= 1 << NumBits;
1235 ImmOp.ChangeToImmediate(ImmedOffset);
1240 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1241 ImmedOffset = ImmedOffset & Mask;
1243 ImmedOffset |= 1 << NumBits;
1244 ImmOp.ChangeToImmediate(ImmedOffset);
1245 Offset &= ~(Mask*Scale);
1249 Offset = (isSub) ? -Offset : Offset;