1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/BranchProbability.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
40 #define GET_INSTRINFO_CTOR_DTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
53 static cl::opt<unsigned>
54 SwiftPartialUpdateClearance("swift-partial-update-clearance",
55 cl::Hidden, cl::init(12),
56 cl::desc("Clearance before partial register updates"));
58 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
60 uint16_t MLxOpc; // MLA / MLS opcode
61 uint16_t MulOpc; // Expanded multiplication opcode
62 uint16_t AddSubOpc; // Expanded add / sub opcode
63 bool NegAcc; // True if the acc is negated before the add / sub.
64 bool HasLane; // True if instruction has an extra "lane" operand.
67 static const ARM_MLxEntry ARM_MLxTable[] = {
68 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
70 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
71 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
72 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
73 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
74 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
75 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
76 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
77 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
80 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
81 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
82 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
83 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
84 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
85 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
86 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
87 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
90 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
91 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
93 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
94 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
95 assert(false && "Duplicated entries?");
96 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
97 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
101 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
102 // currently defaults to no prepass hazard recognizer.
103 ScheduleHazardRecognizer *ARMBaseInstrInfo::
104 CreateTargetHazardRecognizer(const TargetMachine *TM,
105 const ScheduleDAG *DAG) const {
106 if (usePreRAHazardRecognizer()) {
107 const InstrItineraryData *II = TM->getInstrItineraryData();
108 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
110 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
113 ScheduleHazardRecognizer *ARMBaseInstrInfo::
114 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
115 const ScheduleDAG *DAG) const {
116 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
117 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
118 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
122 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
123 MachineBasicBlock::iterator &MBBI,
124 LiveVariables *LV) const {
125 // FIXME: Thumb2 support.
130 MachineInstr *MI = MBBI;
131 MachineFunction &MF = *MI->getParent()->getParent();
132 uint64_t TSFlags = MI->getDesc().TSFlags;
134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
135 default: return NULL;
136 case ARMII::IndexModePre:
139 case ARMII::IndexModePost:
143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
149 MachineInstr *UpdateMI = NULL;
150 MachineInstr *MemMI = NULL;
151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
152 const MCInstrDesc &MCID = MI->getDesc();
153 unsigned NumOps = MCID.getNumOperands();
154 bool isLoad = !MI->mayStore();
155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
158 unsigned WBReg = WB.getReg();
159 unsigned BaseReg = Base.getReg();
160 unsigned OffReg = Offset.getReg();
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
164 default: llvm_unreachable("Unknown indexed op!");
165 case ARMII::AddrMode2: {
166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
167 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
169 if (ARM_AM::getSOImmVal(Amt) == -1)
170 // Can't encode it in a so_imm operand. This transformation will
171 // add more than 1 instruction. Abandon!
173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
175 .addReg(BaseReg).addImm(Amt)
176 .addImm(Pred).addReg(0).addReg(0);
177 } else if (Amt != 0) {
178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
183 .addImm(Pred).addReg(0).addReg(0);
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 .addReg(BaseReg).addReg(OffReg)
188 .addImm(Pred).addReg(0).addReg(0);
191 case ARMII::AddrMode3 : {
192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
193 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
198 .addReg(BaseReg).addImm(Amt)
199 .addImm(Pred).addReg(0).addReg(0);
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
203 .addReg(BaseReg).addReg(OffReg)
204 .addImm(Pred).addReg(0).addReg(0);
209 std::vector<MachineInstr*> NewMIs;
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(WBReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
219 NewMIs.push_back(MemMI);
220 NewMIs.push_back(UpdateMI);
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
224 get(MemOpc), MI->getOperand(0).getReg())
225 .addReg(BaseReg).addImm(0).addImm(Pred);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc)).addReg(MI->getOperand(1).getReg())
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
231 UpdateMI->getOperand(0).setIsDead();
232 NewMIs.push_back(UpdateMI);
233 NewMIs.push_back(MemMI);
236 // Transfer LiveVariables states, kill / dead info.
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
241 unsigned Reg = MO.getReg();
243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
247 LV->addVirtualRegisterDead(Reg, NewMI);
249 if (MO.isUse() && MO.isKill()) {
250 for (unsigned j = 0; j < 2; ++j) {
251 // Look at the two new MI's in reverse order.
252 MachineInstr *NewMI = NewMIs[j];
253 if (!NewMI->readsRegister(Reg))
255 LV->addVirtualRegisterKilled(Reg, NewMI);
256 if (VI.removeKill(MI))
257 VI.Kills.push_back(NewMI);
265 MFI->insert(MBBI, NewMIs[1]);
266 MFI->insert(MBBI, NewMIs[0]);
272 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
273 MachineBasicBlock *&FBB,
274 SmallVectorImpl<MachineOperand> &Cond,
275 bool AllowModify) const {
279 MachineBasicBlock::iterator I = MBB.end();
280 if (I == MBB.begin())
281 return false; // Empty blocks are easy.
284 // Walk backwards from the end of the basic block until the branch is
285 // analyzed or we give up.
286 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
288 // Flag to be raised on unanalyzeable instructions. This is useful in cases
289 // where we want to clean up on the end of the basic block before we bail
291 bool CantAnalyze = false;
293 // Skip over DEBUG values and predicated nonterminators.
294 while (I->isDebugValue() || !I->isTerminator()) {
295 if (I == MBB.begin())
300 if (isIndirectBranchOpcode(I->getOpcode()) ||
301 isJumpTableBranchOpcode(I->getOpcode())) {
302 // Indirect branches and jump tables can't be analyzed, but we still want
303 // to clean up any instructions at the tail of the basic block.
305 } else if (isUncondBranchOpcode(I->getOpcode())) {
306 TBB = I->getOperand(0).getMBB();
307 } else if (isCondBranchOpcode(I->getOpcode())) {
308 // Bail out if we encounter multiple conditional branches.
312 assert(!FBB && "FBB should have been null.");
314 TBB = I->getOperand(0).getMBB();
315 Cond.push_back(I->getOperand(1));
316 Cond.push_back(I->getOperand(2));
317 } else if (I->isReturn()) {
318 // Returns can't be analyzed, but we should run cleanup.
319 CantAnalyze = !isPredicated(I);
321 // We encountered other unrecognized terminator. Bail out immediately.
325 // Cleanup code - to be run for unpredicated unconditional branches and
327 if (!isPredicated(I) &&
328 (isUncondBranchOpcode(I->getOpcode()) ||
329 isIndirectBranchOpcode(I->getOpcode()) ||
330 isJumpTableBranchOpcode(I->getOpcode()) ||
332 // Forget any previous condition branch information - it no longer applies.
336 // If we can modify the function, delete everything below this
337 // unconditional branch.
339 MachineBasicBlock::iterator DI = std::next(I);
340 while (DI != MBB.end()) {
341 MachineInstr *InstToDelete = DI;
343 InstToDelete->eraseFromParent();
351 if (I == MBB.begin())
357 // We made it past the terminators without bailing out - we must have
358 // analyzed this branch successfully.
363 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
364 MachineBasicBlock::iterator I = MBB.end();
365 if (I == MBB.begin()) return 0;
367 while (I->isDebugValue()) {
368 if (I == MBB.begin())
372 if (!isUncondBranchOpcode(I->getOpcode()) &&
373 !isCondBranchOpcode(I->getOpcode()))
376 // Remove the branch.
377 I->eraseFromParent();
381 if (I == MBB.begin()) return 1;
383 if (!isCondBranchOpcode(I->getOpcode()))
386 // Remove the branch.
387 I->eraseFromParent();
392 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
393 MachineBasicBlock *FBB,
394 const SmallVectorImpl<MachineOperand> &Cond,
396 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
397 int BOpc = !AFI->isThumbFunction()
398 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
399 int BccOpc = !AFI->isThumbFunction()
400 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
401 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
403 // Shouldn't be a fall through.
404 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
405 assert((Cond.size() == 2 || Cond.size() == 0) &&
406 "ARM branch conditions have two components!");
409 if (Cond.empty()) { // Unconditional branch?
411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
413 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
415 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
420 // Two-way conditional branch.
421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
426 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
430 bool ARMBaseInstrInfo::
431 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
432 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
433 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
437 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
438 if (MI->isBundle()) {
439 MachineBasicBlock::const_instr_iterator I = MI;
440 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
441 while (++I != E && I->isInsideBundle()) {
442 int PIdx = I->findFirstPredOperandIdx();
443 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
449 int PIdx = MI->findFirstPredOperandIdx();
450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
453 bool ARMBaseInstrInfo::
454 PredicateInstruction(MachineInstr *MI,
455 const SmallVectorImpl<MachineOperand> &Pred) const {
456 unsigned Opc = MI->getOpcode();
457 if (isUncondBranchOpcode(Opc)) {
458 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
459 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
460 .addImm(Pred[0].getImm())
461 .addReg(Pred[1].getReg());
465 int PIdx = MI->findFirstPredOperandIdx();
467 MachineOperand &PMO = MI->getOperand(PIdx);
468 PMO.setImm(Pred[0].getImm());
469 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
475 bool ARMBaseInstrInfo::
476 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
477 const SmallVectorImpl<MachineOperand> &Pred2) const {
478 if (Pred1.size() > 2 || Pred2.size() > 2)
481 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
482 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
492 return CC2 == ARMCC::HI;
494 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
496 return CC2 == ARMCC::GT;
498 return CC2 == ARMCC::LT;
502 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
503 std::vector<MachineOperand> &Pred) const {
505 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
506 const MachineOperand &MO = MI->getOperand(i);
507 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
517 /// isPredicable - Return true if the specified instruction can be predicated.
518 /// By default, this returns true for every instruction with a
519 /// PredicateOperand.
520 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
521 if (!MI->isPredicable())
524 ARMFunctionInfo *AFI =
525 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
527 if (AFI->isThumb2Function()) {
528 if (getSubtarget().restrictIT())
529 return isV8EligibleForIT(MI);
530 } else { // non-Thumb
531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
538 template<> bool IsCPSRDead<MachineInstr>(MachineInstr* MI) {
539 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
540 const MachineOperand &MO = MI->getOperand(i);
541 if (!MO.isReg() || MO.isUndef() || MO.isUse())
543 if (MO.getReg() != ARM::CPSR)
548 // all definitions of CPSR are dead
552 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
553 LLVM_ATTRIBUTE_NOINLINE
554 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
556 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
558 assert(JTI < JT.size());
559 return JT[JTI].MBBs.size();
562 /// GetInstSize - Return the size of the specified MachineInstr.
564 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
565 const MachineBasicBlock &MBB = *MI->getParent();
566 const MachineFunction *MF = MBB.getParent();
567 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
569 const MCInstrDesc &MCID = MI->getDesc();
571 return MCID.getSize();
573 // If this machine instr is an inline asm, measure it.
574 if (MI->getOpcode() == ARM::INLINEASM)
575 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
578 unsigned Opc = MI->getOpcode();
580 case TargetOpcode::IMPLICIT_DEF:
581 case TargetOpcode::KILL:
582 case TargetOpcode::PROLOG_LABEL:
583 case TargetOpcode::EH_LABEL:
584 case TargetOpcode::DBG_VALUE:
586 case TargetOpcode::BUNDLE:
587 return getInstBundleLength(MI);
588 case ARM::MOVi16_ga_pcrel:
589 case ARM::MOVTi16_ga_pcrel:
590 case ARM::t2MOVi16_ga_pcrel:
591 case ARM::t2MOVTi16_ga_pcrel:
594 case ARM::t2MOVi32imm:
596 case ARM::CONSTPOOL_ENTRY:
597 // If this machine instr is a constant pool entry, its size is recorded as
599 return MI->getOperand(2).getImm();
600 case ARM::Int_eh_sjlj_longjmp:
602 case ARM::tInt_eh_sjlj_longjmp:
604 case ARM::Int_eh_sjlj_setjmp:
605 case ARM::Int_eh_sjlj_setjmp_nofp:
607 case ARM::tInt_eh_sjlj_setjmp:
608 case ARM::t2Int_eh_sjlj_setjmp:
609 case ARM::t2Int_eh_sjlj_setjmp_nofp:
617 case ARM::t2TBH_JT: {
618 // These are jumptable branches, i.e. a branch followed by an inlined
619 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
620 // entry is one byte; TBH two byte each.
621 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
622 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
623 unsigned NumOps = MCID.getNumOperands();
624 MachineOperand JTOP =
625 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
626 unsigned JTI = JTOP.getIndex();
627 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
629 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
630 assert(JTI < JT.size());
631 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
632 // 4 aligned. The assembler / linker may add 2 byte padding just before
633 // the JT entries. The size does not include this padding; the
634 // constant islands pass does separate bookkeeping for it.
635 // FIXME: If we know the size of the function is less than (1 << 16) *2
636 // bytes, we can use 16-bit entries instead. Then there won't be an
638 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
639 unsigned NumEntries = getNumJTEntries(JT, JTI);
640 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
641 // Make sure the instruction that follows TBB is 2-byte aligned.
642 // FIXME: Constant island pass should insert an "ALIGN" instruction
645 return NumEntries * EntrySize + InstSize;
648 // Otherwise, pseudo-instruction sizes are zero.
653 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
655 MachineBasicBlock::const_instr_iterator I = MI;
656 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
657 while (++I != E && I->isInsideBundle()) {
658 assert(!I->isBundle() && "No nested bundle!");
659 Size += GetInstSizeInBytes(&*I);
664 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
665 MachineBasicBlock::iterator I, DebugLoc DL,
666 unsigned DestReg, unsigned SrcReg,
667 bool KillSrc) const {
668 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
669 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
671 if (GPRDest && GPRSrc) {
672 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
673 .addReg(SrcReg, getKillRegState(KillSrc))));
677 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
678 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
681 if (SPRDest && SPRSrc)
683 else if (GPRDest && SPRSrc)
685 else if (SPRDest && GPRSrc)
687 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
689 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
693 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
694 MIB.addReg(SrcReg, getKillRegState(KillSrc));
695 if (Opc == ARM::VORRq)
696 MIB.addReg(SrcReg, getKillRegState(KillSrc));
701 // Handle register classes that require multiple instructions.
702 unsigned BeginIdx = 0;
703 unsigned SubRegs = 0;
706 // Use VORRq when possible.
707 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
709 BeginIdx = ARM::qsub_0;
711 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
713 BeginIdx = ARM::qsub_0;
715 // Fall back to VMOVD.
716 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
718 BeginIdx = ARM::dsub_0;
720 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
722 BeginIdx = ARM::dsub_0;
724 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
726 BeginIdx = ARM::dsub_0;
728 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
729 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
730 BeginIdx = ARM::gsub_0;
732 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
734 BeginIdx = ARM::dsub_0;
737 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
739 BeginIdx = ARM::dsub_0;
742 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
744 BeginIdx = ARM::dsub_0;
749 assert(Opc && "Impossible reg-to-reg copy");
751 const TargetRegisterInfo *TRI = &getRegisterInfo();
752 MachineInstrBuilder Mov;
754 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
755 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
756 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
760 SmallSet<unsigned, 4> DstRegs;
762 for (unsigned i = 0; i != SubRegs; ++i) {
763 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
764 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
765 assert(Dst && Src && "Bad sub-register");
767 assert(!DstRegs.count(Src) && "destructive vector copy");
770 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
771 // VORR takes two source operands.
772 if (Opc == ARM::VORRq)
774 Mov = AddDefaultPred(Mov);
776 if (Opc == ARM::MOVr)
777 Mov = AddDefaultCC(Mov);
779 // Add implicit super-register defs and kills to the last instruction.
780 Mov->addRegisterDefined(DestReg, TRI);
782 Mov->addRegisterKilled(SrcReg, TRI);
785 const MachineInstrBuilder &
786 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
787 unsigned SubIdx, unsigned State,
788 const TargetRegisterInfo *TRI) const {
790 return MIB.addReg(Reg, State);
792 if (TargetRegisterInfo::isPhysicalRegister(Reg))
793 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
794 return MIB.addReg(Reg, State, SubIdx);
797 void ARMBaseInstrInfo::
798 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
799 unsigned SrcReg, bool isKill, int FI,
800 const TargetRegisterClass *RC,
801 const TargetRegisterInfo *TRI) const {
803 if (I != MBB.end()) DL = I->getDebugLoc();
804 MachineFunction &MF = *MBB.getParent();
805 MachineFrameInfo &MFI = *MF.getFrameInfo();
806 unsigned Align = MFI.getObjectAlignment(FI);
808 MachineMemOperand *MMO =
809 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
810 MachineMemOperand::MOStore,
811 MFI.getObjectSize(FI),
814 switch (RC->getSize()) {
816 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
817 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
818 .addReg(SrcReg, getKillRegState(isKill))
819 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
820 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
821 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
822 .addReg(SrcReg, getKillRegState(isKill))
823 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
825 llvm_unreachable("Unknown reg class!");
828 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
830 .addReg(SrcReg, getKillRegState(isKill))
831 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
832 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
833 if (Subtarget.hasV5TEOps()) {
834 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
835 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
836 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
837 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
841 // Fallback to STM instruction, which has existed since the dawn of
843 MachineInstrBuilder MIB =
844 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
845 .addFrameIndex(FI).addMemOperand(MMO));
846 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
847 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
850 llvm_unreachable("Unknown reg class!");
853 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
854 // Use aligned spills if the stack can be realigned.
855 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
856 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
857 .addFrameIndex(FI).addImm(16)
858 .addReg(SrcReg, getKillRegState(isKill))
859 .addMemOperand(MMO));
861 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
862 .addReg(SrcReg, getKillRegState(isKill))
864 .addMemOperand(MMO));
867 llvm_unreachable("Unknown reg class!");
870 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
871 // Use aligned spills if the stack can be realigned.
872 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
873 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
874 .addFrameIndex(FI).addImm(16)
875 .addReg(SrcReg, getKillRegState(isKill))
876 .addMemOperand(MMO));
878 MachineInstrBuilder MIB =
879 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
882 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
883 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
884 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
887 llvm_unreachable("Unknown reg class!");
890 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
891 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
892 // FIXME: It's possible to only store part of the QQ register if the
893 // spilled def has a sub-register index.
894 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
895 .addFrameIndex(FI).addImm(16)
896 .addReg(SrcReg, getKillRegState(isKill))
897 .addMemOperand(MMO));
899 MachineInstrBuilder MIB =
900 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
903 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
904 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
905 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
906 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
909 llvm_unreachable("Unknown reg class!");
912 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
913 MachineInstrBuilder MIB =
914 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
917 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
918 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
919 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
920 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
921 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
922 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
923 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
924 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
926 llvm_unreachable("Unknown reg class!");
929 llvm_unreachable("Unknown reg class!");
934 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
935 int &FrameIndex) const {
936 switch (MI->getOpcode()) {
939 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
940 if (MI->getOperand(1).isFI() &&
941 MI->getOperand(2).isReg() &&
942 MI->getOperand(3).isImm() &&
943 MI->getOperand(2).getReg() == 0 &&
944 MI->getOperand(3).getImm() == 0) {
945 FrameIndex = MI->getOperand(1).getIndex();
946 return MI->getOperand(0).getReg();
954 if (MI->getOperand(1).isFI() &&
955 MI->getOperand(2).isImm() &&
956 MI->getOperand(2).getImm() == 0) {
957 FrameIndex = MI->getOperand(1).getIndex();
958 return MI->getOperand(0).getReg();
962 case ARM::VST1d64TPseudo:
963 case ARM::VST1d64QPseudo:
964 if (MI->getOperand(0).isFI() &&
965 MI->getOperand(2).getSubReg() == 0) {
966 FrameIndex = MI->getOperand(0).getIndex();
967 return MI->getOperand(2).getReg();
971 if (MI->getOperand(1).isFI() &&
972 MI->getOperand(0).getSubReg() == 0) {
973 FrameIndex = MI->getOperand(1).getIndex();
974 return MI->getOperand(0).getReg();
982 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
983 int &FrameIndex) const {
984 const MachineMemOperand *Dummy;
985 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
988 void ARMBaseInstrInfo::
989 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
990 unsigned DestReg, int FI,
991 const TargetRegisterClass *RC,
992 const TargetRegisterInfo *TRI) const {
994 if (I != MBB.end()) DL = I->getDebugLoc();
995 MachineFunction &MF = *MBB.getParent();
996 MachineFrameInfo &MFI = *MF.getFrameInfo();
997 unsigned Align = MFI.getObjectAlignment(FI);
998 MachineMemOperand *MMO =
999 MF.getMachineMemOperand(
1000 MachinePointerInfo::getFixedStack(FI),
1001 MachineMemOperand::MOLoad,
1002 MFI.getObjectSize(FI),
1005 switch (RC->getSize()) {
1007 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1008 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1009 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1011 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1012 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1013 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1015 llvm_unreachable("Unknown reg class!");
1018 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1019 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1020 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1021 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1022 MachineInstrBuilder MIB;
1024 if (Subtarget.hasV5TEOps()) {
1025 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1026 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1027 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1028 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1030 AddDefaultPred(MIB);
1032 // Fallback to LDM instruction, which has existed since the dawn of
1034 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1035 .addFrameIndex(FI).addMemOperand(MMO));
1036 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1037 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1040 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1041 MIB.addReg(DestReg, RegState::ImplicitDefine);
1043 llvm_unreachable("Unknown reg class!");
1046 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1047 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1048 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1049 .addFrameIndex(FI).addImm(16)
1050 .addMemOperand(MMO));
1052 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1054 .addMemOperand(MMO));
1057 llvm_unreachable("Unknown reg class!");
1060 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1061 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1063 .addFrameIndex(FI).addImm(16)
1064 .addMemOperand(MMO));
1066 MachineInstrBuilder MIB =
1067 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1069 .addMemOperand(MMO));
1070 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1071 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1072 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1073 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1074 MIB.addReg(DestReg, RegState::ImplicitDefine);
1077 llvm_unreachable("Unknown reg class!");
1080 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1081 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1082 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1083 .addFrameIndex(FI).addImm(16)
1084 .addMemOperand(MMO));
1086 MachineInstrBuilder MIB =
1087 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1089 .addMemOperand(MMO);
1090 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1091 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1092 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1093 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1094 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1095 MIB.addReg(DestReg, RegState::ImplicitDefine);
1098 llvm_unreachable("Unknown reg class!");
1101 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1102 MachineInstrBuilder MIB =
1103 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1105 .addMemOperand(MMO);
1106 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1107 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1108 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1109 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1110 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1111 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1112 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1113 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1114 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1115 MIB.addReg(DestReg, RegState::ImplicitDefine);
1117 llvm_unreachable("Unknown reg class!");
1120 llvm_unreachable("Unknown regclass!");
1125 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1126 int &FrameIndex) const {
1127 switch (MI->getOpcode()) {
1130 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1131 if (MI->getOperand(1).isFI() &&
1132 MI->getOperand(2).isReg() &&
1133 MI->getOperand(3).isImm() &&
1134 MI->getOperand(2).getReg() == 0 &&
1135 MI->getOperand(3).getImm() == 0) {
1136 FrameIndex = MI->getOperand(1).getIndex();
1137 return MI->getOperand(0).getReg();
1145 if (MI->getOperand(1).isFI() &&
1146 MI->getOperand(2).isImm() &&
1147 MI->getOperand(2).getImm() == 0) {
1148 FrameIndex = MI->getOperand(1).getIndex();
1149 return MI->getOperand(0).getReg();
1153 case ARM::VLD1d64TPseudo:
1154 case ARM::VLD1d64QPseudo:
1155 if (MI->getOperand(1).isFI() &&
1156 MI->getOperand(0).getSubReg() == 0) {
1157 FrameIndex = MI->getOperand(1).getIndex();
1158 return MI->getOperand(0).getReg();
1162 if (MI->getOperand(1).isFI() &&
1163 MI->getOperand(0).getSubReg() == 0) {
1164 FrameIndex = MI->getOperand(1).getIndex();
1165 return MI->getOperand(0).getReg();
1173 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1174 int &FrameIndex) const {
1175 const MachineMemOperand *Dummy;
1176 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1179 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1180 // This hook gets to expand COPY instructions before they become
1181 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1182 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1183 // changed into a VORR that can go down the NEON pipeline.
1184 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1187 // Look for a copy between even S-registers. That is where we keep floats
1188 // when using NEON v2f32 instructions for f32 arithmetic.
1189 unsigned DstRegS = MI->getOperand(0).getReg();
1190 unsigned SrcRegS = MI->getOperand(1).getReg();
1191 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1194 const TargetRegisterInfo *TRI = &getRegisterInfo();
1195 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1197 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1199 if (!DstRegD || !SrcRegD)
1202 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1203 // legal if the COPY already defines the full DstRegD, and it isn't a
1204 // sub-register insertion.
1205 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1208 // A dead copy shouldn't show up here, but reject it just in case.
1209 if (MI->getOperand(0).isDead())
1212 // All clear, widen the COPY.
1213 DEBUG(dbgs() << "widening: " << *MI);
1214 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1216 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1217 // or some other super-register.
1218 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1219 if (ImpDefIdx != -1)
1220 MI->RemoveOperand(ImpDefIdx);
1222 // Change the opcode and operands.
1223 MI->setDesc(get(ARM::VMOVD));
1224 MI->getOperand(0).setReg(DstRegD);
1225 MI->getOperand(1).setReg(SrcRegD);
1226 AddDefaultPred(MIB);
1228 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1229 // register scavenger and machine verifier, so we need to indicate that we
1230 // are reading an undefined value from SrcRegD, but a proper value from
1232 MI->getOperand(1).setIsUndef();
1233 MIB.addReg(SrcRegS, RegState::Implicit);
1235 // SrcRegD may actually contain an unrelated value in the ssub_1
1236 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1237 if (MI->getOperand(1).isKill()) {
1238 MI->getOperand(1).setIsKill(false);
1239 MI->addRegisterKilled(SrcRegS, TRI, true);
1242 DEBUG(dbgs() << "replaced by: " << *MI);
1246 /// Create a copy of a const pool value. Update CPI to the new index and return
1248 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1249 MachineConstantPool *MCP = MF.getConstantPool();
1250 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1252 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1253 assert(MCPE.isMachineConstantPoolEntry() &&
1254 "Expecting a machine constantpool entry!");
1255 ARMConstantPoolValue *ACPV =
1256 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1258 unsigned PCLabelId = AFI->createPICLabelUId();
1259 ARMConstantPoolValue *NewCPV = 0;
1261 // FIXME: The below assumes PIC relocation model and that the function
1262 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1263 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1264 // instructions, so that's probably OK, but is PIC always correct when
1266 if (ACPV->isGlobalValue())
1267 NewCPV = ARMConstantPoolConstant::
1268 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1270 else if (ACPV->isExtSymbol())
1271 NewCPV = ARMConstantPoolSymbol::
1272 Create(MF.getFunction()->getContext(),
1273 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1274 else if (ACPV->isBlockAddress())
1275 NewCPV = ARMConstantPoolConstant::
1276 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1277 ARMCP::CPBlockAddress, 4);
1278 else if (ACPV->isLSDA())
1279 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1281 else if (ACPV->isMachineBasicBlock())
1282 NewCPV = ARMConstantPoolMBB::
1283 Create(MF.getFunction()->getContext(),
1284 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1286 llvm_unreachable("Unexpected ARM constantpool value type!!");
1287 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1291 void ARMBaseInstrInfo::
1292 reMaterialize(MachineBasicBlock &MBB,
1293 MachineBasicBlock::iterator I,
1294 unsigned DestReg, unsigned SubIdx,
1295 const MachineInstr *Orig,
1296 const TargetRegisterInfo &TRI) const {
1297 unsigned Opcode = Orig->getOpcode();
1300 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1301 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1305 case ARM::tLDRpci_pic:
1306 case ARM::t2LDRpci_pic: {
1307 MachineFunction &MF = *MBB.getParent();
1308 unsigned CPI = Orig->getOperand(1).getIndex();
1309 unsigned PCLabelId = duplicateCPV(MF, CPI);
1310 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1312 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1313 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1320 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1321 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1322 switch(Orig->getOpcode()) {
1323 case ARM::tLDRpci_pic:
1324 case ARM::t2LDRpci_pic: {
1325 unsigned CPI = Orig->getOperand(1).getIndex();
1326 unsigned PCLabelId = duplicateCPV(MF, CPI);
1327 Orig->getOperand(1).setIndex(CPI);
1328 Orig->getOperand(2).setImm(PCLabelId);
1335 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1336 const MachineInstr *MI1,
1337 const MachineRegisterInfo *MRI) const {
1338 int Opcode = MI0->getOpcode();
1339 if (Opcode == ARM::t2LDRpci ||
1340 Opcode == ARM::t2LDRpci_pic ||
1341 Opcode == ARM::tLDRpci ||
1342 Opcode == ARM::tLDRpci_pic ||
1343 Opcode == ARM::LDRLIT_ga_pcrel ||
1344 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1345 Opcode == ARM::tLDRLIT_ga_pcrel ||
1346 Opcode == ARM::MOV_ga_pcrel ||
1347 Opcode == ARM::MOV_ga_pcrel_ldr ||
1348 Opcode == ARM::t2MOV_ga_pcrel) {
1349 if (MI1->getOpcode() != Opcode)
1351 if (MI0->getNumOperands() != MI1->getNumOperands())
1354 const MachineOperand &MO0 = MI0->getOperand(1);
1355 const MachineOperand &MO1 = MI1->getOperand(1);
1356 if (MO0.getOffset() != MO1.getOffset())
1359 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1360 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1361 Opcode == ARM::tLDRLIT_ga_pcrel ||
1362 Opcode == ARM::MOV_ga_pcrel ||
1363 Opcode == ARM::MOV_ga_pcrel_ldr ||
1364 Opcode == ARM::t2MOV_ga_pcrel)
1365 // Ignore the PC labels.
1366 return MO0.getGlobal() == MO1.getGlobal();
1368 const MachineFunction *MF = MI0->getParent()->getParent();
1369 const MachineConstantPool *MCP = MF->getConstantPool();
1370 int CPI0 = MO0.getIndex();
1371 int CPI1 = MO1.getIndex();
1372 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1373 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1374 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1375 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1376 if (isARMCP0 && isARMCP1) {
1377 ARMConstantPoolValue *ACPV0 =
1378 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1379 ARMConstantPoolValue *ACPV1 =
1380 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1381 return ACPV0->hasSameValue(ACPV1);
1382 } else if (!isARMCP0 && !isARMCP1) {
1383 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1386 } else if (Opcode == ARM::PICLDR) {
1387 if (MI1->getOpcode() != Opcode)
1389 if (MI0->getNumOperands() != MI1->getNumOperands())
1392 unsigned Addr0 = MI0->getOperand(1).getReg();
1393 unsigned Addr1 = MI1->getOperand(1).getReg();
1394 if (Addr0 != Addr1) {
1396 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1397 !TargetRegisterInfo::isVirtualRegister(Addr1))
1400 // This assumes SSA form.
1401 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1402 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1403 // Check if the loaded value, e.g. a constantpool of a global address, are
1405 if (!produceSameValue(Def0, Def1, MRI))
1409 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1410 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1411 const MachineOperand &MO0 = MI0->getOperand(i);
1412 const MachineOperand &MO1 = MI1->getOperand(i);
1413 if (!MO0.isIdenticalTo(MO1))
1419 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1422 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1423 /// determine if two loads are loading from the same base address. It should
1424 /// only return true if the base pointers are the same and the only differences
1425 /// between the two addresses is the offset. It also returns the offsets by
1428 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1429 /// is permanently disabled.
1430 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1432 int64_t &Offset2) const {
1433 // Don't worry about Thumb: just ARM and Thumb2.
1434 if (Subtarget.isThumb1Only()) return false;
1436 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1439 switch (Load1->getMachineOpcode()) {
1453 case ARM::t2LDRSHi8:
1455 case ARM::t2LDRBi12:
1456 case ARM::t2LDRSHi12:
1460 switch (Load2->getMachineOpcode()) {
1473 case ARM::t2LDRSHi8:
1475 case ARM::t2LDRBi12:
1476 case ARM::t2LDRSHi12:
1480 // Check if base addresses and chain operands match.
1481 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1482 Load1->getOperand(4) != Load2->getOperand(4))
1485 // Index should be Reg0.
1486 if (Load1->getOperand(3) != Load2->getOperand(3))
1489 // Determine the offsets.
1490 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1491 isa<ConstantSDNode>(Load2->getOperand(1))) {
1492 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1493 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1500 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1501 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1502 /// be scheduled togther. On some targets if two loads are loading from
1503 /// addresses in the same cache line, it's better if they are scheduled
1504 /// together. This function takes two integers that represent the load offsets
1505 /// from the common base address. It returns true if it decides it's desirable
1506 /// to schedule the two loads together. "NumLoads" is the number of loads that
1507 /// have already been scheduled after Load1.
1509 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1510 /// is permanently disabled.
1511 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1512 int64_t Offset1, int64_t Offset2,
1513 unsigned NumLoads) const {
1514 // Don't worry about Thumb: just ARM and Thumb2.
1515 if (Subtarget.isThumb1Only()) return false;
1517 assert(Offset2 > Offset1);
1519 if ((Offset2 - Offset1) / 8 > 64)
1522 // Check if the machine opcodes are different. If they are different
1523 // then we consider them to not be of the same base address,
1524 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1525 // In this case, they are considered to be the same because they are different
1526 // encoding forms of the same basic instruction.
1527 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1528 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1529 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1530 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1531 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1532 return false; // FIXME: overly conservative?
1534 // Four loads in a row should be sufficient.
1541 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1542 const MachineBasicBlock *MBB,
1543 const MachineFunction &MF) const {
1544 // Debug info is never a scheduling boundary. It's necessary to be explicit
1545 // due to the special treatment of IT instructions below, otherwise a
1546 // dbg_value followed by an IT will result in the IT instruction being
1547 // considered a scheduling hazard, which is wrong. It should be the actual
1548 // instruction preceding the dbg_value instruction(s), just like it is
1549 // when debug info is not present.
1550 if (MI->isDebugValue())
1553 // Terminators and labels can't be scheduled around.
1554 if (MI->isTerminator() || MI->isLabel())
1557 // Treat the start of the IT block as a scheduling boundary, but schedule
1558 // t2IT along with all instructions following it.
1559 // FIXME: This is a big hammer. But the alternative is to add all potential
1560 // true and anti dependencies to IT block instructions as implicit operands
1561 // to the t2IT instruction. The added compile time and complexity does not
1563 MachineBasicBlock::const_iterator I = MI;
1564 // Make sure to skip any dbg_value instructions
1565 while (++I != MBB->end() && I->isDebugValue())
1567 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1570 // Don't attempt to schedule around any instruction that defines
1571 // a stack-oriented pointer, as it's unlikely to be profitable. This
1572 // saves compile time, because it doesn't require every single
1573 // stack slot reference to depend on the instruction that does the
1575 // Calls don't actually change the stack pointer, even if they have imp-defs.
1576 // No ARM calling conventions change the stack pointer. (X86 calling
1577 // conventions sometimes do).
1578 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1584 bool ARMBaseInstrInfo::
1585 isProfitableToIfCvt(MachineBasicBlock &MBB,
1586 unsigned NumCycles, unsigned ExtraPredCycles,
1587 const BranchProbability &Probability) const {
1591 // Attempt to estimate the relative costs of predication versus branching.
1592 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1593 UnpredCost /= Probability.getDenominator();
1594 UnpredCost += 1; // The branch itself
1595 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1597 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1600 bool ARMBaseInstrInfo::
1601 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1602 unsigned TCycles, unsigned TExtra,
1603 MachineBasicBlock &FMBB,
1604 unsigned FCycles, unsigned FExtra,
1605 const BranchProbability &Probability) const {
1606 if (!TCycles || !FCycles)
1609 // Attempt to estimate the relative costs of predication versus branching.
1610 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1611 TUnpredCost /= Probability.getDenominator();
1613 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1614 unsigned FUnpredCost = Comp * FCycles;
1615 FUnpredCost /= Probability.getDenominator();
1617 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1618 UnpredCost += 1; // The branch itself
1619 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1621 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1625 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1626 MachineBasicBlock &FMBB) const {
1627 // Reduce false anti-dependencies to let Swift's out-of-order execution
1628 // engine do its thing.
1629 return Subtarget.isSwift();
1632 /// getInstrPredicate - If instruction is predicated, returns its predicate
1633 /// condition, otherwise returns AL. It also returns the condition code
1634 /// register by reference.
1636 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1637 int PIdx = MI->findFirstPredOperandIdx();
1643 PredReg = MI->getOperand(PIdx+1).getReg();
1644 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1648 int llvm::getMatchingCondBranchOpcode(int Opc) {
1653 if (Opc == ARM::t2B)
1656 llvm_unreachable("Unknown unconditional branch opcode!");
1659 /// commuteInstruction - Handle commutable instructions.
1661 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1662 switch (MI->getOpcode()) {
1664 case ARM::t2MOVCCr: {
1665 // MOVCC can be commuted by inverting the condition.
1666 unsigned PredReg = 0;
1667 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1668 // MOVCC AL can't be inverted. Shouldn't happen.
1669 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1671 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1674 // After swapping the MOVCC operands, also invert the condition.
1675 MI->getOperand(MI->findFirstPredOperandIdx())
1676 .setImm(ARMCC::getOppositeCondition(CC));
1680 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1683 /// Identify instructions that can be folded into a MOVCC instruction, and
1684 /// return the defining instruction.
1685 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1686 const MachineRegisterInfo &MRI,
1687 const TargetInstrInfo *TII) {
1688 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1690 if (!MRI.hasOneNonDBGUse(Reg))
1692 MachineInstr *MI = MRI.getVRegDef(Reg);
1695 // MI is folded into the MOVCC by predicating it.
1696 if (!MI->isPredicable())
1698 // Check if MI has any non-dead defs or physreg uses. This also detects
1699 // predicated instructions which will be reading CPSR.
1700 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1701 const MachineOperand &MO = MI->getOperand(i);
1702 // Reject frame index operands, PEI can't handle the predicated pseudos.
1703 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1707 // MI can't have any tied operands, that would conflict with predication.
1710 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1712 if (MO.isDef() && !MO.isDead())
1715 bool DontMoveAcrossStores = true;
1716 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1721 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1722 SmallVectorImpl<MachineOperand> &Cond,
1723 unsigned &TrueOp, unsigned &FalseOp,
1724 bool &Optimizable) const {
1725 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1726 "Unknown select instruction");
1731 // 3: Condition code.
1735 Cond.push_back(MI->getOperand(3));
1736 Cond.push_back(MI->getOperand(4));
1737 // We can always fold a def.
1742 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1743 bool PreferFalse) const {
1744 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1745 "Unknown select instruction");
1746 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1747 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1748 bool Invert = !DefMI;
1750 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1754 // Find new register class to use.
1755 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1756 unsigned DestReg = MI->getOperand(0).getReg();
1757 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1758 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1761 // Create a new predicated version of DefMI.
1762 // Rfalse is the first use.
1763 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1764 DefMI->getDesc(), DestReg);
1766 // Copy all the DefMI operands, excluding its (null) predicate.
1767 const MCInstrDesc &DefDesc = DefMI->getDesc();
1768 for (unsigned i = 1, e = DefDesc.getNumOperands();
1769 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1770 NewMI.addOperand(DefMI->getOperand(i));
1772 unsigned CondCode = MI->getOperand(3).getImm();
1774 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1776 NewMI.addImm(CondCode);
1777 NewMI.addOperand(MI->getOperand(4));
1779 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1780 if (NewMI->hasOptionalDef())
1781 AddDefaultCC(NewMI);
1783 // The output register value when the predicate is false is an implicit
1784 // register operand tied to the first def.
1785 // The tie makes the register allocator ensure the FalseReg is allocated the
1786 // same register as operand 0.
1787 FalseReg.setImplicit();
1788 NewMI.addOperand(FalseReg);
1789 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1791 // The caller will erase MI, but not DefMI.
1792 DefMI->eraseFromParent();
1796 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1797 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1800 /// This will go away once we can teach tblgen how to set the optional CPSR def
1802 struct AddSubFlagsOpcodePair {
1804 uint16_t MachineOpc;
1807 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1808 {ARM::ADDSri, ARM::ADDri},
1809 {ARM::ADDSrr, ARM::ADDrr},
1810 {ARM::ADDSrsi, ARM::ADDrsi},
1811 {ARM::ADDSrsr, ARM::ADDrsr},
1813 {ARM::SUBSri, ARM::SUBri},
1814 {ARM::SUBSrr, ARM::SUBrr},
1815 {ARM::SUBSrsi, ARM::SUBrsi},
1816 {ARM::SUBSrsr, ARM::SUBrsr},
1818 {ARM::RSBSri, ARM::RSBri},
1819 {ARM::RSBSrsi, ARM::RSBrsi},
1820 {ARM::RSBSrsr, ARM::RSBrsr},
1822 {ARM::t2ADDSri, ARM::t2ADDri},
1823 {ARM::t2ADDSrr, ARM::t2ADDrr},
1824 {ARM::t2ADDSrs, ARM::t2ADDrs},
1826 {ARM::t2SUBSri, ARM::t2SUBri},
1827 {ARM::t2SUBSrr, ARM::t2SUBrr},
1828 {ARM::t2SUBSrs, ARM::t2SUBrs},
1830 {ARM::t2RSBSri, ARM::t2RSBri},
1831 {ARM::t2RSBSrs, ARM::t2RSBrs},
1834 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1835 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1836 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1837 return AddSubFlagsOpcodeMap[i].MachineOpc;
1841 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1842 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1843 unsigned DestReg, unsigned BaseReg, int NumBytes,
1844 ARMCC::CondCodes Pred, unsigned PredReg,
1845 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1846 if (NumBytes == 0 && DestReg != BaseReg) {
1847 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1848 .addReg(BaseReg, RegState::Kill)
1849 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1850 .setMIFlags(MIFlags);
1854 bool isSub = NumBytes < 0;
1855 if (isSub) NumBytes = -NumBytes;
1858 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1859 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1860 assert(ThisVal && "Didn't extract field correctly");
1862 // We will handle these bits from offset, clear them.
1863 NumBytes &= ~ThisVal;
1865 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1867 // Build the new ADD / SUB.
1868 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1869 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1870 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1871 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1872 .setMIFlags(MIFlags);
1877 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1878 MachineFunction &MF, MachineInstr *MI,
1879 unsigned NumBytes) {
1880 // This optimisation potentially adds lots of load and store
1881 // micro-operations, it's only really a great benefit to code-size.
1882 if (!Subtarget.isMinSize())
1885 // If only one register is pushed/popped, LLVM can use an LDR/STR
1886 // instead. We can't modify those so make sure we're dealing with an
1887 // instruction we understand.
1888 bool IsPop = isPopOpcode(MI->getOpcode());
1889 bool IsPush = isPushOpcode(MI->getOpcode());
1890 if (!IsPush && !IsPop)
1893 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1894 MI->getOpcode() == ARM::VLDMDIA_UPD;
1895 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
1896 MI->getOpcode() == ARM::tPOP ||
1897 MI->getOpcode() == ARM::tPOP_RET;
1899 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
1900 MI->getOperand(1).getReg() == ARM::SP)) &&
1901 "trying to fold sp update into non-sp-updating push/pop");
1903 // The VFP push & pop act on D-registers, so we can only fold an adjustment
1904 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
1905 // if this is violated.
1906 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
1909 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
1910 // pred) so the list starts at 4. Thumb1 starts after the predicate.
1911 int RegListIdx = IsT1PushPop ? 2 : 4;
1913 // Calculate the space we'll need in terms of registers.
1914 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
1915 unsigned RD0Reg, RegsNeeded;
1918 RegsNeeded = NumBytes / 8;
1921 RegsNeeded = NumBytes / 4;
1924 // We're going to have to strip all list operands off before
1925 // re-adding them since the order matters, so save the existing ones
1927 SmallVector<MachineOperand, 4> RegList;
1928 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1929 RegList.push_back(MI->getOperand(i));
1931 MachineBasicBlock *MBB = MI->getParent();
1932 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
1933 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
1935 // Now try to find enough space in the reglist to allocate NumBytes.
1936 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
1939 // Pushing any register is completely harmless, mark the
1940 // register involved as undef since we don't care about it in
1942 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
1943 false, false, true));
1948 // However, we can only pop an extra register if it's not live. For
1949 // registers live within the function we might clobber a return value
1950 // register; the other way a register can be live here is if it's
1952 if (isCalleeSavedRegister(CurReg, CSRegs) ||
1953 MBB->computeRegisterLiveness(TRI, CurReg, MI) !=
1954 MachineBasicBlock::LQR_Dead) {
1955 // VFP pops don't allow holes in the register list, so any skip is fatal
1956 // for our transformation. GPR pops do, so we should just keep looking.
1963 // Mark the unimportant registers as <def,dead> in the POP.
1964 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
1972 // Finally we know we can profitably perform the optimisation so go
1973 // ahead: strip all existing registers off and add them back again
1974 // in the right order.
1975 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1976 MI->RemoveOperand(i);
1978 // Add the complete list back in.
1979 MachineInstrBuilder MIB(MF, &*MI);
1980 for (int i = RegList.size() - 1; i >= 0; --i)
1981 MIB.addOperand(RegList[i]);
1986 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1987 unsigned FrameReg, int &Offset,
1988 const ARMBaseInstrInfo &TII) {
1989 unsigned Opcode = MI.getOpcode();
1990 const MCInstrDesc &Desc = MI.getDesc();
1991 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1994 // Memory operands in inline assembly always use AddrMode2.
1995 if (Opcode == ARM::INLINEASM)
1996 AddrMode = ARMII::AddrMode2;
1998 if (Opcode == ARM::ADDri) {
1999 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2001 // Turn it into a move.
2002 MI.setDesc(TII.get(ARM::MOVr));
2003 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2004 MI.RemoveOperand(FrameRegIdx+1);
2007 } else if (Offset < 0) {
2010 MI.setDesc(TII.get(ARM::SUBri));
2013 // Common case: small offset, fits into instruction.
2014 if (ARM_AM::getSOImmVal(Offset) != -1) {
2015 // Replace the FrameIndex with sp / fp
2016 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2017 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2022 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2024 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2025 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2027 // We will handle these bits from offset, clear them.
2028 Offset &= ~ThisImmVal;
2030 // Get the properly encoded SOImmVal field.
2031 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2032 "Bit extraction didn't work?");
2033 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2035 unsigned ImmIdx = 0;
2037 unsigned NumBits = 0;
2040 case ARMII::AddrMode_i12: {
2041 ImmIdx = FrameRegIdx + 1;
2042 InstrOffs = MI.getOperand(ImmIdx).getImm();
2046 case ARMII::AddrMode2: {
2047 ImmIdx = FrameRegIdx+2;
2048 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2049 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2054 case ARMII::AddrMode3: {
2055 ImmIdx = FrameRegIdx+2;
2056 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2057 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2062 case ARMII::AddrMode4:
2063 case ARMII::AddrMode6:
2064 // Can't fold any offset even if it's zero.
2066 case ARMII::AddrMode5: {
2067 ImmIdx = FrameRegIdx+1;
2068 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2069 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2076 llvm_unreachable("Unsupported addressing mode!");
2079 Offset += InstrOffs * Scale;
2080 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2086 // Attempt to fold address comp. if opcode has offset bits
2088 // Common case: small offset, fits into instruction.
2089 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2090 int ImmedOffset = Offset / Scale;
2091 unsigned Mask = (1 << NumBits) - 1;
2092 if ((unsigned)Offset <= Mask * Scale) {
2093 // Replace the FrameIndex with sp
2094 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2095 // FIXME: When addrmode2 goes away, this will simplify (like the
2096 // T2 version), as the LDR.i12 versions don't need the encoding
2097 // tricks for the offset value.
2099 if (AddrMode == ARMII::AddrMode_i12)
2100 ImmedOffset = -ImmedOffset;
2102 ImmedOffset |= 1 << NumBits;
2104 ImmOp.ChangeToImmediate(ImmedOffset);
2109 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2110 ImmedOffset = ImmedOffset & Mask;
2112 if (AddrMode == ARMII::AddrMode_i12)
2113 ImmedOffset = -ImmedOffset;
2115 ImmedOffset |= 1 << NumBits;
2117 ImmOp.ChangeToImmediate(ImmedOffset);
2118 Offset &= ~(Mask*Scale);
2122 Offset = (isSub) ? -Offset : Offset;
2126 /// analyzeCompare - For a comparison instruction, return the source registers
2127 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2128 /// compares against in CmpValue. Return true if the comparison instruction
2129 /// can be analyzed.
2130 bool ARMBaseInstrInfo::
2131 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2132 int &CmpMask, int &CmpValue) const {
2133 switch (MI->getOpcode()) {
2137 SrcReg = MI->getOperand(0).getReg();
2140 CmpValue = MI->getOperand(1).getImm();
2144 SrcReg = MI->getOperand(0).getReg();
2145 SrcReg2 = MI->getOperand(1).getReg();
2151 SrcReg = MI->getOperand(0).getReg();
2153 CmpMask = MI->getOperand(1).getImm();
2161 /// isSuitableForMask - Identify a suitable 'and' instruction that
2162 /// operates on the given source register and applies the same mask
2163 /// as a 'tst' instruction. Provide a limited look-through for copies.
2164 /// When successful, MI will hold the found instruction.
2165 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2166 int CmpMask, bool CommonUse) {
2167 switch (MI->getOpcode()) {
2170 if (CmpMask != MI->getOperand(2).getImm())
2172 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2176 // Walk down one instruction which is potentially an 'and'.
2177 const MachineInstr &Copy = *MI;
2178 MachineBasicBlock::iterator AND(
2179 std::next(MachineBasicBlock::iterator(MI)));
2180 if (AND == MI->getParent()->end()) return false;
2182 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2190 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2191 /// the condition code if we modify the instructions such that flags are
2193 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2195 default: return ARMCC::AL;
2196 case ARMCC::EQ: return ARMCC::EQ;
2197 case ARMCC::NE: return ARMCC::NE;
2198 case ARMCC::HS: return ARMCC::LS;
2199 case ARMCC::LO: return ARMCC::HI;
2200 case ARMCC::HI: return ARMCC::LO;
2201 case ARMCC::LS: return ARMCC::HS;
2202 case ARMCC::GE: return ARMCC::LE;
2203 case ARMCC::LT: return ARMCC::GT;
2204 case ARMCC::GT: return ARMCC::LT;
2205 case ARMCC::LE: return ARMCC::GE;
2209 /// isRedundantFlagInstr - check whether the first instruction, whose only
2210 /// purpose is to update flags, can be made redundant.
2211 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2212 /// CMPri can be made redundant by SUBri if the operands are the same.
2213 /// This function can be extended later on.
2214 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2215 unsigned SrcReg2, int ImmValue,
2217 if ((CmpI->getOpcode() == ARM::CMPrr ||
2218 CmpI->getOpcode() == ARM::t2CMPrr) &&
2219 (OI->getOpcode() == ARM::SUBrr ||
2220 OI->getOpcode() == ARM::t2SUBrr) &&
2221 ((OI->getOperand(1).getReg() == SrcReg &&
2222 OI->getOperand(2).getReg() == SrcReg2) ||
2223 (OI->getOperand(1).getReg() == SrcReg2 &&
2224 OI->getOperand(2).getReg() == SrcReg)))
2227 if ((CmpI->getOpcode() == ARM::CMPri ||
2228 CmpI->getOpcode() == ARM::t2CMPri) &&
2229 (OI->getOpcode() == ARM::SUBri ||
2230 OI->getOpcode() == ARM::t2SUBri) &&
2231 OI->getOperand(1).getReg() == SrcReg &&
2232 OI->getOperand(2).getImm() == ImmValue)
2237 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2238 /// comparison into one that sets the zero bit in the flags register;
2239 /// Remove a redundant Compare instruction if an earlier instruction can set the
2240 /// flags in the same way as Compare.
2241 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2242 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2243 /// condition code of instructions which use the flags.
2244 bool ARMBaseInstrInfo::
2245 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2246 int CmpMask, int CmpValue,
2247 const MachineRegisterInfo *MRI) const {
2248 // Get the unique definition of SrcReg.
2249 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2250 if (!MI) return false;
2252 // Masked compares sometimes use the same register as the corresponding 'and'.
2253 if (CmpMask != ~0) {
2254 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2256 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2257 UE = MRI->use_end(); UI != UE; ++UI) {
2258 if (UI->getParent() != CmpInstr->getParent()) continue;
2259 MachineInstr *PotentialAND = &*UI;
2260 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2261 isPredicated(PotentialAND))
2266 if (!MI) return false;
2270 // Get ready to iterate backward from CmpInstr.
2271 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2272 B = CmpInstr->getParent()->begin();
2274 // Early exit if CmpInstr is at the beginning of the BB.
2275 if (I == B) return false;
2277 // There are two possible candidates which can be changed to set CPSR:
2278 // One is MI, the other is a SUB instruction.
2279 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2280 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2281 MachineInstr *Sub = NULL;
2283 // MI is not a candidate for CMPrr.
2285 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2286 // Conservatively refuse to convert an instruction which isn't in the same
2287 // BB as the comparison.
2288 // For CMPri, we need to check Sub, thus we can't return here.
2289 if (CmpInstr->getOpcode() == ARM::CMPri ||
2290 CmpInstr->getOpcode() == ARM::t2CMPri)
2296 // Check that CPSR isn't set between the comparison instruction and the one we
2297 // want to change. At the same time, search for Sub.
2298 const TargetRegisterInfo *TRI = &getRegisterInfo();
2300 for (; I != E; --I) {
2301 const MachineInstr &Instr = *I;
2303 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2304 Instr.readsRegister(ARM::CPSR, TRI))
2305 // This instruction modifies or uses CPSR after the one we want to
2306 // change. We can't do this transformation.
2309 // Check whether CmpInstr can be made redundant by the current instruction.
2310 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2316 // The 'and' is below the comparison instruction.
2320 // Return false if no candidates exist.
2324 // The single candidate is called MI.
2327 // We can't use a predicated instruction - it doesn't always write the flags.
2328 if (isPredicated(MI))
2331 switch (MI->getOpcode()) {
2365 case ARM::t2EORri: {
2366 // Scan forward for the use of CPSR
2367 // When checking against MI: if it's a conditional code requires
2368 // checking of V bit, then this is not safe to do.
2369 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2370 // If we are done with the basic block, we need to check whether CPSR is
2372 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2374 bool isSafe = false;
2376 E = CmpInstr->getParent()->end();
2377 while (!isSafe && ++I != E) {
2378 const MachineInstr &Instr = *I;
2379 for (unsigned IO = 0, EO = Instr.getNumOperands();
2380 !isSafe && IO != EO; ++IO) {
2381 const MachineOperand &MO = Instr.getOperand(IO);
2382 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2386 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2392 // Condition code is after the operand before CPSR except for VSELs.
2393 ARMCC::CondCodes CC;
2394 bool IsInstrVSel = true;
2395 switch (Instr.getOpcode()) {
2397 IsInstrVSel = false;
2398 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2419 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2420 if (NewCC == ARMCC::AL)
2422 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2423 // on CMP needs to be updated to be based on SUB.
2424 // Push the condition code operands to OperandsToUpdate.
2425 // If it is safe to remove CmpInstr, the condition code of these
2426 // operands will be modified.
2427 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2428 Sub->getOperand(2).getReg() == SrcReg) {
2429 // VSel doesn't support condition code update.
2432 OperandsToUpdate.push_back(
2433 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2438 // CPSR can be used multiple times, we should continue.
2451 // If CPSR is not killed nor re-defined, we should check whether it is
2452 // live-out. If it is live-out, do not optimize.
2454 MachineBasicBlock *MBB = CmpInstr->getParent();
2455 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2456 SE = MBB->succ_end(); SI != SE; ++SI)
2457 if ((*SI)->isLiveIn(ARM::CPSR))
2461 // Toggle the optional operand to CPSR.
2462 MI->getOperand(5).setReg(ARM::CPSR);
2463 MI->getOperand(5).setIsDef(true);
2464 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2465 CmpInstr->eraseFromParent();
2467 // Modify the condition code of operands in OperandsToUpdate.
2468 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2469 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2470 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2471 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2479 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2480 MachineInstr *DefMI, unsigned Reg,
2481 MachineRegisterInfo *MRI) const {
2482 // Fold large immediates into add, sub, or, xor.
2483 unsigned DefOpc = DefMI->getOpcode();
2484 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2486 if (!DefMI->getOperand(1).isImm())
2487 // Could be t2MOVi32imm <ga:xx>
2490 if (!MRI->hasOneNonDBGUse(Reg))
2493 const MCInstrDesc &DefMCID = DefMI->getDesc();
2494 if (DefMCID.hasOptionalDef()) {
2495 unsigned NumOps = DefMCID.getNumOperands();
2496 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2497 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2498 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2503 const MCInstrDesc &UseMCID = UseMI->getDesc();
2504 if (UseMCID.hasOptionalDef()) {
2505 unsigned NumOps = UseMCID.getNumOperands();
2506 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2507 // If the instruction sets the flag, do not attempt this optimization
2508 // since it may change the semantics of the code.
2512 unsigned UseOpc = UseMI->getOpcode();
2513 unsigned NewUseOpc = 0;
2514 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2515 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2516 bool Commute = false;
2518 default: return false;
2526 case ARM::t2EORrr: {
2527 Commute = UseMI->getOperand(2).getReg() != Reg;
2534 NewUseOpc = ARM::SUBri;
2540 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2542 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2543 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2546 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2547 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2548 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2552 case ARM::t2SUBrr: {
2556 NewUseOpc = ARM::t2SUBri;
2561 case ARM::t2EORrr: {
2562 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2564 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2565 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2568 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2569 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2570 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2578 unsigned OpIdx = Commute ? 2 : 1;
2579 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2580 bool isKill = UseMI->getOperand(OpIdx).isKill();
2581 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2582 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2583 UseMI, UseMI->getDebugLoc(),
2584 get(NewUseOpc), NewReg)
2585 .addReg(Reg1, getKillRegState(isKill))
2586 .addImm(SOImmValV1)));
2587 UseMI->setDesc(get(NewUseOpc));
2588 UseMI->getOperand(1).setReg(NewReg);
2589 UseMI->getOperand(1).setIsKill();
2590 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2591 DefMI->eraseFromParent();
2595 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2596 const MachineInstr *MI) {
2597 switch (MI->getOpcode()) {
2599 const MCInstrDesc &Desc = MI->getDesc();
2600 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2601 assert(UOps >= 0 && "bad # UOps");
2609 unsigned ShOpVal = MI->getOperand(3).getImm();
2610 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2611 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2614 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2615 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2622 if (!MI->getOperand(2).getReg())
2625 unsigned ShOpVal = MI->getOperand(3).getImm();
2626 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2627 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2630 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2631 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2638 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2640 case ARM::LDRSB_POST:
2641 case ARM::LDRSH_POST: {
2642 unsigned Rt = MI->getOperand(0).getReg();
2643 unsigned Rm = MI->getOperand(3).getReg();
2644 return (Rt == Rm) ? 4 : 3;
2647 case ARM::LDR_PRE_REG:
2648 case ARM::LDRB_PRE_REG: {
2649 unsigned Rt = MI->getOperand(0).getReg();
2650 unsigned Rm = MI->getOperand(3).getReg();
2653 unsigned ShOpVal = MI->getOperand(4).getImm();
2654 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2655 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2658 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2659 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2664 case ARM::STR_PRE_REG:
2665 case ARM::STRB_PRE_REG: {
2666 unsigned ShOpVal = MI->getOperand(4).getImm();
2667 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2668 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2671 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2672 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2678 case ARM::STRH_PRE: {
2679 unsigned Rt = MI->getOperand(0).getReg();
2680 unsigned Rm = MI->getOperand(3).getReg();
2685 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2689 case ARM::LDR_POST_REG:
2690 case ARM::LDRB_POST_REG:
2691 case ARM::LDRH_POST: {
2692 unsigned Rt = MI->getOperand(0).getReg();
2693 unsigned Rm = MI->getOperand(3).getReg();
2694 return (Rt == Rm) ? 3 : 2;
2697 case ARM::LDR_PRE_IMM:
2698 case ARM::LDRB_PRE_IMM:
2699 case ARM::LDR_POST_IMM:
2700 case ARM::LDRB_POST_IMM:
2701 case ARM::STRB_POST_IMM:
2702 case ARM::STRB_POST_REG:
2703 case ARM::STRB_PRE_IMM:
2704 case ARM::STRH_POST:
2705 case ARM::STR_POST_IMM:
2706 case ARM::STR_POST_REG:
2707 case ARM::STR_PRE_IMM:
2710 case ARM::LDRSB_PRE:
2711 case ARM::LDRSH_PRE: {
2712 unsigned Rm = MI->getOperand(3).getReg();
2715 unsigned Rt = MI->getOperand(0).getReg();
2718 unsigned ShOpVal = MI->getOperand(4).getImm();
2719 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2720 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2723 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2724 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2730 unsigned Rt = MI->getOperand(0).getReg();
2731 unsigned Rn = MI->getOperand(2).getReg();
2732 unsigned Rm = MI->getOperand(3).getReg();
2734 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2735 return (Rt == Rn) ? 3 : 2;
2739 unsigned Rm = MI->getOperand(3).getReg();
2741 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2745 case ARM::LDRD_POST:
2746 case ARM::t2LDRD_POST:
2749 case ARM::STRD_POST:
2750 case ARM::t2STRD_POST:
2753 case ARM::LDRD_PRE: {
2754 unsigned Rt = MI->getOperand(0).getReg();
2755 unsigned Rn = MI->getOperand(3).getReg();
2756 unsigned Rm = MI->getOperand(4).getReg();
2758 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2759 return (Rt == Rn) ? 4 : 3;
2762 case ARM::t2LDRD_PRE: {
2763 unsigned Rt = MI->getOperand(0).getReg();
2764 unsigned Rn = MI->getOperand(3).getReg();
2765 return (Rt == Rn) ? 4 : 3;
2768 case ARM::STRD_PRE: {
2769 unsigned Rm = MI->getOperand(4).getReg();
2771 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2775 case ARM::t2STRD_PRE:
2778 case ARM::t2LDR_POST:
2779 case ARM::t2LDRB_POST:
2780 case ARM::t2LDRB_PRE:
2781 case ARM::t2LDRSBi12:
2782 case ARM::t2LDRSBi8:
2783 case ARM::t2LDRSBpci:
2785 case ARM::t2LDRH_POST:
2786 case ARM::t2LDRH_PRE:
2788 case ARM::t2LDRSB_POST:
2789 case ARM::t2LDRSB_PRE:
2790 case ARM::t2LDRSH_POST:
2791 case ARM::t2LDRSH_PRE:
2792 case ARM::t2LDRSHi12:
2793 case ARM::t2LDRSHi8:
2794 case ARM::t2LDRSHpci:
2798 case ARM::t2LDRDi8: {
2799 unsigned Rt = MI->getOperand(0).getReg();
2800 unsigned Rn = MI->getOperand(2).getReg();
2801 return (Rt == Rn) ? 3 : 2;
2804 case ARM::t2STRB_POST:
2805 case ARM::t2STRB_PRE:
2808 case ARM::t2STRH_POST:
2809 case ARM::t2STRH_PRE:
2811 case ARM::t2STR_POST:
2812 case ARM::t2STR_PRE:
2818 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2819 // can't be easily determined return 0 (missing MachineMemOperand).
2821 // FIXME: The current MachineInstr design does not support relying on machine
2822 // mem operands to determine the width of a memory access. Instead, we expect
2823 // the target to provide this information based on the instruction opcode and
2824 // operands. However, using MachineMemOperand is a the best solution now for
2827 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2828 // operands. This is much more dangerous than using the MachineMemOperand
2829 // sizes because CodeGen passes can insert/remove optional machine operands. In
2830 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2831 // postRA passes as well.
2833 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2834 // machine model that calls this should handle the unknown (zero size) case.
2836 // Long term, we should require a target hook that verifies MachineMemOperand
2837 // sizes during MC lowering. That target hook should be local to MC lowering
2838 // because we can't ensure that it is aware of other MI forms. Doing this will
2839 // ensure that MachineMemOperands are correctly propagated through all passes.
2840 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2842 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2843 E = MI->memoperands_end(); I != E; ++I) {
2844 Size += (*I)->getSize();
2850 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2851 const MachineInstr *MI) const {
2852 if (!ItinData || ItinData->isEmpty())
2855 const MCInstrDesc &Desc = MI->getDesc();
2856 unsigned Class = Desc.getSchedClass();
2857 int ItinUOps = ItinData->getNumMicroOps(Class);
2858 if (ItinUOps >= 0) {
2859 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2860 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2865 unsigned Opc = MI->getOpcode();
2868 llvm_unreachable("Unexpected multi-uops instruction!");
2873 // The number of uOps for load / store multiple are determined by the number
2876 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2877 // same cycle. The scheduling for the first load / store must be done
2878 // separately by assuming the address is not 64-bit aligned.
2880 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2881 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2882 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2884 case ARM::VLDMDIA_UPD:
2885 case ARM::VLDMDDB_UPD:
2887 case ARM::VLDMSIA_UPD:
2888 case ARM::VLDMSDB_UPD:
2890 case ARM::VSTMDIA_UPD:
2891 case ARM::VSTMDDB_UPD:
2893 case ARM::VSTMSIA_UPD:
2894 case ARM::VSTMSDB_UPD: {
2895 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2896 return (NumRegs / 2) + (NumRegs % 2) + 1;
2899 case ARM::LDMIA_RET:
2904 case ARM::LDMIA_UPD:
2905 case ARM::LDMDA_UPD:
2906 case ARM::LDMDB_UPD:
2907 case ARM::LDMIB_UPD:
2912 case ARM::STMIA_UPD:
2913 case ARM::STMDA_UPD:
2914 case ARM::STMDB_UPD:
2915 case ARM::STMIB_UPD:
2917 case ARM::tLDMIA_UPD:
2918 case ARM::tSTMIA_UPD:
2922 case ARM::t2LDMIA_RET:
2925 case ARM::t2LDMIA_UPD:
2926 case ARM::t2LDMDB_UPD:
2929 case ARM::t2STMIA_UPD:
2930 case ARM::t2STMDB_UPD: {
2931 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2932 if (Subtarget.isSwift()) {
2933 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2936 case ARM::VLDMDIA_UPD:
2937 case ARM::VLDMDDB_UPD:
2938 case ARM::VLDMSIA_UPD:
2939 case ARM::VLDMSDB_UPD:
2940 case ARM::VSTMDIA_UPD:
2941 case ARM::VSTMDDB_UPD:
2942 case ARM::VSTMSIA_UPD:
2943 case ARM::VSTMSDB_UPD:
2944 case ARM::LDMIA_UPD:
2945 case ARM::LDMDA_UPD:
2946 case ARM::LDMDB_UPD:
2947 case ARM::LDMIB_UPD:
2948 case ARM::STMIA_UPD:
2949 case ARM::STMDA_UPD:
2950 case ARM::STMDB_UPD:
2951 case ARM::STMIB_UPD:
2952 case ARM::tLDMIA_UPD:
2953 case ARM::tSTMIA_UPD:
2954 case ARM::t2LDMIA_UPD:
2955 case ARM::t2LDMDB_UPD:
2956 case ARM::t2STMIA_UPD:
2957 case ARM::t2STMDB_UPD:
2958 ++UOps; // One for base register writeback.
2960 case ARM::LDMIA_RET:
2962 case ARM::t2LDMIA_RET:
2963 UOps += 2; // One for base reg wb, one for write to pc.
2967 } else if (Subtarget.isCortexA8()) {
2970 // 4 registers would be issued: 2, 2.
2971 // 5 registers would be issued: 2, 2, 1.
2972 int A8UOps = (NumRegs / 2);
2976 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2977 int A9UOps = (NumRegs / 2);
2978 // If there are odd number of registers or if it's not 64-bit aligned,
2979 // then it takes an extra AGU (Address Generation Unit) cycle.
2980 if ((NumRegs % 2) ||
2981 !MI->hasOneMemOperand() ||
2982 (*MI->memoperands_begin())->getAlignment() < 8)
2986 // Assume the worst.
2994 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2995 const MCInstrDesc &DefMCID,
2997 unsigned DefIdx, unsigned DefAlign) const {
2998 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3000 // Def is the address writeback.
3001 return ItinData->getOperandCycle(DefClass, DefIdx);
3004 if (Subtarget.isCortexA8()) {
3005 // (regno / 2) + (regno % 2) + 1
3006 DefCycle = RegNo / 2 + 1;
3009 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3011 bool isSLoad = false;
3013 switch (DefMCID.getOpcode()) {
3016 case ARM::VLDMSIA_UPD:
3017 case ARM::VLDMSDB_UPD:
3022 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3023 // then it takes an extra cycle.
3024 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3027 // Assume the worst.
3028 DefCycle = RegNo + 2;
3035 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3036 const MCInstrDesc &DefMCID,
3038 unsigned DefIdx, unsigned DefAlign) const {
3039 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3041 // Def is the address writeback.
3042 return ItinData->getOperandCycle(DefClass, DefIdx);
3045 if (Subtarget.isCortexA8()) {
3046 // 4 registers would be issued: 1, 2, 1.
3047 // 5 registers would be issued: 1, 2, 2.
3048 DefCycle = RegNo / 2;
3051 // Result latency is issue cycle + 2: E2.
3053 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3054 DefCycle = (RegNo / 2);
3055 // If there are odd number of registers or if it's not 64-bit aligned,
3056 // then it takes an extra AGU (Address Generation Unit) cycle.
3057 if ((RegNo % 2) || DefAlign < 8)
3059 // Result latency is AGU cycles + 2.
3062 // Assume the worst.
3063 DefCycle = RegNo + 2;
3070 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3071 const MCInstrDesc &UseMCID,
3073 unsigned UseIdx, unsigned UseAlign) const {
3074 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3076 return ItinData->getOperandCycle(UseClass, UseIdx);
3079 if (Subtarget.isCortexA8()) {
3080 // (regno / 2) + (regno % 2) + 1
3081 UseCycle = RegNo / 2 + 1;
3084 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3086 bool isSStore = false;
3088 switch (UseMCID.getOpcode()) {
3091 case ARM::VSTMSIA_UPD:
3092 case ARM::VSTMSDB_UPD:
3097 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3098 // then it takes an extra cycle.
3099 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3102 // Assume the worst.
3103 UseCycle = RegNo + 2;
3110 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3111 const MCInstrDesc &UseMCID,
3113 unsigned UseIdx, unsigned UseAlign) const {
3114 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3116 return ItinData->getOperandCycle(UseClass, UseIdx);
3119 if (Subtarget.isCortexA8()) {
3120 UseCycle = RegNo / 2;
3125 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3126 UseCycle = (RegNo / 2);
3127 // If there are odd number of registers or if it's not 64-bit aligned,
3128 // then it takes an extra AGU (Address Generation Unit) cycle.
3129 if ((RegNo % 2) || UseAlign < 8)
3132 // Assume the worst.
3139 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3140 const MCInstrDesc &DefMCID,
3141 unsigned DefIdx, unsigned DefAlign,
3142 const MCInstrDesc &UseMCID,
3143 unsigned UseIdx, unsigned UseAlign) const {
3144 unsigned DefClass = DefMCID.getSchedClass();
3145 unsigned UseClass = UseMCID.getSchedClass();
3147 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3148 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3150 // This may be a def / use of a variable_ops instruction, the operand
3151 // latency might be determinable dynamically. Let the target try to
3154 bool LdmBypass = false;
3155 switch (DefMCID.getOpcode()) {
3157 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3161 case ARM::VLDMDIA_UPD:
3162 case ARM::VLDMDDB_UPD:
3164 case ARM::VLDMSIA_UPD:
3165 case ARM::VLDMSDB_UPD:
3166 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3169 case ARM::LDMIA_RET:
3174 case ARM::LDMIA_UPD:
3175 case ARM::LDMDA_UPD:
3176 case ARM::LDMDB_UPD:
3177 case ARM::LDMIB_UPD:
3179 case ARM::tLDMIA_UPD:
3181 case ARM::t2LDMIA_RET:
3184 case ARM::t2LDMIA_UPD:
3185 case ARM::t2LDMDB_UPD:
3187 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3192 // We can't seem to determine the result latency of the def, assume it's 2.
3196 switch (UseMCID.getOpcode()) {
3198 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3202 case ARM::VSTMDIA_UPD:
3203 case ARM::VSTMDDB_UPD:
3205 case ARM::VSTMSIA_UPD:
3206 case ARM::VSTMSDB_UPD:
3207 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3214 case ARM::STMIA_UPD:
3215 case ARM::STMDA_UPD:
3216 case ARM::STMDB_UPD:
3217 case ARM::STMIB_UPD:
3218 case ARM::tSTMIA_UPD:
3223 case ARM::t2STMIA_UPD:
3224 case ARM::t2STMDB_UPD:
3225 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3230 // Assume it's read in the first stage.
3233 UseCycle = DefCycle - UseCycle + 1;
3236 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3237 // first def operand.
3238 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3241 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3242 UseClass, UseIdx)) {
3250 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3251 const MachineInstr *MI, unsigned Reg,
3252 unsigned &DefIdx, unsigned &Dist) {
3255 MachineBasicBlock::const_iterator I = MI; ++I;
3256 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3257 assert(II->isInsideBundle() && "Empty bundle?");
3260 while (II->isInsideBundle()) {
3261 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3268 assert(Idx != -1 && "Cannot find bundled definition!");
3273 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3274 const MachineInstr *MI, unsigned Reg,
3275 unsigned &UseIdx, unsigned &Dist) {
3278 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3279 assert(II->isInsideBundle() && "Empty bundle?");
3280 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3282 // FIXME: This doesn't properly handle multiple uses.
3284 while (II != E && II->isInsideBundle()) {
3285 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3288 if (II->getOpcode() != ARM::t2IT)
3302 /// Return the number of cycles to add to (or subtract from) the static
3303 /// itinerary based on the def opcode and alignment. The caller will ensure that
3304 /// adjusted latency is at least one cycle.
3305 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3306 const MachineInstr *DefMI,
3307 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3309 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3310 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3311 // variants are one cycle cheaper.
3312 switch (DefMCID->getOpcode()) {
3316 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3317 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3319 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3326 case ARM::t2LDRSHs: {
3327 // Thumb2 mode: lsl only.
3328 unsigned ShAmt = DefMI->getOperand(3).getImm();
3329 if (ShAmt == 0 || ShAmt == 2)
3334 } else if (Subtarget.isSwift()) {
3335 // FIXME: Properly handle all of the latency adjustments for address
3337 switch (DefMCID->getOpcode()) {
3341 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3342 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3343 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3346 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3347 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3350 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3357 case ARM::t2LDRSHs: {
3358 // Thumb2 mode: lsl only.
3359 unsigned ShAmt = DefMI->getOperand(3).getImm();
3360 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3367 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3368 switch (DefMCID->getOpcode()) {
3374 case ARM::VLD1q8wb_fixed:
3375 case ARM::VLD1q16wb_fixed:
3376 case ARM::VLD1q32wb_fixed:
3377 case ARM::VLD1q64wb_fixed:
3378 case ARM::VLD1q8wb_register:
3379 case ARM::VLD1q16wb_register:
3380 case ARM::VLD1q32wb_register:
3381 case ARM::VLD1q64wb_register:
3388 case ARM::VLD2d8wb_fixed:
3389 case ARM::VLD2d16wb_fixed:
3390 case ARM::VLD2d32wb_fixed:
3391 case ARM::VLD2q8wb_fixed:
3392 case ARM::VLD2q16wb_fixed:
3393 case ARM::VLD2q32wb_fixed:
3394 case ARM::VLD2d8wb_register:
3395 case ARM::VLD2d16wb_register:
3396 case ARM::VLD2d32wb_register:
3397 case ARM::VLD2q8wb_register:
3398 case ARM::VLD2q16wb_register:
3399 case ARM::VLD2q32wb_register:
3404 case ARM::VLD3d8_UPD:
3405 case ARM::VLD3d16_UPD:
3406 case ARM::VLD3d32_UPD:
3407 case ARM::VLD1d64Twb_fixed:
3408 case ARM::VLD1d64Twb_register:
3409 case ARM::VLD3q8_UPD:
3410 case ARM::VLD3q16_UPD:
3411 case ARM::VLD3q32_UPD:
3416 case ARM::VLD4d8_UPD:
3417 case ARM::VLD4d16_UPD:
3418 case ARM::VLD4d32_UPD:
3419 case ARM::VLD1d64Qwb_fixed:
3420 case ARM::VLD1d64Qwb_register:
3421 case ARM::VLD4q8_UPD:
3422 case ARM::VLD4q16_UPD:
3423 case ARM::VLD4q32_UPD:
3424 case ARM::VLD1DUPq8:
3425 case ARM::VLD1DUPq16:
3426 case ARM::VLD1DUPq32:
3427 case ARM::VLD1DUPq8wb_fixed:
3428 case ARM::VLD1DUPq16wb_fixed:
3429 case ARM::VLD1DUPq32wb_fixed:
3430 case ARM::VLD1DUPq8wb_register:
3431 case ARM::VLD1DUPq16wb_register:
3432 case ARM::VLD1DUPq32wb_register:
3433 case ARM::VLD2DUPd8:
3434 case ARM::VLD2DUPd16:
3435 case ARM::VLD2DUPd32:
3436 case ARM::VLD2DUPd8wb_fixed:
3437 case ARM::VLD2DUPd16wb_fixed:
3438 case ARM::VLD2DUPd32wb_fixed:
3439 case ARM::VLD2DUPd8wb_register:
3440 case ARM::VLD2DUPd16wb_register:
3441 case ARM::VLD2DUPd32wb_register:
3442 case ARM::VLD4DUPd8:
3443 case ARM::VLD4DUPd16:
3444 case ARM::VLD4DUPd32:
3445 case ARM::VLD4DUPd8_UPD:
3446 case ARM::VLD4DUPd16_UPD:
3447 case ARM::VLD4DUPd32_UPD:
3449 case ARM::VLD1LNd16:
3450 case ARM::VLD1LNd32:
3451 case ARM::VLD1LNd8_UPD:
3452 case ARM::VLD1LNd16_UPD:
3453 case ARM::VLD1LNd32_UPD:
3455 case ARM::VLD2LNd16:
3456 case ARM::VLD2LNd32:
3457 case ARM::VLD2LNq16:
3458 case ARM::VLD2LNq32:
3459 case ARM::VLD2LNd8_UPD:
3460 case ARM::VLD2LNd16_UPD:
3461 case ARM::VLD2LNd32_UPD:
3462 case ARM::VLD2LNq16_UPD:
3463 case ARM::VLD2LNq32_UPD:
3465 case ARM::VLD4LNd16:
3466 case ARM::VLD4LNd32:
3467 case ARM::VLD4LNq16:
3468 case ARM::VLD4LNq32:
3469 case ARM::VLD4LNd8_UPD:
3470 case ARM::VLD4LNd16_UPD:
3471 case ARM::VLD4LNd32_UPD:
3472 case ARM::VLD4LNq16_UPD:
3473 case ARM::VLD4LNq32_UPD:
3474 // If the address is not 64-bit aligned, the latencies of these
3475 // instructions increases by one.
3486 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3487 const MachineInstr *DefMI, unsigned DefIdx,
3488 const MachineInstr *UseMI,
3489 unsigned UseIdx) const {
3490 // No operand latency. The caller may fall back to getInstrLatency.
3491 if (!ItinData || ItinData->isEmpty())
3494 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3495 unsigned Reg = DefMO.getReg();
3496 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3497 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3499 unsigned DefAdj = 0;
3500 if (DefMI->isBundle()) {
3501 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3502 DefMCID = &DefMI->getDesc();
3504 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3505 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3509 unsigned UseAdj = 0;
3510 if (UseMI->isBundle()) {
3512 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3513 Reg, NewUseIdx, UseAdj);
3519 UseMCID = &UseMI->getDesc();
3522 if (Reg == ARM::CPSR) {
3523 if (DefMI->getOpcode() == ARM::FMSTAT) {
3524 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3525 return Subtarget.isLikeA9() ? 1 : 20;
3528 // CPSR set and branch can be paired in the same cycle.
3529 if (UseMI->isBranch())
3532 // Otherwise it takes the instruction latency (generally one).
3533 unsigned Latency = getInstrLatency(ItinData, DefMI);
3535 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3536 // its uses. Instructions which are otherwise scheduled between them may
3537 // incur a code size penalty (not able to use the CPSR setting 16-bit
3539 if (Latency > 0 && Subtarget.isThumb2()) {
3540 const MachineFunction *MF = DefMI->getParent()->getParent();
3541 if (MF->getFunction()->getAttributes().
3542 hasAttribute(AttributeSet::FunctionIndex,
3543 Attribute::OptimizeForSize))
3549 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3552 unsigned DefAlign = DefMI->hasOneMemOperand()
3553 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3554 unsigned UseAlign = UseMI->hasOneMemOperand()
3555 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3557 // Get the itinerary's latency if possible, and handle variable_ops.
3558 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3559 *UseMCID, UseIdx, UseAlign);
3560 // Unable to find operand latency. The caller may resort to getInstrLatency.
3564 // Adjust for IT block position.
3565 int Adj = DefAdj + UseAdj;
3567 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3568 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3569 if (Adj >= 0 || (int)Latency > -Adj) {
3570 return Latency + Adj;
3572 // Return the itinerary latency, which may be zero but not less than zero.
3577 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3578 SDNode *DefNode, unsigned DefIdx,
3579 SDNode *UseNode, unsigned UseIdx) const {
3580 if (!DefNode->isMachineOpcode())
3583 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3585 if (isZeroCost(DefMCID.Opcode))
3588 if (!ItinData || ItinData->isEmpty())
3589 return DefMCID.mayLoad() ? 3 : 1;
3591 if (!UseNode->isMachineOpcode()) {
3592 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3593 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3594 return Latency <= 2 ? 1 : Latency - 1;
3596 return Latency <= 3 ? 1 : Latency - 2;
3599 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3600 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3601 unsigned DefAlign = !DefMN->memoperands_empty()
3602 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3603 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3604 unsigned UseAlign = !UseMN->memoperands_empty()
3605 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3606 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3607 UseMCID, UseIdx, UseAlign);
3610 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3611 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3612 // variants are one cycle cheaper.
3613 switch (DefMCID.getOpcode()) {
3618 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3619 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3621 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3628 case ARM::t2LDRSHs: {
3629 // Thumb2 mode: lsl only.
3631 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3632 if (ShAmt == 0 || ShAmt == 2)
3637 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3638 // FIXME: Properly handle all of the latency adjustments for address
3640 switch (DefMCID.getOpcode()) {
3645 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3646 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3648 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3649 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3651 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3658 case ARM::t2LDRSHs: {
3659 // Thumb2 mode: lsl 0-3 only.
3666 if (DefAlign < 8 && Subtarget.isLikeA9())
3667 switch (DefMCID.getOpcode()) {
3673 case ARM::VLD1q8wb_register:
3674 case ARM::VLD1q16wb_register:
3675 case ARM::VLD1q32wb_register:
3676 case ARM::VLD1q64wb_register:
3677 case ARM::VLD1q8wb_fixed:
3678 case ARM::VLD1q16wb_fixed:
3679 case ARM::VLD1q32wb_fixed:
3680 case ARM::VLD1q64wb_fixed:
3684 case ARM::VLD2q8Pseudo:
3685 case ARM::VLD2q16Pseudo:
3686 case ARM::VLD2q32Pseudo:
3687 case ARM::VLD2d8wb_fixed:
3688 case ARM::VLD2d16wb_fixed:
3689 case ARM::VLD2d32wb_fixed:
3690 case ARM::VLD2q8PseudoWB_fixed:
3691 case ARM::VLD2q16PseudoWB_fixed:
3692 case ARM::VLD2q32PseudoWB_fixed:
3693 case ARM::VLD2d8wb_register:
3694 case ARM::VLD2d16wb_register:
3695 case ARM::VLD2d32wb_register:
3696 case ARM::VLD2q8PseudoWB_register:
3697 case ARM::VLD2q16PseudoWB_register:
3698 case ARM::VLD2q32PseudoWB_register:
3699 case ARM::VLD3d8Pseudo:
3700 case ARM::VLD3d16Pseudo:
3701 case ARM::VLD3d32Pseudo:
3702 case ARM::VLD1d64TPseudo:
3703 case ARM::VLD1d64TPseudoWB_fixed:
3704 case ARM::VLD3d8Pseudo_UPD:
3705 case ARM::VLD3d16Pseudo_UPD:
3706 case ARM::VLD3d32Pseudo_UPD:
3707 case ARM::VLD3q8Pseudo_UPD:
3708 case ARM::VLD3q16Pseudo_UPD:
3709 case ARM::VLD3q32Pseudo_UPD:
3710 case ARM::VLD3q8oddPseudo:
3711 case ARM::VLD3q16oddPseudo:
3712 case ARM::VLD3q32oddPseudo:
3713 case ARM::VLD3q8oddPseudo_UPD:
3714 case ARM::VLD3q16oddPseudo_UPD:
3715 case ARM::VLD3q32oddPseudo_UPD:
3716 case ARM::VLD4d8Pseudo:
3717 case ARM::VLD4d16Pseudo:
3718 case ARM::VLD4d32Pseudo:
3719 case ARM::VLD1d64QPseudo:
3720 case ARM::VLD1d64QPseudoWB_fixed:
3721 case ARM::VLD4d8Pseudo_UPD:
3722 case ARM::VLD4d16Pseudo_UPD:
3723 case ARM::VLD4d32Pseudo_UPD:
3724 case ARM::VLD4q8Pseudo_UPD:
3725 case ARM::VLD4q16Pseudo_UPD:
3726 case ARM::VLD4q32Pseudo_UPD:
3727 case ARM::VLD4q8oddPseudo:
3728 case ARM::VLD4q16oddPseudo:
3729 case ARM::VLD4q32oddPseudo:
3730 case ARM::VLD4q8oddPseudo_UPD:
3731 case ARM::VLD4q16oddPseudo_UPD:
3732 case ARM::VLD4q32oddPseudo_UPD:
3733 case ARM::VLD1DUPq8:
3734 case ARM::VLD1DUPq16:
3735 case ARM::VLD1DUPq32:
3736 case ARM::VLD1DUPq8wb_fixed:
3737 case ARM::VLD1DUPq16wb_fixed:
3738 case ARM::VLD1DUPq32wb_fixed:
3739 case ARM::VLD1DUPq8wb_register:
3740 case ARM::VLD1DUPq16wb_register:
3741 case ARM::VLD1DUPq32wb_register:
3742 case ARM::VLD2DUPd8:
3743 case ARM::VLD2DUPd16:
3744 case ARM::VLD2DUPd32:
3745 case ARM::VLD2DUPd8wb_fixed:
3746 case ARM::VLD2DUPd16wb_fixed:
3747 case ARM::VLD2DUPd32wb_fixed:
3748 case ARM::VLD2DUPd8wb_register:
3749 case ARM::VLD2DUPd16wb_register:
3750 case ARM::VLD2DUPd32wb_register:
3751 case ARM::VLD4DUPd8Pseudo:
3752 case ARM::VLD4DUPd16Pseudo:
3753 case ARM::VLD4DUPd32Pseudo:
3754 case ARM::VLD4DUPd8Pseudo_UPD:
3755 case ARM::VLD4DUPd16Pseudo_UPD:
3756 case ARM::VLD4DUPd32Pseudo_UPD:
3757 case ARM::VLD1LNq8Pseudo:
3758 case ARM::VLD1LNq16Pseudo:
3759 case ARM::VLD1LNq32Pseudo:
3760 case ARM::VLD1LNq8Pseudo_UPD:
3761 case ARM::VLD1LNq16Pseudo_UPD:
3762 case ARM::VLD1LNq32Pseudo_UPD:
3763 case ARM::VLD2LNd8Pseudo:
3764 case ARM::VLD2LNd16Pseudo:
3765 case ARM::VLD2LNd32Pseudo:
3766 case ARM::VLD2LNq16Pseudo:
3767 case ARM::VLD2LNq32Pseudo:
3768 case ARM::VLD2LNd8Pseudo_UPD:
3769 case ARM::VLD2LNd16Pseudo_UPD:
3770 case ARM::VLD2LNd32Pseudo_UPD:
3771 case ARM::VLD2LNq16Pseudo_UPD:
3772 case ARM::VLD2LNq32Pseudo_UPD:
3773 case ARM::VLD4LNd8Pseudo:
3774 case ARM::VLD4LNd16Pseudo:
3775 case ARM::VLD4LNd32Pseudo:
3776 case ARM::VLD4LNq16Pseudo:
3777 case ARM::VLD4LNq32Pseudo:
3778 case ARM::VLD4LNd8Pseudo_UPD:
3779 case ARM::VLD4LNd16Pseudo_UPD:
3780 case ARM::VLD4LNd32Pseudo_UPD:
3781 case ARM::VLD4LNq16Pseudo_UPD:
3782 case ARM::VLD4LNq32Pseudo_UPD:
3783 // If the address is not 64-bit aligned, the latencies of these
3784 // instructions increases by one.
3792 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3793 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3794 MI->isRegSequence() || MI->isImplicitDef())
3800 const MCInstrDesc &MCID = MI->getDesc();
3802 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3803 // When predicated, CPSR is an additional source operand for CPSR updating
3804 // instructions, this apparently increases their latencies.
3810 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3811 const MachineInstr *MI,
3812 unsigned *PredCost) const {
3813 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3814 MI->isRegSequence() || MI->isImplicitDef())
3817 // An instruction scheduler typically runs on unbundled instructions, however
3818 // other passes may query the latency of a bundled instruction.
3819 if (MI->isBundle()) {
3820 unsigned Latency = 0;
3821 MachineBasicBlock::const_instr_iterator I = MI;
3822 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3823 while (++I != E && I->isInsideBundle()) {
3824 if (I->getOpcode() != ARM::t2IT)
3825 Latency += getInstrLatency(ItinData, I, PredCost);
3830 const MCInstrDesc &MCID = MI->getDesc();
3831 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3832 // When predicated, CPSR is an additional source operand for CPSR updating
3833 // instructions, this apparently increases their latencies.
3836 // Be sure to call getStageLatency for an empty itinerary in case it has a
3837 // valid MinLatency property.
3839 return MI->mayLoad() ? 3 : 1;
3841 unsigned Class = MCID.getSchedClass();
3843 // For instructions with variable uops, use uops as latency.
3844 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3845 return getNumMicroOps(ItinData, MI);
3847 // For the common case, fall back on the itinerary's latency.
3848 unsigned Latency = ItinData->getStageLatency(Class);
3850 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3851 unsigned DefAlign = MI->hasOneMemOperand()
3852 ? (*MI->memoperands_begin())->getAlignment() : 0;
3853 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3854 if (Adj >= 0 || (int)Latency > -Adj) {
3855 return Latency + Adj;
3860 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3861 SDNode *Node) const {
3862 if (!Node->isMachineOpcode())
3865 if (!ItinData || ItinData->isEmpty())
3868 unsigned Opcode = Node->getMachineOpcode();
3871 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3878 bool ARMBaseInstrInfo::
3879 hasHighOperandLatency(const InstrItineraryData *ItinData,
3880 const MachineRegisterInfo *MRI,
3881 const MachineInstr *DefMI, unsigned DefIdx,
3882 const MachineInstr *UseMI, unsigned UseIdx) const {
3883 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3884 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3885 if (Subtarget.isCortexA8() &&
3886 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3887 // CortexA8 VFP instructions are not pipelined.
3890 // Hoist VFP / NEON instructions with 4 or higher latency.
3891 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3893 Latency = getInstrLatency(ItinData, DefMI);
3896 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3897 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3900 bool ARMBaseInstrInfo::
3901 hasLowDefLatency(const InstrItineraryData *ItinData,
3902 const MachineInstr *DefMI, unsigned DefIdx) const {
3903 if (!ItinData || ItinData->isEmpty())
3906 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3907 if (DDomain == ARMII::DomainGeneral) {
3908 unsigned DefClass = DefMI->getDesc().getSchedClass();
3909 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3910 return (DefCycle != -1 && DefCycle <= 2);
3915 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3916 StringRef &ErrInfo) const {
3917 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3918 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3925 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3926 unsigned &AddSubOpc,
3927 bool &NegAcc, bool &HasLane) const {
3928 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3929 if (I == MLxEntryMap.end())
3932 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3933 MulOpc = Entry.MulOpc;
3934 AddSubOpc = Entry.AddSubOpc;
3935 NegAcc = Entry.NegAcc;
3936 HasLane = Entry.HasLane;
3940 //===----------------------------------------------------------------------===//
3941 // Execution domains.
3942 //===----------------------------------------------------------------------===//
3944 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3945 // and some can go down both. The vmov instructions go down the VFP pipeline,
3946 // but they can be changed to vorr equivalents that are executed by the NEON
3949 // We use the following execution domain numbering:
3957 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3959 std::pair<uint16_t, uint16_t>
3960 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3961 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3962 // if they are not predicated.
3963 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3964 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3966 // CortexA9 is particularly picky about mixing the two and wants these
3968 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3969 (MI->getOpcode() == ARM::VMOVRS ||
3970 MI->getOpcode() == ARM::VMOVSR ||
3971 MI->getOpcode() == ARM::VMOVS))
3972 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3974 // No other instructions can be swizzled, so just determine their domain.
3975 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3977 if (Domain & ARMII::DomainNEON)
3978 return std::make_pair(ExeNEON, 0);
3980 // Certain instructions can go either way on Cortex-A8.
3981 // Treat them as NEON instructions.
3982 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3983 return std::make_pair(ExeNEON, 0);
3985 if (Domain & ARMII::DomainVFP)
3986 return std::make_pair(ExeVFP, 0);
3988 return std::make_pair(ExeGeneric, 0);
3991 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3992 unsigned SReg, unsigned &Lane) {
3993 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3996 if (DReg != ARM::NoRegister)
4000 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4002 assert(DReg && "S-register with no D super-register?");
4006 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4007 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4008 /// zero if no register needs to be defined as implicit-use.
4010 /// If the function cannot determine if an SPR should be marked implicit use or
4011 /// not, it returns false.
4013 /// This function handles cases where an instruction is being modified from taking
4014 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4015 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4016 /// lane of the DPR).
4018 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4019 /// (including the case where the DPR itself is defined), it should not.
4021 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4023 unsigned DReg, unsigned Lane,
4024 unsigned &ImplicitSReg) {
4025 // If the DPR is defined or used already, the other SPR lane will be chained
4026 // correctly, so there is nothing to be done.
4027 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4032 // Otherwise we need to go searching to see if the SPR is set explicitly.
4033 ImplicitSReg = TRI->getSubReg(DReg,
4034 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4035 MachineBasicBlock::LivenessQueryResult LQR =
4036 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4038 if (LQR == MachineBasicBlock::LQR_Live)
4040 else if (LQR == MachineBasicBlock::LQR_Unknown)
4043 // If the register is known not to be live, there is no need to add an
4050 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4051 unsigned DstReg, SrcReg, DReg;
4053 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4054 const TargetRegisterInfo *TRI = &getRegisterInfo();
4055 switch (MI->getOpcode()) {
4057 llvm_unreachable("cannot handle opcode!");
4060 if (Domain != ExeNEON)
4063 // Zap the predicate operands.
4064 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4066 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4067 DstReg = MI->getOperand(0).getReg();
4068 SrcReg = MI->getOperand(1).getReg();
4070 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4071 MI->RemoveOperand(i-1);
4073 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4074 MI->setDesc(get(ARM::VORRd));
4075 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4080 if (Domain != ExeNEON)
4082 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4084 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4085 DstReg = MI->getOperand(0).getReg();
4086 SrcReg = MI->getOperand(1).getReg();
4088 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4089 MI->RemoveOperand(i-1);
4091 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4093 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4094 // Note that DSrc has been widened and the other lane may be undef, which
4095 // contaminates the entire register.
4096 MI->setDesc(get(ARM::VGETLNi32));
4097 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4098 .addReg(DReg, RegState::Undef)
4101 // The old source should be an implicit use, otherwise we might think it
4102 // was dead before here.
4103 MIB.addReg(SrcReg, RegState::Implicit);
4106 if (Domain != ExeNEON)
4108 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4110 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4111 DstReg = MI->getOperand(0).getReg();
4112 SrcReg = MI->getOperand(1).getReg();
4114 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4116 unsigned ImplicitSReg;
4117 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4120 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4121 MI->RemoveOperand(i-1);
4123 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4124 // Again DDst may be undefined at the beginning of this instruction.
4125 MI->setDesc(get(ARM::VSETLNi32));
4126 MIB.addReg(DReg, RegState::Define)
4127 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4130 AddDefaultPred(MIB);
4132 // The narrower destination must be marked as set to keep previous chains
4134 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4135 if (ImplicitSReg != 0)
4136 MIB.addReg(ImplicitSReg, RegState::Implicit);
4140 if (Domain != ExeNEON)
4143 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4144 DstReg = MI->getOperand(0).getReg();
4145 SrcReg = MI->getOperand(1).getReg();
4147 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4148 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4149 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4151 unsigned ImplicitSReg;
4152 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4155 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4156 MI->RemoveOperand(i-1);
4159 // Destination can be:
4160 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4161 MI->setDesc(get(ARM::VDUPLN32d));
4162 MIB.addReg(DDst, RegState::Define)
4163 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4165 AddDefaultPred(MIB);
4167 // Neither the source or the destination are naturally represented any
4168 // more, so add them in manually.
4169 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4170 MIB.addReg(SrcReg, RegState::Implicit);
4171 if (ImplicitSReg != 0)
4172 MIB.addReg(ImplicitSReg, RegState::Implicit);
4176 // In general there's no single instruction that can perform an S <-> S
4177 // move in NEON space, but a pair of VEXT instructions *can* do the
4178 // job. It turns out that the VEXTs needed will only use DSrc once, with
4179 // the position based purely on the combination of lane-0 and lane-1
4180 // involved. For example
4181 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4182 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4183 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4184 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4186 // Pattern of the MachineInstrs is:
4187 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4188 MachineInstrBuilder NewMIB;
4189 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4190 get(ARM::VEXTd32), DDst);
4192 // On the first instruction, both DSrc and DDst may be <undef> if present.
4193 // Specifically when the original instruction didn't have them as an
4195 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4196 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4197 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4199 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4200 CurUndef = !MI->readsRegister(CurReg, TRI);
4201 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4204 AddDefaultPred(NewMIB);
4206 if (SrcLane == DstLane)
4207 NewMIB.addReg(SrcReg, RegState::Implicit);
4209 MI->setDesc(get(ARM::VEXTd32));
4210 MIB.addReg(DDst, RegState::Define);
4212 // On the second instruction, DDst has definitely been defined above, so
4213 // it is not <undef>. DSrc, if present, can be <undef> as above.
4214 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4215 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4216 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4218 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4219 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4220 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4223 AddDefaultPred(MIB);
4225 if (SrcLane != DstLane)
4226 MIB.addReg(SrcReg, RegState::Implicit);
4228 // As before, the original destination is no longer represented, add it
4230 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4231 if (ImplicitSReg != 0)
4232 MIB.addReg(ImplicitSReg, RegState::Implicit);
4239 //===----------------------------------------------------------------------===//
4240 // Partial register updates
4241 //===----------------------------------------------------------------------===//
4243 // Swift renames NEON registers with 64-bit granularity. That means any
4244 // instruction writing an S-reg implicitly reads the containing D-reg. The
4245 // problem is mostly avoided by translating f32 operations to v2f32 operations
4246 // on D-registers, but f32 loads are still a problem.
4248 // These instructions can load an f32 into a NEON register:
4250 // VLDRS - Only writes S, partial D update.
4251 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4252 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4254 // FCONSTD can be used as a dependency-breaking instruction.
4255 unsigned ARMBaseInstrInfo::
4256 getPartialRegUpdateClearance(const MachineInstr *MI,
4258 const TargetRegisterInfo *TRI) const {
4259 if (!SwiftPartialUpdateClearance ||
4260 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4263 assert(TRI && "Need TRI instance");
4265 const MachineOperand &MO = MI->getOperand(OpNum);
4268 unsigned Reg = MO.getReg();
4271 switch(MI->getOpcode()) {
4272 // Normal instructions writing only an S-register.
4277 case ARM::VMOVv4i16:
4278 case ARM::VMOVv2i32:
4279 case ARM::VMOVv2f32:
4280 case ARM::VMOVv1i64:
4281 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4284 // Explicitly reads the dependency.
4285 case ARM::VLD1LNd32:
4292 // If this instruction actually reads a value from Reg, there is no unwanted
4294 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4297 // We must be able to clobber the whole D-reg.
4298 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4299 // Virtual register must be a foo:ssub_0<def,undef> operand.
4300 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4302 } else if (ARM::SPRRegClass.contains(Reg)) {
4303 // Physical register: MI must define the full D-reg.
4304 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4306 if (!DReg || !MI->definesRegister(DReg, TRI))
4310 // MI has an unwanted D-register dependency.
4311 // Avoid defs in the previous N instructrions.
4312 return SwiftPartialUpdateClearance;
4315 // Break a partial register dependency after getPartialRegUpdateClearance
4316 // returned non-zero.
4317 void ARMBaseInstrInfo::
4318 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4320 const TargetRegisterInfo *TRI) const {
4321 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4322 assert(TRI && "Need TRI instance");
4324 const MachineOperand &MO = MI->getOperand(OpNum);
4325 unsigned Reg = MO.getReg();
4326 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4327 "Can't break virtual register dependencies.");
4328 unsigned DReg = Reg;
4330 // If MI defines an S-reg, find the corresponding D super-register.
4331 if (ARM::SPRRegClass.contains(Reg)) {
4332 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4333 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4336 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4337 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4339 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4340 // the full D-register by loading the same value to both lanes. The
4341 // instruction is micro-coded with 2 uops, so don't do this until we can
4342 // properly schedule micro-coded instructions. The dispatcher stalls cause
4343 // too big regressions.
4345 // Insert the dependency-breaking FCONSTD before MI.
4346 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4347 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4348 get(ARM::FCONSTD), DReg).addImm(96));
4349 MI->addRegisterKilled(DReg, TRI, true);
4352 bool ARMBaseInstrInfo::hasNOP() const {
4353 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4356 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4357 if (MI->getNumOperands() < 4)
4359 unsigned ShOpVal = MI->getOperand(3).getImm();
4360 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4361 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4362 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4363 ((ShImm == 1 || ShImm == 2) &&
4364 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))