1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
160 assert(false && "Unknown indexed op!");
162 case ARMII::AddrMode2: {
163 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
164 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
166 if (ARM_AM::getSOImmVal(Amt) == -1)
167 // Can't encode it in a so_imm operand. This transformation will
168 // add more than 1 instruction. Abandon!
170 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
171 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
172 .addReg(BaseReg).addImm(Amt)
173 .addImm(Pred).addReg(0).addReg(0);
174 } else if (Amt != 0) {
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
179 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
180 .addImm(Pred).addReg(0).addReg(0);
182 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
183 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
184 .addReg(BaseReg).addReg(OffReg)
185 .addImm(Pred).addReg(0).addReg(0);
188 case ARMII::AddrMode3 : {
189 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
190 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
192 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
193 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
194 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
195 .addReg(BaseReg).addImm(Amt)
196 .addImm(Pred).addReg(0).addReg(0);
198 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
199 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
200 .addReg(BaseReg).addReg(OffReg)
201 .addImm(Pred).addReg(0).addReg(0);
206 std::vector<MachineInstr*> NewMIs;
209 MemMI = BuildMI(MF, MI->getDebugLoc(),
210 get(MemOpc), MI->getOperand(0).getReg())
211 .addReg(WBReg).addImm(0).addImm(Pred);
213 MemMI = BuildMI(MF, MI->getDebugLoc(),
214 get(MemOpc)).addReg(MI->getOperand(1).getReg())
215 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
216 NewMIs.push_back(MemMI);
217 NewMIs.push_back(UpdateMI);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc), MI->getOperand(0).getReg())
222 .addReg(BaseReg).addImm(0).addImm(Pred);
224 MemMI = BuildMI(MF, MI->getDebugLoc(),
225 get(MemOpc)).addReg(MI->getOperand(1).getReg())
226 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
228 UpdateMI->getOperand(0).setIsDead();
229 NewMIs.push_back(UpdateMI);
230 NewMIs.push_back(MemMI);
233 // Transfer LiveVariables states, kill / dead info.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = MI->getOperand(i);
237 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
238 unsigned Reg = MO.getReg();
240 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
242 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
244 LV->addVirtualRegisterDead(Reg, NewMI);
246 if (MO.isUse() && MO.isKill()) {
247 for (unsigned j = 0; j < 2; ++j) {
248 // Look at the two new MI's in reverse order.
249 MachineInstr *NewMI = NewMIs[j];
250 if (!NewMI->readsRegister(Reg))
252 LV->addVirtualRegisterKilled(Reg, NewMI);
253 if (VI.removeKill(MI))
254 VI.Kills.push_back(NewMI);
262 MFI->insert(MBBI, NewMIs[1]);
263 MFI->insert(MBBI, NewMIs[0]);
269 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
270 MachineBasicBlock *&FBB,
271 SmallVectorImpl<MachineOperand> &Cond,
272 bool AllowModify) const {
273 // If the block has no terminators, it just falls into the block after it.
274 MachineBasicBlock::iterator I = MBB.end();
275 if (I == MBB.begin())
278 while (I->isDebugValue()) {
279 if (I == MBB.begin())
283 if (!isUnpredicatedTerminator(I))
286 // Get the last instruction in the block.
287 MachineInstr *LastInst = I;
289 // If there is only one terminator instruction, process it.
290 unsigned LastOpc = LastInst->getOpcode();
291 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
292 if (isUncondBranchOpcode(LastOpc)) {
293 TBB = LastInst->getOperand(0).getMBB();
296 if (isCondBranchOpcode(LastOpc)) {
297 // Block ends with fall-through condbranch.
298 TBB = LastInst->getOperand(0).getMBB();
299 Cond.push_back(LastInst->getOperand(1));
300 Cond.push_back(LastInst->getOperand(2));
303 return true; // Can't handle indirect branch.
306 // Get the instruction before it if it is a terminator.
307 MachineInstr *SecondLastInst = I;
308 unsigned SecondLastOpc = SecondLastInst->getOpcode();
310 // If AllowModify is true and the block ends with two or more unconditional
311 // branches, delete all but the first unconditional branch.
312 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
313 while (isUncondBranchOpcode(SecondLastOpc)) {
314 LastInst->eraseFromParent();
315 LastInst = SecondLastInst;
316 LastOpc = LastInst->getOpcode();
317 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
318 // Return now the only terminator is an unconditional branch.
319 TBB = LastInst->getOperand(0).getMBB();
323 SecondLastOpc = SecondLastInst->getOpcode();
328 // If there are three terminators, we don't know what sort of block this is.
329 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
332 // If the block ends with a B and a Bcc, handle it.
333 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
334 TBB = SecondLastInst->getOperand(0).getMBB();
335 Cond.push_back(SecondLastInst->getOperand(1));
336 Cond.push_back(SecondLastInst->getOperand(2));
337 FBB = LastInst->getOperand(0).getMBB();
341 // If the block ends with two unconditional branches, handle it. The second
342 // one is not executed, so remove it.
343 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
344 TBB = SecondLastInst->getOperand(0).getMBB();
347 I->eraseFromParent();
351 // ...likewise if it ends with a branch table followed by an unconditional
352 // branch. The branch folder can create these, and we must get rid of them for
353 // correctness of Thumb constant islands.
354 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
355 isIndirectBranchOpcode(SecondLastOpc)) &&
356 isUncondBranchOpcode(LastOpc)) {
359 I->eraseFromParent();
363 // Otherwise, can't handle this.
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 while (I->isDebugValue()) {
373 if (I == MBB.begin())
377 if (!isUncondBranchOpcode(I->getOpcode()) &&
378 !isCondBranchOpcode(I->getOpcode()))
381 // Remove the branch.
382 I->eraseFromParent();
386 if (I == MBB.begin()) return 1;
388 if (!isCondBranchOpcode(I->getOpcode()))
391 // Remove the branch.
392 I->eraseFromParent();
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 MachineBasicBlock *FBB,
399 const SmallVectorImpl<MachineOperand> &Cond,
401 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
402 int BOpc = !AFI->isThumbFunction()
403 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
404 int BccOpc = !AFI->isThumbFunction()
405 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
406 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
408 // Shouldn't be a fall through.
409 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 assert((Cond.size() == 2 || Cond.size() == 0) &&
411 "ARM branch conditions have two components!");
414 if (Cond.empty()) { // Unconditional branch?
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
418 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
420 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
425 // Two-way conditional branch.
426 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
427 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
431 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
435 bool ARMBaseInstrInfo::
436 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
437 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
438 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
442 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
443 if (MI->isBundle()) {
444 MachineBasicBlock::const_instr_iterator I = MI;
445 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
446 while (++I != E && I->isInsideBundle()) {
447 int PIdx = I->findFirstPredOperandIdx();
448 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
454 int PIdx = MI->findFirstPredOperandIdx();
455 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
458 bool ARMBaseInstrInfo::
459 PredicateInstruction(MachineInstr *MI,
460 const SmallVectorImpl<MachineOperand> &Pred) const {
461 unsigned Opc = MI->getOpcode();
462 if (isUncondBranchOpcode(Opc)) {
463 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
464 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
465 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
469 int PIdx = MI->findFirstPredOperandIdx();
471 MachineOperand &PMO = MI->getOperand(PIdx);
472 PMO.setImm(Pred[0].getImm());
473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
479 bool ARMBaseInstrInfo::
480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
481 const SmallVectorImpl<MachineOperand> &Pred2) const {
482 if (Pred1.size() > 2 || Pred2.size() > 2)
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
496 return CC2 == ARMCC::HI;
498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
500 return CC2 == ARMCC::GT;
502 return CC2 == ARMCC::LT;
506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
507 std::vector<MachineOperand> &Pred) const {
508 // FIXME: This confuses implicit_def with optional CPSR def.
509 const MCInstrDesc &MCID = MI->getDesc();
510 if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
514 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
515 const MachineOperand &MO = MI->getOperand(i);
516 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
525 /// isPredicable - Return true if the specified instruction can be predicated.
526 /// By default, this returns true for every instruction with a
527 /// PredicateOperand.
528 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
529 if (!MI->isPredicable())
532 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
533 ARMFunctionInfo *AFI =
534 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
535 return AFI->isThumb2Function();
540 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
541 LLVM_ATTRIBUTE_NOINLINE
542 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
544 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
546 assert(JTI < JT.size());
547 return JT[JTI].MBBs.size();
550 /// GetInstSize - Return the size of the specified MachineInstr.
552 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
553 const MachineBasicBlock &MBB = *MI->getParent();
554 const MachineFunction *MF = MBB.getParent();
555 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
557 const MCInstrDesc &MCID = MI->getDesc();
559 return MCID.getSize();
561 // If this machine instr is an inline asm, measure it.
562 if (MI->getOpcode() == ARM::INLINEASM)
563 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
566 unsigned Opc = MI->getOpcode();
568 case TargetOpcode::IMPLICIT_DEF:
569 case TargetOpcode::KILL:
570 case TargetOpcode::PROLOG_LABEL:
571 case TargetOpcode::EH_LABEL:
572 case TargetOpcode::DBG_VALUE:
574 case TargetOpcode::BUNDLE:
575 return getInstBundleLength(MI);
576 case ARM::MOVi16_ga_pcrel:
577 case ARM::MOVTi16_ga_pcrel:
578 case ARM::t2MOVi16_ga_pcrel:
579 case ARM::t2MOVTi16_ga_pcrel:
582 case ARM::t2MOVi32imm:
584 case ARM::CONSTPOOL_ENTRY:
585 // If this machine instr is a constant pool entry, its size is recorded as
587 return MI->getOperand(2).getImm();
588 case ARM::Int_eh_sjlj_longjmp:
590 case ARM::tInt_eh_sjlj_longjmp:
592 case ARM::Int_eh_sjlj_setjmp:
593 case ARM::Int_eh_sjlj_setjmp_nofp:
595 case ARM::tInt_eh_sjlj_setjmp:
596 case ARM::t2Int_eh_sjlj_setjmp:
597 case ARM::t2Int_eh_sjlj_setjmp_nofp:
605 case ARM::t2TBH_JT: {
606 // These are jumptable branches, i.e. a branch followed by an inlined
607 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
608 // entry is one byte; TBH two byte each.
609 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
610 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
611 unsigned NumOps = MCID.getNumOperands();
612 MachineOperand JTOP =
613 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
614 unsigned JTI = JTOP.getIndex();
615 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
617 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
618 assert(JTI < JT.size());
619 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
620 // 4 aligned. The assembler / linker may add 2 byte padding just before
621 // the JT entries. The size does not include this padding; the
622 // constant islands pass does separate bookkeeping for it.
623 // FIXME: If we know the size of the function is less than (1 << 16) *2
624 // bytes, we can use 16-bit entries instead. Then there won't be an
626 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
627 unsigned NumEntries = getNumJTEntries(JT, JTI);
628 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
629 // Make sure the instruction that follows TBB is 2-byte aligned.
630 // FIXME: Constant island pass should insert an "ALIGN" instruction
633 return NumEntries * EntrySize + InstSize;
636 // Otherwise, pseudo-instruction sizes are zero.
641 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
643 MachineBasicBlock::const_instr_iterator I = MI;
644 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
645 while (++I != E && I->isInsideBundle()) {
646 assert(!I->isBundle() && "No nested bundle!");
647 Size += GetInstSizeInBytes(&*I);
652 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
653 MachineBasicBlock::iterator I, DebugLoc DL,
654 unsigned DestReg, unsigned SrcReg,
655 bool KillSrc) const {
656 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
657 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
659 if (GPRDest && GPRSrc) {
660 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
661 .addReg(SrcReg, getKillRegState(KillSrc))));
665 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
666 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
669 if (SPRDest && SPRSrc)
671 else if (GPRDest && SPRSrc)
673 else if (SPRDest && GPRSrc)
675 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
677 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 if (Opc == ARM::VORRq)
684 MIB.addReg(SrcReg, getKillRegState(KillSrc));
689 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
690 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
691 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
692 const TargetRegisterInfo *TRI = &getRegisterInfo();
693 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
694 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
695 ARM::qsub_1 : ARM::qsub_3;
696 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
697 unsigned Dst = TRI->getSubReg(DestReg, i);
698 unsigned Src = TRI->getSubReg(SrcReg, i);
699 MachineInstrBuilder Mov =
700 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
701 .addReg(Dst, RegState::Define)
702 .addReg(Src, getKillRegState(KillSrc))
703 .addReg(Src, getKillRegState(KillSrc)));
704 if (i == EndSubReg) {
705 Mov->addRegisterDefined(DestReg, TRI);
707 Mov->addRegisterKilled(SrcReg, TRI);
712 llvm_unreachable("Impossible reg-to-reg copy");
716 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
717 unsigned Reg, unsigned SubIdx, unsigned State,
718 const TargetRegisterInfo *TRI) {
720 return MIB.addReg(Reg, State);
722 if (TargetRegisterInfo::isPhysicalRegister(Reg))
723 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
724 return MIB.addReg(Reg, State, SubIdx);
727 void ARMBaseInstrInfo::
728 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
729 unsigned SrcReg, bool isKill, int FI,
730 const TargetRegisterClass *RC,
731 const TargetRegisterInfo *TRI) const {
733 if (I != MBB.end()) DL = I->getDebugLoc();
734 MachineFunction &MF = *MBB.getParent();
735 MachineFrameInfo &MFI = *MF.getFrameInfo();
736 unsigned Align = MFI.getObjectAlignment(FI);
738 MachineMemOperand *MMO =
739 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
740 MachineMemOperand::MOStore,
741 MFI.getObjectSize(FI),
744 switch (RC->getSize()) {
746 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
747 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
748 .addReg(SrcReg, getKillRegState(isKill))
749 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
750 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
751 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
752 .addReg(SrcReg, getKillRegState(isKill))
753 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
755 llvm_unreachable("Unknown reg class!");
758 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
759 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
760 .addReg(SrcReg, getKillRegState(isKill))
761 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
763 llvm_unreachable("Unknown reg class!");
766 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
767 // Use aligned spills if the stack can be realigned.
768 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
769 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
770 .addFrameIndex(FI).addImm(16)
771 .addReg(SrcReg, getKillRegState(isKill))
772 .addMemOperand(MMO));
774 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
775 .addReg(SrcReg, getKillRegState(isKill))
777 .addMemOperand(MMO));
780 llvm_unreachable("Unknown reg class!");
783 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
784 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
785 // FIXME: It's possible to only store part of the QQ register if the
786 // spilled def has a sub-register index.
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
788 .addFrameIndex(FI).addImm(16)
789 .addReg(SrcReg, getKillRegState(isKill))
790 .addMemOperand(MMO));
792 MachineInstrBuilder MIB =
793 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
796 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
797 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
798 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
799 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
802 llvm_unreachable("Unknown reg class!");
805 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
806 MachineInstrBuilder MIB =
807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
810 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
814 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
815 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
816 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
817 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
819 llvm_unreachable("Unknown reg class!");
822 llvm_unreachable("Unknown reg class!");
827 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
828 int &FrameIndex) const {
829 switch (MI->getOpcode()) {
832 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
833 if (MI->getOperand(1).isFI() &&
834 MI->getOperand(2).isReg() &&
835 MI->getOperand(3).isImm() &&
836 MI->getOperand(2).getReg() == 0 &&
837 MI->getOperand(3).getImm() == 0) {
838 FrameIndex = MI->getOperand(1).getIndex();
839 return MI->getOperand(0).getReg();
847 if (MI->getOperand(1).isFI() &&
848 MI->getOperand(2).isImm() &&
849 MI->getOperand(2).getImm() == 0) {
850 FrameIndex = MI->getOperand(1).getIndex();
851 return MI->getOperand(0).getReg();
854 case ARM::VST1q64Pseudo:
855 if (MI->getOperand(0).isFI() &&
856 MI->getOperand(2).getSubReg() == 0) {
857 FrameIndex = MI->getOperand(0).getIndex();
858 return MI->getOperand(2).getReg();
862 if (MI->getOperand(1).isFI() &&
863 MI->getOperand(0).getSubReg() == 0) {
864 FrameIndex = MI->getOperand(1).getIndex();
865 return MI->getOperand(0).getReg();
873 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
874 int &FrameIndex) const {
875 const MachineMemOperand *Dummy;
876 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
879 void ARMBaseInstrInfo::
880 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
881 unsigned DestReg, int FI,
882 const TargetRegisterClass *RC,
883 const TargetRegisterInfo *TRI) const {
885 if (I != MBB.end()) DL = I->getDebugLoc();
886 MachineFunction &MF = *MBB.getParent();
887 MachineFrameInfo &MFI = *MF.getFrameInfo();
888 unsigned Align = MFI.getObjectAlignment(FI);
889 MachineMemOperand *MMO =
890 MF.getMachineMemOperand(
891 MachinePointerInfo::getFixedStack(FI),
892 MachineMemOperand::MOLoad,
893 MFI.getObjectSize(FI),
896 switch (RC->getSize()) {
898 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
899 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
900 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
902 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
903 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
904 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
906 llvm_unreachable("Unknown reg class!");
909 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
910 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
911 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
913 llvm_unreachable("Unknown reg class!");
916 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
917 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
918 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
919 .addFrameIndex(FI).addImm(16)
920 .addMemOperand(MMO));
922 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
924 .addMemOperand(MMO));
927 llvm_unreachable("Unknown reg class!");
930 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
931 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
932 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
933 .addFrameIndex(FI).addImm(16)
934 .addMemOperand(MMO));
936 MachineInstrBuilder MIB =
937 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
940 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
941 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
942 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
943 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
944 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
947 llvm_unreachable("Unknown reg class!");
950 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
951 MachineInstrBuilder MIB =
952 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
955 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
956 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
957 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
958 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
959 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
960 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
961 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
962 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
963 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
965 llvm_unreachable("Unknown reg class!");
968 llvm_unreachable("Unknown regclass!");
973 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
974 int &FrameIndex) const {
975 switch (MI->getOpcode()) {
978 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
979 if (MI->getOperand(1).isFI() &&
980 MI->getOperand(2).isReg() &&
981 MI->getOperand(3).isImm() &&
982 MI->getOperand(2).getReg() == 0 &&
983 MI->getOperand(3).getImm() == 0) {
984 FrameIndex = MI->getOperand(1).getIndex();
985 return MI->getOperand(0).getReg();
993 if (MI->getOperand(1).isFI() &&
994 MI->getOperand(2).isImm() &&
995 MI->getOperand(2).getImm() == 0) {
996 FrameIndex = MI->getOperand(1).getIndex();
997 return MI->getOperand(0).getReg();
1000 case ARM::VLD1q64Pseudo:
1001 if (MI->getOperand(1).isFI() &&
1002 MI->getOperand(0).getSubReg() == 0) {
1003 FrameIndex = MI->getOperand(1).getIndex();
1004 return MI->getOperand(0).getReg();
1008 if (MI->getOperand(1).isFI() &&
1009 MI->getOperand(0).getSubReg() == 0) {
1010 FrameIndex = MI->getOperand(1).getIndex();
1011 return MI->getOperand(0).getReg();
1019 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1020 int &FrameIndex) const {
1021 const MachineMemOperand *Dummy;
1022 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1025 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1026 // This hook gets to expand COPY instructions before they become
1027 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1028 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1029 // changed into a VORR that can go down the NEON pipeline.
1030 if (!WidenVMOVS || !MI->isCopy())
1033 // Look for a copy between even S-registers. That is where we keep floats
1034 // when using NEON v2f32 instructions for f32 arithmetic.
1035 unsigned DstRegS = MI->getOperand(0).getReg();
1036 unsigned SrcRegS = MI->getOperand(1).getReg();
1037 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1040 const TargetRegisterInfo *TRI = &getRegisterInfo();
1041 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1043 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1045 if (!DstRegD || !SrcRegD)
1048 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1049 // legal if the COPY already defines the full DstRegD, and it isn't a
1050 // sub-register insertion.
1051 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1054 // A dead copy shouldn't show up here, but reject it just in case.
1055 if (MI->getOperand(0).isDead())
1058 // All clear, widen the COPY.
1059 DEBUG(dbgs() << "widening: " << *MI);
1061 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1062 // or some other super-register.
1063 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1064 if (ImpDefIdx != -1)
1065 MI->RemoveOperand(ImpDefIdx);
1067 // Change the opcode and operands.
1068 MI->setDesc(get(ARM::VMOVD));
1069 MI->getOperand(0).setReg(DstRegD);
1070 MI->getOperand(1).setReg(SrcRegD);
1071 AddDefaultPred(MachineInstrBuilder(MI));
1073 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1074 // register scavenger and machine verifier, so we need to indicate that we
1075 // are reading an undefined value from SrcRegD, but a proper value from
1077 MI->getOperand(1).setIsUndef();
1078 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1080 // SrcRegD may actually contain an unrelated value in the ssub_1
1081 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1082 if (MI->getOperand(1).isKill()) {
1083 MI->getOperand(1).setIsKill(false);
1084 MI->addRegisterKilled(SrcRegS, TRI, true);
1087 DEBUG(dbgs() << "replaced by: " << *MI);
1092 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1093 int FrameIx, uint64_t Offset,
1094 const MDNode *MDPtr,
1095 DebugLoc DL) const {
1096 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1097 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1101 /// Create a copy of a const pool value. Update CPI to the new index and return
1103 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1104 MachineConstantPool *MCP = MF.getConstantPool();
1105 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1107 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1108 assert(MCPE.isMachineConstantPoolEntry() &&
1109 "Expecting a machine constantpool entry!");
1110 ARMConstantPoolValue *ACPV =
1111 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1113 unsigned PCLabelId = AFI->createPICLabelUId();
1114 ARMConstantPoolValue *NewCPV = 0;
1115 // FIXME: The below assumes PIC relocation model and that the function
1116 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1117 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1118 // instructions, so that's probably OK, but is PIC always correct when
1120 if (ACPV->isGlobalValue())
1121 NewCPV = ARMConstantPoolConstant::
1122 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1124 else if (ACPV->isExtSymbol())
1125 NewCPV = ARMConstantPoolSymbol::
1126 Create(MF.getFunction()->getContext(),
1127 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1128 else if (ACPV->isBlockAddress())
1129 NewCPV = ARMConstantPoolConstant::
1130 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1131 ARMCP::CPBlockAddress, 4);
1132 else if (ACPV->isLSDA())
1133 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1135 else if (ACPV->isMachineBasicBlock())
1136 NewCPV = ARMConstantPoolMBB::
1137 Create(MF.getFunction()->getContext(),
1138 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1140 llvm_unreachable("Unexpected ARM constantpool value type!!");
1141 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1145 void ARMBaseInstrInfo::
1146 reMaterialize(MachineBasicBlock &MBB,
1147 MachineBasicBlock::iterator I,
1148 unsigned DestReg, unsigned SubIdx,
1149 const MachineInstr *Orig,
1150 const TargetRegisterInfo &TRI) const {
1151 unsigned Opcode = Orig->getOpcode();
1154 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1155 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1159 case ARM::tLDRpci_pic:
1160 case ARM::t2LDRpci_pic: {
1161 MachineFunction &MF = *MBB.getParent();
1162 unsigned CPI = Orig->getOperand(1).getIndex();
1163 unsigned PCLabelId = duplicateCPV(MF, CPI);
1164 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1166 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1167 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1174 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1175 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1176 switch(Orig->getOpcode()) {
1177 case ARM::tLDRpci_pic:
1178 case ARM::t2LDRpci_pic: {
1179 unsigned CPI = Orig->getOperand(1).getIndex();
1180 unsigned PCLabelId = duplicateCPV(MF, CPI);
1181 Orig->getOperand(1).setIndex(CPI);
1182 Orig->getOperand(2).setImm(PCLabelId);
1189 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1190 const MachineInstr *MI1,
1191 const MachineRegisterInfo *MRI) const {
1192 int Opcode = MI0->getOpcode();
1193 if (Opcode == ARM::t2LDRpci ||
1194 Opcode == ARM::t2LDRpci_pic ||
1195 Opcode == ARM::tLDRpci ||
1196 Opcode == ARM::tLDRpci_pic ||
1197 Opcode == ARM::MOV_ga_dyn ||
1198 Opcode == ARM::MOV_ga_pcrel ||
1199 Opcode == ARM::MOV_ga_pcrel_ldr ||
1200 Opcode == ARM::t2MOV_ga_dyn ||
1201 Opcode == ARM::t2MOV_ga_pcrel) {
1202 if (MI1->getOpcode() != Opcode)
1204 if (MI0->getNumOperands() != MI1->getNumOperands())
1207 const MachineOperand &MO0 = MI0->getOperand(1);
1208 const MachineOperand &MO1 = MI1->getOperand(1);
1209 if (MO0.getOffset() != MO1.getOffset())
1212 if (Opcode == ARM::MOV_ga_dyn ||
1213 Opcode == ARM::MOV_ga_pcrel ||
1214 Opcode == ARM::MOV_ga_pcrel_ldr ||
1215 Opcode == ARM::t2MOV_ga_dyn ||
1216 Opcode == ARM::t2MOV_ga_pcrel)
1217 // Ignore the PC labels.
1218 return MO0.getGlobal() == MO1.getGlobal();
1220 const MachineFunction *MF = MI0->getParent()->getParent();
1221 const MachineConstantPool *MCP = MF->getConstantPool();
1222 int CPI0 = MO0.getIndex();
1223 int CPI1 = MO1.getIndex();
1224 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1225 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1226 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1227 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1228 if (isARMCP0 && isARMCP1) {
1229 ARMConstantPoolValue *ACPV0 =
1230 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1231 ARMConstantPoolValue *ACPV1 =
1232 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1233 return ACPV0->hasSameValue(ACPV1);
1234 } else if (!isARMCP0 && !isARMCP1) {
1235 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1238 } else if (Opcode == ARM::PICLDR) {
1239 if (MI1->getOpcode() != Opcode)
1241 if (MI0->getNumOperands() != MI1->getNumOperands())
1244 unsigned Addr0 = MI0->getOperand(1).getReg();
1245 unsigned Addr1 = MI1->getOperand(1).getReg();
1246 if (Addr0 != Addr1) {
1248 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1249 !TargetRegisterInfo::isVirtualRegister(Addr1))
1252 // This assumes SSA form.
1253 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1254 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1255 // Check if the loaded value, e.g. a constantpool of a global address, are
1257 if (!produceSameValue(Def0, Def1, MRI))
1261 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1262 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1263 const MachineOperand &MO0 = MI0->getOperand(i);
1264 const MachineOperand &MO1 = MI1->getOperand(i);
1265 if (!MO0.isIdenticalTo(MO1))
1271 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1274 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1275 /// determine if two loads are loading from the same base address. It should
1276 /// only return true if the base pointers are the same and the only differences
1277 /// between the two addresses is the offset. It also returns the offsets by
1279 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1281 int64_t &Offset2) const {
1282 // Don't worry about Thumb: just ARM and Thumb2.
1283 if (Subtarget.isThumb1Only()) return false;
1285 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1288 switch (Load1->getMachineOpcode()) {
1301 case ARM::t2LDRSHi8:
1303 case ARM::t2LDRSHi12:
1307 switch (Load2->getMachineOpcode()) {
1320 case ARM::t2LDRSHi8:
1322 case ARM::t2LDRSHi12:
1326 // Check if base addresses and chain operands match.
1327 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1328 Load1->getOperand(4) != Load2->getOperand(4))
1331 // Index should be Reg0.
1332 if (Load1->getOperand(3) != Load2->getOperand(3))
1335 // Determine the offsets.
1336 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1337 isa<ConstantSDNode>(Load2->getOperand(1))) {
1338 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1339 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1346 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1347 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1348 /// be scheduled togther. On some targets if two loads are loading from
1349 /// addresses in the same cache line, it's better if they are scheduled
1350 /// together. This function takes two integers that represent the load offsets
1351 /// from the common base address. It returns true if it decides it's desirable
1352 /// to schedule the two loads together. "NumLoads" is the number of loads that
1353 /// have already been scheduled after Load1.
1354 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1355 int64_t Offset1, int64_t Offset2,
1356 unsigned NumLoads) const {
1357 // Don't worry about Thumb: just ARM and Thumb2.
1358 if (Subtarget.isThumb1Only()) return false;
1360 assert(Offset2 > Offset1);
1362 if ((Offset2 - Offset1) / 8 > 64)
1365 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1366 return false; // FIXME: overly conservative?
1368 // Four loads in a row should be sufficient.
1375 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1376 const MachineBasicBlock *MBB,
1377 const MachineFunction &MF) const {
1378 // Debug info is never a scheduling boundary. It's necessary to be explicit
1379 // due to the special treatment of IT instructions below, otherwise a
1380 // dbg_value followed by an IT will result in the IT instruction being
1381 // considered a scheduling hazard, which is wrong. It should be the actual
1382 // instruction preceding the dbg_value instruction(s), just like it is
1383 // when debug info is not present.
1384 if (MI->isDebugValue())
1387 // Terminators and labels can't be scheduled around.
1388 if (MI->isTerminator() || MI->isLabel())
1391 // Treat the start of the IT block as a scheduling boundary, but schedule
1392 // t2IT along with all instructions following it.
1393 // FIXME: This is a big hammer. But the alternative is to add all potential
1394 // true and anti dependencies to IT block instructions as implicit operands
1395 // to the t2IT instruction. The added compile time and complexity does not
1397 MachineBasicBlock::const_iterator I = MI;
1398 // Make sure to skip any dbg_value instructions
1399 while (++I != MBB->end() && I->isDebugValue())
1401 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1404 // Don't attempt to schedule around any instruction that defines
1405 // a stack-oriented pointer, as it's unlikely to be profitable. This
1406 // saves compile time, because it doesn't require every single
1407 // stack slot reference to depend on the instruction that does the
1409 if (MI->definesRegister(ARM::SP))
1415 bool ARMBaseInstrInfo::
1416 isProfitableToIfCvt(MachineBasicBlock &MBB,
1417 unsigned NumCycles, unsigned ExtraPredCycles,
1418 const BranchProbability &Probability) const {
1422 // Attempt to estimate the relative costs of predication versus branching.
1423 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1424 UnpredCost /= Probability.getDenominator();
1425 UnpredCost += 1; // The branch itself
1426 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1428 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1431 bool ARMBaseInstrInfo::
1432 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1433 unsigned TCycles, unsigned TExtra,
1434 MachineBasicBlock &FMBB,
1435 unsigned FCycles, unsigned FExtra,
1436 const BranchProbability &Probability) const {
1437 if (!TCycles || !FCycles)
1440 // Attempt to estimate the relative costs of predication versus branching.
1441 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1442 TUnpredCost /= Probability.getDenominator();
1444 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1445 unsigned FUnpredCost = Comp * FCycles;
1446 FUnpredCost /= Probability.getDenominator();
1448 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1449 UnpredCost += 1; // The branch itself
1450 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1452 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1455 /// getInstrPredicate - If instruction is predicated, returns its predicate
1456 /// condition, otherwise returns AL. It also returns the condition code
1457 /// register by reference.
1459 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1460 int PIdx = MI->findFirstPredOperandIdx();
1466 PredReg = MI->getOperand(PIdx+1).getReg();
1467 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1471 int llvm::getMatchingCondBranchOpcode(int Opc) {
1476 if (Opc == ARM::t2B)
1479 llvm_unreachable("Unknown unconditional branch opcode!");
1483 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1484 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1487 /// This will go away once we can teach tblgen how to set the optional CPSR def
1489 struct AddSubFlagsOpcodePair {
1491 unsigned MachineOpc;
1494 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1495 {ARM::ADDSri, ARM::ADDri},
1496 {ARM::ADDSrr, ARM::ADDrr},
1497 {ARM::ADDSrsi, ARM::ADDrsi},
1498 {ARM::ADDSrsr, ARM::ADDrsr},
1500 {ARM::SUBSri, ARM::SUBri},
1501 {ARM::SUBSrr, ARM::SUBrr},
1502 {ARM::SUBSrsi, ARM::SUBrsi},
1503 {ARM::SUBSrsr, ARM::SUBrsr},
1505 {ARM::RSBSri, ARM::RSBri},
1506 {ARM::RSBSrsi, ARM::RSBrsi},
1507 {ARM::RSBSrsr, ARM::RSBrsr},
1509 {ARM::t2ADDSri, ARM::t2ADDri},
1510 {ARM::t2ADDSrr, ARM::t2ADDrr},
1511 {ARM::t2ADDSrs, ARM::t2ADDrs},
1513 {ARM::t2SUBSri, ARM::t2SUBri},
1514 {ARM::t2SUBSrr, ARM::t2SUBrr},
1515 {ARM::t2SUBSrs, ARM::t2SUBrs},
1517 {ARM::t2RSBSri, ARM::t2RSBri},
1518 {ARM::t2RSBSrs, ARM::t2RSBrs},
1521 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1522 static const int NPairs =
1523 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1524 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1525 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1526 if (OldOpc == OpcPair->PseudoOpc) {
1527 return OpcPair->MachineOpc;
1533 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1534 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1535 unsigned DestReg, unsigned BaseReg, int NumBytes,
1536 ARMCC::CondCodes Pred, unsigned PredReg,
1537 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1538 bool isSub = NumBytes < 0;
1539 if (isSub) NumBytes = -NumBytes;
1542 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1543 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1544 assert(ThisVal && "Didn't extract field correctly");
1546 // We will handle these bits from offset, clear them.
1547 NumBytes &= ~ThisVal;
1549 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1551 // Build the new ADD / SUB.
1552 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1553 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1554 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1555 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1556 .setMIFlags(MIFlags);
1561 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1562 unsigned FrameReg, int &Offset,
1563 const ARMBaseInstrInfo &TII) {
1564 unsigned Opcode = MI.getOpcode();
1565 const MCInstrDesc &Desc = MI.getDesc();
1566 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1569 // Memory operands in inline assembly always use AddrMode2.
1570 if (Opcode == ARM::INLINEASM)
1571 AddrMode = ARMII::AddrMode2;
1573 if (Opcode == ARM::ADDri) {
1574 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1576 // Turn it into a move.
1577 MI.setDesc(TII.get(ARM::MOVr));
1578 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1579 MI.RemoveOperand(FrameRegIdx+1);
1582 } else if (Offset < 0) {
1585 MI.setDesc(TII.get(ARM::SUBri));
1588 // Common case: small offset, fits into instruction.
1589 if (ARM_AM::getSOImmVal(Offset) != -1) {
1590 // Replace the FrameIndex with sp / fp
1591 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1592 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1597 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1599 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1600 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1602 // We will handle these bits from offset, clear them.
1603 Offset &= ~ThisImmVal;
1605 // Get the properly encoded SOImmVal field.
1606 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1607 "Bit extraction didn't work?");
1608 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1610 unsigned ImmIdx = 0;
1612 unsigned NumBits = 0;
1615 case ARMII::AddrMode_i12: {
1616 ImmIdx = FrameRegIdx + 1;
1617 InstrOffs = MI.getOperand(ImmIdx).getImm();
1621 case ARMII::AddrMode2: {
1622 ImmIdx = FrameRegIdx+2;
1623 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1624 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1629 case ARMII::AddrMode3: {
1630 ImmIdx = FrameRegIdx+2;
1631 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1632 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1637 case ARMII::AddrMode4:
1638 case ARMII::AddrMode6:
1639 // Can't fold any offset even if it's zero.
1641 case ARMII::AddrMode5: {
1642 ImmIdx = FrameRegIdx+1;
1643 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1644 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1651 llvm_unreachable("Unsupported addressing mode!");
1654 Offset += InstrOffs * Scale;
1655 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1661 // Attempt to fold address comp. if opcode has offset bits
1663 // Common case: small offset, fits into instruction.
1664 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1665 int ImmedOffset = Offset / Scale;
1666 unsigned Mask = (1 << NumBits) - 1;
1667 if ((unsigned)Offset <= Mask * Scale) {
1668 // Replace the FrameIndex with sp
1669 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1670 // FIXME: When addrmode2 goes away, this will simplify (like the
1671 // T2 version), as the LDR.i12 versions don't need the encoding
1672 // tricks for the offset value.
1674 if (AddrMode == ARMII::AddrMode_i12)
1675 ImmedOffset = -ImmedOffset;
1677 ImmedOffset |= 1 << NumBits;
1679 ImmOp.ChangeToImmediate(ImmedOffset);
1684 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1685 ImmedOffset = ImmedOffset & Mask;
1687 if (AddrMode == ARMII::AddrMode_i12)
1688 ImmedOffset = -ImmedOffset;
1690 ImmedOffset |= 1 << NumBits;
1692 ImmOp.ChangeToImmediate(ImmedOffset);
1693 Offset &= ~(Mask*Scale);
1697 Offset = (isSub) ? -Offset : Offset;
1701 bool ARMBaseInstrInfo::
1702 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1703 int &CmpValue) const {
1704 switch (MI->getOpcode()) {
1708 SrcReg = MI->getOperand(0).getReg();
1710 CmpValue = MI->getOperand(1).getImm();
1714 SrcReg = MI->getOperand(0).getReg();
1715 CmpMask = MI->getOperand(1).getImm();
1723 /// isSuitableForMask - Identify a suitable 'and' instruction that
1724 /// operates on the given source register and applies the same mask
1725 /// as a 'tst' instruction. Provide a limited look-through for copies.
1726 /// When successful, MI will hold the found instruction.
1727 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1728 int CmpMask, bool CommonUse) {
1729 switch (MI->getOpcode()) {
1732 if (CmpMask != MI->getOperand(2).getImm())
1734 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1738 // Walk down one instruction which is potentially an 'and'.
1739 const MachineInstr &Copy = *MI;
1740 MachineBasicBlock::iterator AND(
1741 llvm::next(MachineBasicBlock::iterator(MI)));
1742 if (AND == MI->getParent()->end()) return false;
1744 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1752 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1753 /// comparison into one that sets the zero bit in the flags register.
1754 bool ARMBaseInstrInfo::
1755 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1756 int CmpValue, const MachineRegisterInfo *MRI) const {
1760 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1761 if (llvm::next(DI) != MRI->def_end())
1762 // Only support one definition.
1765 MachineInstr *MI = &*DI;
1767 // Masked compares sometimes use the same register as the corresponding 'and'.
1768 if (CmpMask != ~0) {
1769 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1771 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1772 UE = MRI->use_end(); UI != UE; ++UI) {
1773 if (UI->getParent() != CmpInstr->getParent()) continue;
1774 MachineInstr *PotentialAND = &*UI;
1775 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1780 if (!MI) return false;
1784 // Conservatively refuse to convert an instruction which isn't in the same BB
1785 // as the comparison.
1786 if (MI->getParent() != CmpInstr->getParent())
1789 // Check that CPSR isn't set between the comparison instruction and the one we
1791 MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin();
1793 // Early exit if CmpInstr is at the beginning of the BB.
1794 if (I == B) return false;
1797 for (; I != E; --I) {
1798 const MachineInstr &Instr = *I;
1800 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1801 const MachineOperand &MO = Instr.getOperand(IO);
1802 if (!MO.isReg()) continue;
1804 // This instruction modifies or uses CPSR after the one we want to
1805 // change. We can't do this transformation.
1806 if (MO.getReg() == ARM::CPSR)
1811 // The 'and' is below the comparison instruction.
1815 // Set the "zero" bit in CPSR.
1816 switch (MI->getOpcode()) {
1850 case ARM::t2EORri: {
1851 // Scan forward for the use of CPSR, if it's a conditional code requires
1852 // checking of V bit, then this is not safe to do. If we can't find the
1853 // CPSR use (i.e. used in another block), then it's not safe to perform
1854 // the optimization.
1855 bool isSafe = false;
1857 E = MI->getParent()->end();
1858 while (!isSafe && ++I != E) {
1859 const MachineInstr &Instr = *I;
1860 for (unsigned IO = 0, EO = Instr.getNumOperands();
1861 !isSafe && IO != EO; ++IO) {
1862 const MachineOperand &MO = Instr.getOperand(IO);
1863 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1869 // Condition code is after the operand before CPSR.
1870 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1889 // Toggle the optional operand to CPSR.
1890 MI->getOperand(5).setReg(ARM::CPSR);
1891 MI->getOperand(5).setIsDef(true);
1892 CmpInstr->eraseFromParent();
1900 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1901 MachineInstr *DefMI, unsigned Reg,
1902 MachineRegisterInfo *MRI) const {
1903 // Fold large immediates into add, sub, or, xor.
1904 unsigned DefOpc = DefMI->getOpcode();
1905 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1907 if (!DefMI->getOperand(1).isImm())
1908 // Could be t2MOVi32imm <ga:xx>
1911 if (!MRI->hasOneNonDBGUse(Reg))
1914 unsigned UseOpc = UseMI->getOpcode();
1915 unsigned NewUseOpc = 0;
1916 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1917 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1918 bool Commute = false;
1920 default: return false;
1928 case ARM::t2EORrr: {
1929 Commute = UseMI->getOperand(2).getReg() != Reg;
1936 NewUseOpc = ARM::SUBri;
1942 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1944 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1945 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1948 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1949 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1950 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1954 case ARM::t2SUBrr: {
1958 NewUseOpc = ARM::t2SUBri;
1963 case ARM::t2EORrr: {
1964 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1966 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1967 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1970 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1971 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1972 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1980 unsigned OpIdx = Commute ? 2 : 1;
1981 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1982 bool isKill = UseMI->getOperand(OpIdx).isKill();
1983 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1984 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1985 UseMI, UseMI->getDebugLoc(),
1986 get(NewUseOpc), NewReg)
1987 .addReg(Reg1, getKillRegState(isKill))
1988 .addImm(SOImmValV1)));
1989 UseMI->setDesc(get(NewUseOpc));
1990 UseMI->getOperand(1).setReg(NewReg);
1991 UseMI->getOperand(1).setIsKill();
1992 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1993 DefMI->eraseFromParent();
1998 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1999 const MachineInstr *MI) const {
2000 if (!ItinData || ItinData->isEmpty())
2003 const MCInstrDesc &Desc = MI->getDesc();
2004 unsigned Class = Desc.getSchedClass();
2005 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2009 unsigned Opc = MI->getOpcode();
2012 llvm_unreachable("Unexpected multi-uops instruction!");
2017 // The number of uOps for load / store multiple are determined by the number
2020 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2021 // same cycle. The scheduling for the first load / store must be done
2022 // separately by assuming the the address is not 64-bit aligned.
2024 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2025 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2026 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2028 case ARM::VLDMDIA_UPD:
2029 case ARM::VLDMDDB_UPD:
2031 case ARM::VLDMSIA_UPD:
2032 case ARM::VLDMSDB_UPD:
2034 case ARM::VSTMDIA_UPD:
2035 case ARM::VSTMDDB_UPD:
2037 case ARM::VSTMSIA_UPD:
2038 case ARM::VSTMSDB_UPD: {
2039 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2040 return (NumRegs / 2) + (NumRegs % 2) + 1;
2043 case ARM::LDMIA_RET:
2048 case ARM::LDMIA_UPD:
2049 case ARM::LDMDA_UPD:
2050 case ARM::LDMDB_UPD:
2051 case ARM::LDMIB_UPD:
2056 case ARM::STMIA_UPD:
2057 case ARM::STMDA_UPD:
2058 case ARM::STMDB_UPD:
2059 case ARM::STMIB_UPD:
2061 case ARM::tLDMIA_UPD:
2062 case ARM::tSTMIA_UPD:
2066 case ARM::t2LDMIA_RET:
2069 case ARM::t2LDMIA_UPD:
2070 case ARM::t2LDMDB_UPD:
2073 case ARM::t2STMIA_UPD:
2074 case ARM::t2STMDB_UPD: {
2075 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2076 if (Subtarget.isCortexA8()) {
2079 // 4 registers would be issued: 2, 2.
2080 // 5 registers would be issued: 2, 2, 1.
2081 UOps = (NumRegs / 2);
2085 } else if (Subtarget.isCortexA9()) {
2086 UOps = (NumRegs / 2);
2087 // If there are odd number of registers or if it's not 64-bit aligned,
2088 // then it takes an extra AGU (Address Generation Unit) cycle.
2089 if ((NumRegs % 2) ||
2090 !MI->hasOneMemOperand() ||
2091 (*MI->memoperands_begin())->getAlignment() < 8)
2095 // Assume the worst.
2103 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2104 const MCInstrDesc &DefMCID,
2106 unsigned DefIdx, unsigned DefAlign) const {
2107 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2109 // Def is the address writeback.
2110 return ItinData->getOperandCycle(DefClass, DefIdx);
2113 if (Subtarget.isCortexA8()) {
2114 // (regno / 2) + (regno % 2) + 1
2115 DefCycle = RegNo / 2 + 1;
2118 } else if (Subtarget.isCortexA9()) {
2120 bool isSLoad = false;
2122 switch (DefMCID.getOpcode()) {
2125 case ARM::VLDMSIA_UPD:
2126 case ARM::VLDMSDB_UPD:
2131 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2132 // then it takes an extra cycle.
2133 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2136 // Assume the worst.
2137 DefCycle = RegNo + 2;
2144 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2145 const MCInstrDesc &DefMCID,
2147 unsigned DefIdx, unsigned DefAlign) const {
2148 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2150 // Def is the address writeback.
2151 return ItinData->getOperandCycle(DefClass, DefIdx);
2154 if (Subtarget.isCortexA8()) {
2155 // 4 registers would be issued: 1, 2, 1.
2156 // 5 registers would be issued: 1, 2, 2.
2157 DefCycle = RegNo / 2;
2160 // Result latency is issue cycle + 2: E2.
2162 } else if (Subtarget.isCortexA9()) {
2163 DefCycle = (RegNo / 2);
2164 // If there are odd number of registers or if it's not 64-bit aligned,
2165 // then it takes an extra AGU (Address Generation Unit) cycle.
2166 if ((RegNo % 2) || DefAlign < 8)
2168 // Result latency is AGU cycles + 2.
2171 // Assume the worst.
2172 DefCycle = RegNo + 2;
2179 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2180 const MCInstrDesc &UseMCID,
2182 unsigned UseIdx, unsigned UseAlign) const {
2183 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2185 return ItinData->getOperandCycle(UseClass, UseIdx);
2188 if (Subtarget.isCortexA8()) {
2189 // (regno / 2) + (regno % 2) + 1
2190 UseCycle = RegNo / 2 + 1;
2193 } else if (Subtarget.isCortexA9()) {
2195 bool isSStore = false;
2197 switch (UseMCID.getOpcode()) {
2200 case ARM::VSTMSIA_UPD:
2201 case ARM::VSTMSDB_UPD:
2206 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2207 // then it takes an extra cycle.
2208 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2211 // Assume the worst.
2212 UseCycle = RegNo + 2;
2219 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2220 const MCInstrDesc &UseMCID,
2222 unsigned UseIdx, unsigned UseAlign) const {
2223 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2225 return ItinData->getOperandCycle(UseClass, UseIdx);
2228 if (Subtarget.isCortexA8()) {
2229 UseCycle = RegNo / 2;
2234 } else if (Subtarget.isCortexA9()) {
2235 UseCycle = (RegNo / 2);
2236 // If there are odd number of registers or if it's not 64-bit aligned,
2237 // then it takes an extra AGU (Address Generation Unit) cycle.
2238 if ((RegNo % 2) || UseAlign < 8)
2241 // Assume the worst.
2248 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2249 const MCInstrDesc &DefMCID,
2250 unsigned DefIdx, unsigned DefAlign,
2251 const MCInstrDesc &UseMCID,
2252 unsigned UseIdx, unsigned UseAlign) const {
2253 unsigned DefClass = DefMCID.getSchedClass();
2254 unsigned UseClass = UseMCID.getSchedClass();
2256 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2257 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2259 // This may be a def / use of a variable_ops instruction, the operand
2260 // latency might be determinable dynamically. Let the target try to
2263 bool LdmBypass = false;
2264 switch (DefMCID.getOpcode()) {
2266 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2270 case ARM::VLDMDIA_UPD:
2271 case ARM::VLDMDDB_UPD:
2273 case ARM::VLDMSIA_UPD:
2274 case ARM::VLDMSDB_UPD:
2275 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2278 case ARM::LDMIA_RET:
2283 case ARM::LDMIA_UPD:
2284 case ARM::LDMDA_UPD:
2285 case ARM::LDMDB_UPD:
2286 case ARM::LDMIB_UPD:
2288 case ARM::tLDMIA_UPD:
2290 case ARM::t2LDMIA_RET:
2293 case ARM::t2LDMIA_UPD:
2294 case ARM::t2LDMDB_UPD:
2296 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2301 // We can't seem to determine the result latency of the def, assume it's 2.
2305 switch (UseMCID.getOpcode()) {
2307 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2311 case ARM::VSTMDIA_UPD:
2312 case ARM::VSTMDDB_UPD:
2314 case ARM::VSTMSIA_UPD:
2315 case ARM::VSTMSDB_UPD:
2316 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2323 case ARM::STMIA_UPD:
2324 case ARM::STMDA_UPD:
2325 case ARM::STMDB_UPD:
2326 case ARM::STMIB_UPD:
2327 case ARM::tSTMIA_UPD:
2332 case ARM::t2STMIA_UPD:
2333 case ARM::t2STMDB_UPD:
2334 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2339 // Assume it's read in the first stage.
2342 UseCycle = DefCycle - UseCycle + 1;
2345 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2346 // first def operand.
2347 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2350 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2351 UseClass, UseIdx)) {
2359 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2360 const MachineInstr *MI, unsigned Reg,
2361 unsigned &DefIdx, unsigned &Dist) {
2364 MachineBasicBlock::const_iterator I = MI; ++I;
2365 MachineBasicBlock::const_instr_iterator II =
2366 llvm::prior(I.getInstrIterator());
2367 assert(II->isInsideBundle() && "Empty bundle?");
2370 while (II->isInsideBundle()) {
2371 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2378 assert(Idx != -1 && "Cannot find bundled definition!");
2383 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2384 const MachineInstr *MI, unsigned Reg,
2385 unsigned &UseIdx, unsigned &Dist) {
2388 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2389 assert(II->isInsideBundle() && "Empty bundle?");
2390 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2392 // FIXME: This doesn't properly handle multiple uses.
2394 while (II != E && II->isInsideBundle()) {
2395 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2398 if (II->getOpcode() != ARM::t2IT)
2413 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2414 const MachineInstr *DefMI, unsigned DefIdx,
2415 const MachineInstr *UseMI, unsigned UseIdx) const {
2416 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2417 DefMI->isRegSequence() || DefMI->isImplicitDef())
2420 if (!ItinData || ItinData->isEmpty())
2421 return DefMI->mayLoad() ? 3 : 1;
2423 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2424 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2425 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2426 unsigned Reg = DefMO.getReg();
2427 if (Reg == ARM::CPSR) {
2428 if (DefMI->getOpcode() == ARM::FMSTAT) {
2429 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2430 return Subtarget.isCortexA9() ? 1 : 20;
2433 // CPSR set and branch can be paired in the same cycle.
2434 if (UseMI->isBranch())
2437 // Otherwise it takes the instruction latency (generally one).
2438 int Latency = getInstrLatency(ItinData, DefMI);
2440 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2441 // its uses. Instructions which are otherwise scheduled between them may
2442 // incur a code size penalty (not able to use the CPSR setting 16-bit
2444 if (Latency > 0 && Subtarget.isThumb2()) {
2445 const MachineFunction *MF = DefMI->getParent()->getParent();
2446 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2452 unsigned DefAlign = DefMI->hasOneMemOperand()
2453 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2454 unsigned UseAlign = UseMI->hasOneMemOperand()
2455 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2457 unsigned DefAdj = 0;
2458 if (DefMI->isBundle()) {
2459 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2460 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2461 DefMI->isRegSequence() || DefMI->isImplicitDef())
2463 DefMCID = &DefMI->getDesc();
2465 unsigned UseAdj = 0;
2466 if (UseMI->isBundle()) {
2468 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2469 Reg, NewUseIdx, UseAdj);
2473 UseMCID = &UseMI->getDesc();
2477 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2478 *UseMCID, UseIdx, UseAlign);
2479 int Adj = DefAdj + UseAdj;
2481 Latency -= (int)(DefAdj + UseAdj);
2487 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2488 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2489 // variants are one cycle cheaper.
2490 switch (DefMCID->getOpcode()) {
2494 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2495 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2497 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2504 case ARM::t2LDRSHs: {
2505 // Thumb2 mode: lsl only.
2506 unsigned ShAmt = DefMI->getOperand(3).getImm();
2507 if (ShAmt == 0 || ShAmt == 2)
2514 if (DefAlign < 8 && Subtarget.isCortexA9())
2515 switch (DefMCID->getOpcode()) {
2521 case ARM::VLD1q8wb_fixed:
2522 case ARM::VLD1q16wb_fixed:
2523 case ARM::VLD1q32wb_fixed:
2524 case ARM::VLD1q64wb_fixed:
2525 case ARM::VLD1q8wb_register:
2526 case ARM::VLD1q16wb_register:
2527 case ARM::VLD1q32wb_register:
2528 case ARM::VLD1q64wb_register:
2535 case ARM::VLD2d8wb_fixed:
2536 case ARM::VLD2d16wb_fixed:
2537 case ARM::VLD2d32wb_fixed:
2538 case ARM::VLD2q8wb_fixed:
2539 case ARM::VLD2q16wb_fixed:
2540 case ARM::VLD2q32wb_fixed:
2541 case ARM::VLD2d8wb_register:
2542 case ARM::VLD2d16wb_register:
2543 case ARM::VLD2d32wb_register:
2544 case ARM::VLD2q8wb_register:
2545 case ARM::VLD2q16wb_register:
2546 case ARM::VLD2q32wb_register:
2551 case ARM::VLD3d8_UPD:
2552 case ARM::VLD3d16_UPD:
2553 case ARM::VLD3d32_UPD:
2554 case ARM::VLD1d64Twb_fixed:
2555 case ARM::VLD1d64Twb_register:
2556 case ARM::VLD3q8_UPD:
2557 case ARM::VLD3q16_UPD:
2558 case ARM::VLD3q32_UPD:
2563 case ARM::VLD4d8_UPD:
2564 case ARM::VLD4d16_UPD:
2565 case ARM::VLD4d32_UPD:
2566 case ARM::VLD1d64Qwb_fixed:
2567 case ARM::VLD1d64Qwb_register:
2568 case ARM::VLD4q8_UPD:
2569 case ARM::VLD4q16_UPD:
2570 case ARM::VLD4q32_UPD:
2571 case ARM::VLD1DUPq8:
2572 case ARM::VLD1DUPq16:
2573 case ARM::VLD1DUPq32:
2574 case ARM::VLD1DUPq8wb_fixed:
2575 case ARM::VLD1DUPq16wb_fixed:
2576 case ARM::VLD1DUPq32wb_fixed:
2577 case ARM::VLD1DUPq8wb_register:
2578 case ARM::VLD1DUPq16wb_register:
2579 case ARM::VLD1DUPq32wb_register:
2580 case ARM::VLD2DUPd8:
2581 case ARM::VLD2DUPd16:
2582 case ARM::VLD2DUPd32:
2583 case ARM::VLD2DUPd8wb_fixed:
2584 case ARM::VLD2DUPd16wb_fixed:
2585 case ARM::VLD2DUPd32wb_fixed:
2586 case ARM::VLD2DUPd8wb_register:
2587 case ARM::VLD2DUPd16wb_register:
2588 case ARM::VLD2DUPd32wb_register:
2589 case ARM::VLD4DUPd8:
2590 case ARM::VLD4DUPd16:
2591 case ARM::VLD4DUPd32:
2592 case ARM::VLD4DUPd8_UPD:
2593 case ARM::VLD4DUPd16_UPD:
2594 case ARM::VLD4DUPd32_UPD:
2596 case ARM::VLD1LNd16:
2597 case ARM::VLD1LNd32:
2598 case ARM::VLD1LNd8_UPD:
2599 case ARM::VLD1LNd16_UPD:
2600 case ARM::VLD1LNd32_UPD:
2602 case ARM::VLD2LNd16:
2603 case ARM::VLD2LNd32:
2604 case ARM::VLD2LNq16:
2605 case ARM::VLD2LNq32:
2606 case ARM::VLD2LNd8_UPD:
2607 case ARM::VLD2LNd16_UPD:
2608 case ARM::VLD2LNd32_UPD:
2609 case ARM::VLD2LNq16_UPD:
2610 case ARM::VLD2LNq32_UPD:
2612 case ARM::VLD4LNd16:
2613 case ARM::VLD4LNd32:
2614 case ARM::VLD4LNq16:
2615 case ARM::VLD4LNq32:
2616 case ARM::VLD4LNd8_UPD:
2617 case ARM::VLD4LNd16_UPD:
2618 case ARM::VLD4LNd32_UPD:
2619 case ARM::VLD4LNq16_UPD:
2620 case ARM::VLD4LNq32_UPD:
2621 // If the address is not 64-bit aligned, the latencies of these
2622 // instructions increases by one.
2631 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2632 SDNode *DefNode, unsigned DefIdx,
2633 SDNode *UseNode, unsigned UseIdx) const {
2634 if (!DefNode->isMachineOpcode())
2637 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2639 if (isZeroCost(DefMCID.Opcode))
2642 if (!ItinData || ItinData->isEmpty())
2643 return DefMCID.mayLoad() ? 3 : 1;
2645 if (!UseNode->isMachineOpcode()) {
2646 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2647 if (Subtarget.isCortexA9())
2648 return Latency <= 2 ? 1 : Latency - 1;
2650 return Latency <= 3 ? 1 : Latency - 2;
2653 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2654 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2655 unsigned DefAlign = !DefMN->memoperands_empty()
2656 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2657 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2658 unsigned UseAlign = !UseMN->memoperands_empty()
2659 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2660 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2661 UseMCID, UseIdx, UseAlign);
2664 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2665 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2666 // variants are one cycle cheaper.
2667 switch (DefMCID.getOpcode()) {
2672 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2673 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2675 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2682 case ARM::t2LDRSHs: {
2683 // Thumb2 mode: lsl only.
2685 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2686 if (ShAmt == 0 || ShAmt == 2)
2693 if (DefAlign < 8 && Subtarget.isCortexA9())
2694 switch (DefMCID.getOpcode()) {
2696 case ARM::VLD1q8Pseudo:
2697 case ARM::VLD1q16Pseudo:
2698 case ARM::VLD1q32Pseudo:
2699 case ARM::VLD1q64Pseudo:
2700 case ARM::VLD1q8PseudoWB_register:
2701 case ARM::VLD1q16PseudoWB_register:
2702 case ARM::VLD1q32PseudoWB_register:
2703 case ARM::VLD1q64PseudoWB_register:
2704 case ARM::VLD1q8PseudoWB_fixed:
2705 case ARM::VLD1q16PseudoWB_fixed:
2706 case ARM::VLD1q32PseudoWB_fixed:
2707 case ARM::VLD1q64PseudoWB_fixed:
2708 case ARM::VLD2d8Pseudo:
2709 case ARM::VLD2d16Pseudo:
2710 case ARM::VLD2d32Pseudo:
2711 case ARM::VLD2q8Pseudo:
2712 case ARM::VLD2q16Pseudo:
2713 case ARM::VLD2q32Pseudo:
2714 case ARM::VLD2d8PseudoWB_fixed:
2715 case ARM::VLD2d16PseudoWB_fixed:
2716 case ARM::VLD2d32PseudoWB_fixed:
2717 case ARM::VLD2q8PseudoWB_fixed:
2718 case ARM::VLD2q16PseudoWB_fixed:
2719 case ARM::VLD2q32PseudoWB_fixed:
2720 case ARM::VLD2d8PseudoWB_register:
2721 case ARM::VLD2d16PseudoWB_register:
2722 case ARM::VLD2d32PseudoWB_register:
2723 case ARM::VLD2q8PseudoWB_register:
2724 case ARM::VLD2q16PseudoWB_register:
2725 case ARM::VLD2q32PseudoWB_register:
2726 case ARM::VLD3d8Pseudo:
2727 case ARM::VLD3d16Pseudo:
2728 case ARM::VLD3d32Pseudo:
2729 case ARM::VLD1d64TPseudo:
2730 case ARM::VLD3d8Pseudo_UPD:
2731 case ARM::VLD3d16Pseudo_UPD:
2732 case ARM::VLD3d32Pseudo_UPD:
2733 case ARM::VLD3q8Pseudo_UPD:
2734 case ARM::VLD3q16Pseudo_UPD:
2735 case ARM::VLD3q32Pseudo_UPD:
2736 case ARM::VLD3q8oddPseudo:
2737 case ARM::VLD3q16oddPseudo:
2738 case ARM::VLD3q32oddPseudo:
2739 case ARM::VLD3q8oddPseudo_UPD:
2740 case ARM::VLD3q16oddPseudo_UPD:
2741 case ARM::VLD3q32oddPseudo_UPD:
2742 case ARM::VLD4d8Pseudo:
2743 case ARM::VLD4d16Pseudo:
2744 case ARM::VLD4d32Pseudo:
2745 case ARM::VLD1d64QPseudo:
2746 case ARM::VLD4d8Pseudo_UPD:
2747 case ARM::VLD4d16Pseudo_UPD:
2748 case ARM::VLD4d32Pseudo_UPD:
2749 case ARM::VLD4q8Pseudo_UPD:
2750 case ARM::VLD4q16Pseudo_UPD:
2751 case ARM::VLD4q32Pseudo_UPD:
2752 case ARM::VLD4q8oddPseudo:
2753 case ARM::VLD4q16oddPseudo:
2754 case ARM::VLD4q32oddPseudo:
2755 case ARM::VLD4q8oddPseudo_UPD:
2756 case ARM::VLD4q16oddPseudo_UPD:
2757 case ARM::VLD4q32oddPseudo_UPD:
2758 case ARM::VLD1DUPq8Pseudo:
2759 case ARM::VLD1DUPq16Pseudo:
2760 case ARM::VLD1DUPq32Pseudo:
2761 case ARM::VLD1DUPq8PseudoWB_fixed:
2762 case ARM::VLD1DUPq16PseudoWB_fixed:
2763 case ARM::VLD1DUPq32PseudoWB_fixed:
2764 case ARM::VLD1DUPq8PseudoWB_register:
2765 case ARM::VLD1DUPq16PseudoWB_register:
2766 case ARM::VLD1DUPq32PseudoWB_register:
2767 case ARM::VLD2DUPd8Pseudo:
2768 case ARM::VLD2DUPd16Pseudo:
2769 case ARM::VLD2DUPd32Pseudo:
2770 case ARM::VLD2DUPd8PseudoWB_fixed:
2771 case ARM::VLD2DUPd16PseudoWB_fixed:
2772 case ARM::VLD2DUPd32PseudoWB_fixed:
2773 case ARM::VLD2DUPd8PseudoWB_register:
2774 case ARM::VLD2DUPd16PseudoWB_register:
2775 case ARM::VLD2DUPd32PseudoWB_register:
2776 case ARM::VLD4DUPd8Pseudo:
2777 case ARM::VLD4DUPd16Pseudo:
2778 case ARM::VLD4DUPd32Pseudo:
2779 case ARM::VLD4DUPd8Pseudo_UPD:
2780 case ARM::VLD4DUPd16Pseudo_UPD:
2781 case ARM::VLD4DUPd32Pseudo_UPD:
2782 case ARM::VLD1LNq8Pseudo:
2783 case ARM::VLD1LNq16Pseudo:
2784 case ARM::VLD1LNq32Pseudo:
2785 case ARM::VLD1LNq8Pseudo_UPD:
2786 case ARM::VLD1LNq16Pseudo_UPD:
2787 case ARM::VLD1LNq32Pseudo_UPD:
2788 case ARM::VLD2LNd8Pseudo:
2789 case ARM::VLD2LNd16Pseudo:
2790 case ARM::VLD2LNd32Pseudo:
2791 case ARM::VLD2LNq16Pseudo:
2792 case ARM::VLD2LNq32Pseudo:
2793 case ARM::VLD2LNd8Pseudo_UPD:
2794 case ARM::VLD2LNd16Pseudo_UPD:
2795 case ARM::VLD2LNd32Pseudo_UPD:
2796 case ARM::VLD2LNq16Pseudo_UPD:
2797 case ARM::VLD2LNq32Pseudo_UPD:
2798 case ARM::VLD4LNd8Pseudo:
2799 case ARM::VLD4LNd16Pseudo:
2800 case ARM::VLD4LNd32Pseudo:
2801 case ARM::VLD4LNq16Pseudo:
2802 case ARM::VLD4LNq32Pseudo:
2803 case ARM::VLD4LNd8Pseudo_UPD:
2804 case ARM::VLD4LNd16Pseudo_UPD:
2805 case ARM::VLD4LNd32Pseudo_UPD:
2806 case ARM::VLD4LNq16Pseudo_UPD:
2807 case ARM::VLD4LNq32Pseudo_UPD:
2808 // If the address is not 64-bit aligned, the latencies of these
2809 // instructions increases by one.
2818 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
2819 const MachineInstr *DefMI, unsigned DefIdx,
2820 const MachineInstr *DepMI) const {
2821 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
2822 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
2825 // If the second MI is predicated, then there is an implicit use dependency.
2826 return getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
2827 DepMI->getNumOperands());
2830 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2831 const MachineInstr *MI,
2832 unsigned *PredCost) const {
2833 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2834 MI->isRegSequence() || MI->isImplicitDef())
2837 if (!ItinData || ItinData->isEmpty())
2840 if (MI->isBundle()) {
2842 MachineBasicBlock::const_instr_iterator I = MI;
2843 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2844 while (++I != E && I->isInsideBundle()) {
2845 if (I->getOpcode() != ARM::t2IT)
2846 Latency += getInstrLatency(ItinData, I, PredCost);
2851 const MCInstrDesc &MCID = MI->getDesc();
2852 unsigned Class = MCID.getSchedClass();
2853 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2854 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2855 // When predicated, CPSR is an additional source operand for CPSR updating
2856 // instructions, this apparently increases their latencies.
2859 return ItinData->getStageLatency(Class);
2860 return getNumMicroOps(ItinData, MI);
2863 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2864 SDNode *Node) const {
2865 if (!Node->isMachineOpcode())
2868 if (!ItinData || ItinData->isEmpty())
2871 unsigned Opcode = Node->getMachineOpcode();
2874 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2881 bool ARMBaseInstrInfo::
2882 hasHighOperandLatency(const InstrItineraryData *ItinData,
2883 const MachineRegisterInfo *MRI,
2884 const MachineInstr *DefMI, unsigned DefIdx,
2885 const MachineInstr *UseMI, unsigned UseIdx) const {
2886 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2887 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2888 if (Subtarget.isCortexA8() &&
2889 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2890 // CortexA8 VFP instructions are not pipelined.
2893 // Hoist VFP / NEON instructions with 4 or higher latency.
2894 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2897 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2898 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2901 bool ARMBaseInstrInfo::
2902 hasLowDefLatency(const InstrItineraryData *ItinData,
2903 const MachineInstr *DefMI, unsigned DefIdx) const {
2904 if (!ItinData || ItinData->isEmpty())
2907 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2908 if (DDomain == ARMII::DomainGeneral) {
2909 unsigned DefClass = DefMI->getDesc().getSchedClass();
2910 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2911 return (DefCycle != -1 && DefCycle <= 2);
2916 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2917 StringRef &ErrInfo) const {
2918 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2919 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2926 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2927 unsigned &AddSubOpc,
2928 bool &NegAcc, bool &HasLane) const {
2929 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2930 if (I == MLxEntryMap.end())
2933 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2934 MulOpc = Entry.MulOpc;
2935 AddSubOpc = Entry.AddSubOpc;
2936 NegAcc = Entry.NegAcc;
2937 HasLane = Entry.HasLane;
2941 //===----------------------------------------------------------------------===//
2942 // Execution domains.
2943 //===----------------------------------------------------------------------===//
2945 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2946 // and some can go down both. The vmov instructions go down the VFP pipeline,
2947 // but they can be changed to vorr equivalents that are executed by the NEON
2950 // We use the following execution domain numbering:
2958 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2960 std::pair<uint16_t, uint16_t>
2961 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2962 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2964 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2965 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2967 // No other instructions can be swizzled, so just determine their domain.
2968 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2970 if (Domain & ARMII::DomainNEON)
2971 return std::make_pair(ExeNEON, 0);
2973 // Certain instructions can go either way on Cortex-A8.
2974 // Treat them as NEON instructions.
2975 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2976 return std::make_pair(ExeNEON, 0);
2978 if (Domain & ARMII::DomainVFP)
2979 return std::make_pair(ExeVFP, 0);
2981 return std::make_pair(ExeGeneric, 0);
2985 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2986 // We only know how to change VMOVD into VORR.
2987 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2988 if (Domain != ExeNEON)
2991 // Zap the predicate operands.
2992 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2993 MI->RemoveOperand(3);
2994 MI->RemoveOperand(2);
2996 // Change to a VORRd which requires two identical use operands.
2997 MI->setDesc(get(ARM::VORRd));
2999 // Add the extra source operand and new predicates.
3000 // This will go before any implicit ops.
3001 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));