1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 unsigned LastOpc = LastInst->getOpcode();
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216 if (isUncondBranchOpcode(LastOpc)) {
217 TBB = LastInst->getOperand(0).getMBB();
220 if (isCondBranchOpcode(LastOpc)) {
221 // Block ends with fall-through condbranch.
222 TBB = LastInst->getOperand(0).getMBB();
223 Cond.push_back(LastInst->getOperand(1));
224 Cond.push_back(LastInst->getOperand(2));
227 return true; // Can't handle indirect branch.
230 // Get the instruction before it if it is a terminator.
231 MachineInstr *SecondLastInst = I;
233 // If there are three terminators, we don't know what sort of block this is.
234 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
237 // If the block ends with a B and a Bcc, handle it.
238 unsigned SecondLastOpc = SecondLastInst->getOpcode();
239 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240 TBB = SecondLastInst->getOperand(0).getMBB();
241 Cond.push_back(SecondLastInst->getOperand(1));
242 Cond.push_back(SecondLastInst->getOperand(2));
243 FBB = LastInst->getOperand(0).getMBB();
247 // If the block ends with two unconditional branches, handle it. The second
248 // one is not executed, so remove it.
249 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
250 TBB = SecondLastInst->getOperand(0).getMBB();
253 I->eraseFromParent();
257 // ...likewise if it ends with a branch table followed by an unconditional
258 // branch. The branch folder can create these, and we must get rid of them for
259 // correctness of Thumb constant islands.
260 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
261 isIndirectBranchOpcode(SecondLastOpc)) &&
262 isUncondBranchOpcode(LastOpc)) {
265 I->eraseFromParent();
269 // Otherwise, can't handle this.
274 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin()) return 0;
278 if (!isUncondBranchOpcode(I->getOpcode()) &&
279 !isCondBranchOpcode(I->getOpcode()))
282 // Remove the branch.
283 I->eraseFromParent();
287 if (I == MBB.begin()) return 1;
289 if (!isCondBranchOpcode(I->getOpcode()))
292 // Remove the branch.
293 I->eraseFromParent();
298 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
299 MachineBasicBlock *FBB,
300 const SmallVectorImpl<MachineOperand> &Cond) const {
301 // FIXME this should probably have a DebugLoc argument
302 DebugLoc dl = DebugLoc::getUnknownLoc();
304 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
305 int BOpc = !AFI->isThumbFunction()
306 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
307 int BccOpc = !AFI->isThumbFunction()
308 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
310 // Shouldn't be a fall through.
311 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
312 assert((Cond.size() == 2 || Cond.size() == 0) &&
313 "ARM branch conditions have two components!");
316 if (Cond.empty()) // Unconditional branch?
317 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
319 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
320 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
324 // Two-way conditional branch.
325 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
326 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
327 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
331 bool ARMBaseInstrInfo::
332 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
333 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
334 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
338 bool ARMBaseInstrInfo::
339 PredicateInstruction(MachineInstr *MI,
340 const SmallVectorImpl<MachineOperand> &Pred) const {
341 unsigned Opc = MI->getOpcode();
342 if (isUncondBranchOpcode(Opc)) {
343 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
344 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
345 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
349 int PIdx = MI->findFirstPredOperandIdx();
351 MachineOperand &PMO = MI->getOperand(PIdx);
352 PMO.setImm(Pred[0].getImm());
353 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
359 bool ARMBaseInstrInfo::
360 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
361 const SmallVectorImpl<MachineOperand> &Pred2) const {
362 if (Pred1.size() > 2 || Pred2.size() > 2)
365 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
366 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
376 return CC2 == ARMCC::HI;
378 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
380 return CC2 == ARMCC::GT;
382 return CC2 == ARMCC::LT;
386 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
387 std::vector<MachineOperand> &Pred) const {
388 // FIXME: This confuses implicit_def with optional CPSR def.
389 const TargetInstrDesc &TID = MI->getDesc();
390 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395 const MachineOperand &MO = MI->getOperand(i);
396 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
406 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
407 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
408 unsigned JTI) DISABLE_INLINE;
409 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
411 return JT[JTI].MBBs.size();
414 /// GetInstSize - Return the size of the specified MachineInstr.
416 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
417 const MachineBasicBlock &MBB = *MI->getParent();
418 const MachineFunction *MF = MBB.getParent();
419 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
421 // Basic size info comes from the TSFlags field.
422 const TargetInstrDesc &TID = MI->getDesc();
423 unsigned TSFlags = TID.TSFlags;
425 unsigned Opc = MI->getOpcode();
426 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
428 // If this machine instr is an inline asm, measure it.
429 if (MI->getOpcode() == ARM::INLINEASM)
430 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
435 llvm_unreachable("Unknown or unset size field for instr!");
436 case TargetInstrInfo::IMPLICIT_DEF:
437 case TargetInstrInfo::KILL:
438 case TargetInstrInfo::DBG_LABEL:
439 case TargetInstrInfo::EH_LABEL:
444 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
445 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
446 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
447 case ARMII::SizeSpecial: {
449 case ARM::CONSTPOOL_ENTRY:
450 // If this machine instr is a constant pool entry, its size is recorded as
452 return MI->getOperand(2).getImm();
453 case ARM::Int_eh_sjlj_setjmp:
455 case ARM::t2Int_eh_sjlj_setjmp:
464 // These are jumptable branches, i.e. a branch followed by an inlined
465 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
466 // entry is one byte; TBH two byte each.
467 unsigned EntrySize = (Opc == ARM::t2TBB)
468 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
469 unsigned NumOps = TID.getNumOperands();
470 MachineOperand JTOP =
471 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
472 unsigned JTI = JTOP.getIndex();
473 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
474 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
475 assert(JTI < JT.size());
476 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
477 // 4 aligned. The assembler / linker may add 2 byte padding just before
478 // the JT entries. The size does not include this padding; the
479 // constant islands pass does separate bookkeeping for it.
480 // FIXME: If we know the size of the function is less than (1 << 16) *2
481 // bytes, we can use 16-bit entries instead. Then there won't be an
483 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
484 unsigned NumEntries = getNumJTEntries(JT, JTI);
485 if (Opc == ARM::t2TBB && (NumEntries & 1))
486 // Make sure the instruction that follows TBB is 2-byte aligned.
487 // FIXME: Constant island pass should insert an "ALIGN" instruction
490 return NumEntries * EntrySize + InstSize;
493 // Otherwise, pseudo-instruction sizes are zero.
498 return 0; // Not reached
501 /// Return true if the instruction is a register to register move and
502 /// leave the source and dest operands in the passed parameters.
505 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
506 unsigned &SrcReg, unsigned &DstReg,
507 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
508 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
510 switch (MI.getOpcode()) {
516 SrcReg = MI.getOperand(1).getReg();
517 DstReg = MI.getOperand(0).getReg();
522 case ARM::tMOVgpr2tgpr:
523 case ARM::tMOVtgpr2gpr:
524 case ARM::tMOVgpr2gpr:
526 assert(MI.getDesc().getNumOperands() >= 2 &&
527 MI.getOperand(0).isReg() &&
528 MI.getOperand(1).isReg() &&
529 "Invalid ARM MOV instruction");
530 SrcReg = MI.getOperand(1).getReg();
531 DstReg = MI.getOperand(0).getReg();
540 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
541 int &FrameIndex) const {
542 switch (MI->getOpcode()) {
545 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
546 if (MI->getOperand(1).isFI() &&
547 MI->getOperand(2).isReg() &&
548 MI->getOperand(3).isImm() &&
549 MI->getOperand(2).getReg() == 0 &&
550 MI->getOperand(3).getImm() == 0) {
551 FrameIndex = MI->getOperand(1).getIndex();
552 return MI->getOperand(0).getReg();
557 if (MI->getOperand(1).isFI() &&
558 MI->getOperand(2).isImm() &&
559 MI->getOperand(2).getImm() == 0) {
560 FrameIndex = MI->getOperand(1).getIndex();
561 return MI->getOperand(0).getReg();
566 if (MI->getOperand(1).isFI() &&
567 MI->getOperand(2).isImm() &&
568 MI->getOperand(2).getImm() == 0) {
569 FrameIndex = MI->getOperand(1).getIndex();
570 return MI->getOperand(0).getReg();
579 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
580 int &FrameIndex) const {
581 switch (MI->getOpcode()) {
584 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
585 if (MI->getOperand(1).isFI() &&
586 MI->getOperand(2).isReg() &&
587 MI->getOperand(3).isImm() &&
588 MI->getOperand(2).getReg() == 0 &&
589 MI->getOperand(3).getImm() == 0) {
590 FrameIndex = MI->getOperand(1).getIndex();
591 return MI->getOperand(0).getReg();
596 if (MI->getOperand(1).isFI() &&
597 MI->getOperand(2).isImm() &&
598 MI->getOperand(2).getImm() == 0) {
599 FrameIndex = MI->getOperand(1).getIndex();
600 return MI->getOperand(0).getReg();
605 if (MI->getOperand(1).isFI() &&
606 MI->getOperand(2).isImm() &&
607 MI->getOperand(2).getImm() == 0) {
608 FrameIndex = MI->getOperand(1).getIndex();
609 return MI->getOperand(0).getReg();
618 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator I,
620 unsigned DestReg, unsigned SrcReg,
621 const TargetRegisterClass *DestRC,
622 const TargetRegisterClass *SrcRC) const {
623 DebugLoc DL = DebugLoc::getUnknownLoc();
624 if (I != MBB.end()) DL = I->getDebugLoc();
626 if (DestRC != SrcRC) {
627 if (DestRC->getSize() != SrcRC->getSize())
630 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
631 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
632 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
636 if (DestRC == ARM::GPRRegisterClass) {
637 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
638 DestReg).addReg(SrcReg)));
639 } else if (DestRC == ARM::SPRRegisterClass) {
640 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVS), DestReg)
642 } else if (DestRC == ARM::DPRRegisterClass) {
643 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg)
645 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
646 DestRC == ARM::DPR_8RegisterClass ||
647 SrcRC == ARM::DPR_VFP2RegisterClass ||
648 SrcRC == ARM::DPR_8RegisterClass) {
649 // Always use neon reg-reg move if source or dest is NEON-only regclass.
650 BuildMI(MBB, I, DL, get(ARM::VMOVDneon), DestReg).addReg(SrcReg);
651 } else if (DestRC == ARM::QPRRegisterClass ||
652 DestRC == ARM::QPR_VFP2RegisterClass ||
653 DestRC == ARM::QPR_8RegisterClass) {
654 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
662 void ARMBaseInstrInfo::
663 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
664 unsigned SrcReg, bool isKill, int FI,
665 const TargetRegisterClass *RC) const {
666 DebugLoc DL = DebugLoc::getUnknownLoc();
667 if (I != MBB.end()) DL = I->getDebugLoc();
668 MachineFunction &MF = *MBB.getParent();
669 MachineFrameInfo &MFI = *MF.getFrameInfo();
670 unsigned Align = MFI.getObjectAlignment(FI);
672 MachineMemOperand *MMO =
673 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
674 MachineMemOperand::MOStore, 0,
675 MFI.getObjectSize(FI),
678 if (RC == ARM::GPRRegisterClass) {
679 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
680 .addReg(SrcReg, getKillRegState(isKill))
681 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
682 } else if (RC == ARM::DPRRegisterClass ||
683 RC == ARM::DPR_VFP2RegisterClass ||
684 RC == ARM::DPR_8RegisterClass) {
685 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
686 .addReg(SrcReg, getKillRegState(isKill))
687 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
688 } else if (RC == ARM::SPRRegisterClass) {
689 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
690 .addReg(SrcReg, getKillRegState(isKill))
691 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
693 assert((RC == ARM::QPRRegisterClass ||
694 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
695 // FIXME: Neon instructions should support predicates
697 && (getRegisterInfo().needsStackRealignment(MF))) {
698 BuildMI(MBB, I, DL, get(ARM::VST1q64))
699 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO)
700 .addReg(SrcReg, getKillRegState(isKill));
702 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
703 addReg(SrcReg, getKillRegState(isKill))
704 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
709 void ARMBaseInstrInfo::
710 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
711 unsigned DestReg, int FI,
712 const TargetRegisterClass *RC) const {
713 DebugLoc DL = DebugLoc::getUnknownLoc();
714 if (I != MBB.end()) DL = I->getDebugLoc();
715 MachineFunction &MF = *MBB.getParent();
716 MachineFrameInfo &MFI = *MF.getFrameInfo();
717 unsigned Align = MFI.getObjectAlignment(FI);
719 MachineMemOperand *MMO =
720 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
721 MachineMemOperand::MOLoad, 0,
722 MFI.getObjectSize(FI),
725 if (RC == ARM::GPRRegisterClass) {
726 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
727 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
728 } else if (RC == ARM::DPRRegisterClass ||
729 RC == ARM::DPR_VFP2RegisterClass ||
730 RC == ARM::DPR_8RegisterClass) {
731 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
732 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
733 } else if (RC == ARM::SPRRegisterClass) {
734 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
735 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
737 assert((RC == ARM::QPRRegisterClass ||
738 RC == ARM::QPR_VFP2RegisterClass ||
739 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
740 // FIXME: Neon instructions should support predicates
742 && (getRegisterInfo().needsStackRealignment(MF))) {
743 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
744 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO);
746 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
752 MachineInstr *ARMBaseInstrInfo::
753 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
754 const SmallVectorImpl<unsigned> &Ops, int FI) const {
755 if (Ops.size() != 1) return NULL;
757 unsigned OpNum = Ops[0];
758 unsigned Opc = MI->getOpcode();
759 MachineInstr *NewMI = NULL;
760 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
761 // If it is updating CPSR, then it cannot be folded.
762 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
764 unsigned Pred = MI->getOperand(2).getImm();
765 unsigned PredReg = MI->getOperand(3).getReg();
766 if (OpNum == 0) { // move -> store
767 unsigned SrcReg = MI->getOperand(1).getReg();
768 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
769 bool isKill = MI->getOperand(1).isKill();
770 bool isUndef = MI->getOperand(1).isUndef();
771 if (Opc == ARM::MOVr)
772 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
774 getKillRegState(isKill) | getUndefRegState(isUndef),
776 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
778 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
780 getKillRegState(isKill) | getUndefRegState(isUndef),
782 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
783 } else { // move -> load
784 unsigned DstReg = MI->getOperand(0).getReg();
785 unsigned DstSubReg = MI->getOperand(0).getSubReg();
786 bool isDead = MI->getOperand(0).isDead();
787 bool isUndef = MI->getOperand(0).isUndef();
788 if (Opc == ARM::MOVr)
789 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
792 getDeadRegState(isDead) |
793 getUndefRegState(isUndef), DstSubReg)
794 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
796 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
799 getDeadRegState(isDead) |
800 getUndefRegState(isUndef), DstSubReg)
801 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
803 } else if (Opc == ARM::tMOVgpr2gpr ||
804 Opc == ARM::tMOVtgpr2gpr ||
805 Opc == ARM::tMOVgpr2tgpr) {
806 if (OpNum == 0) { // move -> store
807 unsigned SrcReg = MI->getOperand(1).getReg();
808 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
809 bool isKill = MI->getOperand(1).isKill();
810 bool isUndef = MI->getOperand(1).isUndef();
811 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
813 getKillRegState(isKill) | getUndefRegState(isUndef),
815 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
816 } else { // move -> load
817 unsigned DstReg = MI->getOperand(0).getReg();
818 unsigned DstSubReg = MI->getOperand(0).getSubReg();
819 bool isDead = MI->getOperand(0).isDead();
820 bool isUndef = MI->getOperand(0).isUndef();
821 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
824 getDeadRegState(isDead) |
825 getUndefRegState(isUndef),
827 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
829 } else if (Opc == ARM::VMOVS) {
830 unsigned Pred = MI->getOperand(2).getImm();
831 unsigned PredReg = MI->getOperand(3).getReg();
832 if (OpNum == 0) { // move -> store
833 unsigned SrcReg = MI->getOperand(1).getReg();
834 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
835 bool isKill = MI->getOperand(1).isKill();
836 bool isUndef = MI->getOperand(1).isUndef();
837 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
838 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
841 .addImm(0).addImm(Pred).addReg(PredReg);
842 } else { // move -> load
843 unsigned DstReg = MI->getOperand(0).getReg();
844 unsigned DstSubReg = MI->getOperand(0).getSubReg();
845 bool isDead = MI->getOperand(0).isDead();
846 bool isUndef = MI->getOperand(0).isUndef();
847 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
850 getDeadRegState(isDead) |
851 getUndefRegState(isUndef),
853 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
856 else if (Opc == ARM::VMOVD) {
857 unsigned Pred = MI->getOperand(2).getImm();
858 unsigned PredReg = MI->getOperand(3).getReg();
859 if (OpNum == 0) { // move -> store
860 unsigned SrcReg = MI->getOperand(1).getReg();
861 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
862 bool isKill = MI->getOperand(1).isKill();
863 bool isUndef = MI->getOperand(1).isUndef();
864 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
866 getKillRegState(isKill) | getUndefRegState(isUndef),
868 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
869 } else { // move -> load
870 unsigned DstReg = MI->getOperand(0).getReg();
871 unsigned DstSubReg = MI->getOperand(0).getSubReg();
872 bool isDead = MI->getOperand(0).isDead();
873 bool isUndef = MI->getOperand(0).isUndef();
874 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
877 getDeadRegState(isDead) |
878 getUndefRegState(isUndef),
880 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
888 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
890 const SmallVectorImpl<unsigned> &Ops,
891 MachineInstr* LoadMI) const {
897 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
898 const SmallVectorImpl<unsigned> &Ops) const {
899 if (Ops.size() != 1) return false;
901 unsigned Opc = MI->getOpcode();
902 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
903 // If it is updating CPSR, then it cannot be folded.
904 return MI->getOperand(4).getReg() != ARM::CPSR ||
905 MI->getOperand(4).isDead();
906 } else if (Opc == ARM::tMOVgpr2gpr ||
907 Opc == ARM::tMOVtgpr2gpr ||
908 Opc == ARM::tMOVgpr2tgpr) {
910 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
912 } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
913 return false; // FIXME
919 void ARMBaseInstrInfo::
920 reMaterialize(MachineBasicBlock &MBB,
921 MachineBasicBlock::iterator I,
922 unsigned DestReg, unsigned SubIdx,
923 const MachineInstr *Orig,
924 const TargetRegisterInfo *TRI) const {
925 DebugLoc dl = Orig->getDebugLoc();
927 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
928 DestReg = TRI->getSubReg(DestReg, SubIdx);
932 unsigned Opcode = Orig->getOpcode();
935 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
936 MI->getOperand(0).setReg(DestReg);
940 case ARM::tLDRpci_pic:
941 case ARM::t2LDRpci_pic: {
942 MachineFunction &MF = *MBB.getParent();
943 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
944 MachineConstantPool *MCP = MF.getConstantPool();
945 unsigned CPI = Orig->getOperand(1).getIndex();
946 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
947 assert(MCPE.isMachineConstantPoolEntry() &&
948 "Expecting a machine constantpool entry!");
949 ARMConstantPoolValue *ACPV =
950 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
951 unsigned PCLabelId = AFI->createConstPoolEntryUId();
952 ARMConstantPoolValue *NewCPV = 0;
953 if (ACPV->isGlobalValue())
954 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
956 else if (ACPV->isExtSymbol())
957 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
958 ACPV->getSymbol(), PCLabelId, 4);
959 else if (ACPV->isBlockAddress())
960 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
961 ARMCP::CPBlockAddress, 4);
963 llvm_unreachable("Unexpected ARM constantpool value type!!");
964 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
965 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
967 .addConstantPoolIndex(CPI).addImm(PCLabelId);
968 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
973 MachineInstr *NewMI = prior(I);
974 NewMI->getOperand(0).setSubReg(SubIdx);
977 bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
978 const MachineInstr *MI1,
979 const MachineRegisterInfo *MRI) const {
980 int Opcode = MI0->getOpcode();
981 if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
982 if (MI1->getOpcode() != Opcode)
984 if (MI0->getNumOperands() != MI1->getNumOperands())
987 const MachineOperand &MO0 = MI0->getOperand(1);
988 const MachineOperand &MO1 = MI1->getOperand(1);
989 if (MO0.getOffset() != MO1.getOffset())
992 const MachineFunction *MF = MI0->getParent()->getParent();
993 const MachineConstantPool *MCP = MF->getConstantPool();
994 int CPI0 = MO0.getIndex();
995 int CPI1 = MO1.getIndex();
996 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
997 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
998 ARMConstantPoolValue *ACPV0 =
999 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1000 ARMConstantPoolValue *ACPV1 =
1001 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1002 return ACPV0->hasSameValue(ACPV1);
1005 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
1008 unsigned ARMBaseInstrInfo::TailDuplicationLimit(const MachineBasicBlock &MBB,
1009 unsigned DefaultLimit) const {
1010 // If the target processor can predict indirect branches, it is highly
1011 // desirable to duplicate them, since it can often make them predictable.
1012 if (!MBB.empty() && isIndirectBranchOpcode(MBB.back().getOpcode()) &&
1013 getSubtarget().hasBranchTargetBuffer())
1014 return DefaultLimit + 2;
1015 return DefaultLimit;
1018 /// getInstrPredicate - If instruction is predicated, returns its predicate
1019 /// condition, otherwise returns AL. It also returns the condition code
1020 /// register by reference.
1022 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1023 int PIdx = MI->findFirstPredOperandIdx();
1029 PredReg = MI->getOperand(PIdx+1).getReg();
1030 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1034 int llvm::getMatchingCondBranchOpcode(int Opc) {
1037 else if (Opc == ARM::tB)
1039 else if (Opc == ARM::t2B)
1042 llvm_unreachable("Unknown unconditional branch opcode!");
1047 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1048 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1049 unsigned DestReg, unsigned BaseReg, int NumBytes,
1050 ARMCC::CondCodes Pred, unsigned PredReg,
1051 const ARMBaseInstrInfo &TII) {
1052 bool isSub = NumBytes < 0;
1053 if (isSub) NumBytes = -NumBytes;
1056 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1057 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1058 assert(ThisVal && "Didn't extract field correctly");
1060 // We will handle these bits from offset, clear them.
1061 NumBytes &= ~ThisVal;
1063 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1065 // Build the new ADD / SUB.
1066 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1067 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1068 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1069 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1074 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1075 unsigned FrameReg, int &Offset,
1076 const ARMBaseInstrInfo &TII) {
1077 unsigned Opcode = MI.getOpcode();
1078 const TargetInstrDesc &Desc = MI.getDesc();
1079 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1082 // Memory operands in inline assembly always use AddrMode2.
1083 if (Opcode == ARM::INLINEASM)
1084 AddrMode = ARMII::AddrMode2;
1086 if (Opcode == ARM::ADDri) {
1087 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1089 // Turn it into a move.
1090 MI.setDesc(TII.get(ARM::MOVr));
1091 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1092 MI.RemoveOperand(FrameRegIdx+1);
1095 } else if (Offset < 0) {
1098 MI.setDesc(TII.get(ARM::SUBri));
1101 // Common case: small offset, fits into instruction.
1102 if (ARM_AM::getSOImmVal(Offset) != -1) {
1103 // Replace the FrameIndex with sp / fp
1104 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1105 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1110 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1112 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1113 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1115 // We will handle these bits from offset, clear them.
1116 Offset &= ~ThisImmVal;
1118 // Get the properly encoded SOImmVal field.
1119 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1120 "Bit extraction didn't work?");
1121 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1123 unsigned ImmIdx = 0;
1125 unsigned NumBits = 0;
1128 case ARMII::AddrMode2: {
1129 ImmIdx = FrameRegIdx+2;
1130 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1131 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1136 case ARMII::AddrMode3: {
1137 ImmIdx = FrameRegIdx+2;
1138 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1139 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1144 case ARMII::AddrMode4:
1145 case ARMII::AddrMode6:
1146 // Can't fold any offset even if it's zero.
1148 case ARMII::AddrMode5: {
1149 ImmIdx = FrameRegIdx+1;
1150 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1151 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1158 llvm_unreachable("Unsupported addressing mode!");
1162 Offset += InstrOffs * Scale;
1163 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1169 // Attempt to fold address comp. if opcode has offset bits
1171 // Common case: small offset, fits into instruction.
1172 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1173 int ImmedOffset = Offset / Scale;
1174 unsigned Mask = (1 << NumBits) - 1;
1175 if ((unsigned)Offset <= Mask * Scale) {
1176 // Replace the FrameIndex with sp
1177 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1179 ImmedOffset |= 1 << NumBits;
1180 ImmOp.ChangeToImmediate(ImmedOffset);
1185 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1186 ImmedOffset = ImmedOffset & Mask;
1188 ImmedOffset |= 1 << NumBits;
1189 ImmOp.ChangeToImmediate(ImmedOffset);
1190 Offset &= ~(Mask*Scale);
1194 Offset = (isSub) ? -Offset : Offset;