1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 static cl::opt<unsigned>
53 SwiftPartialUpdateClearance("swift-partial-update-clearance",
54 cl::Hidden, cl::init(12),
55 cl::desc("Clearance before partial register updates"));
57 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
59 uint16_t MLxOpc; // MLA / MLS opcode
60 uint16_t MulOpc; // Expanded multiplication opcode
61 uint16_t AddSubOpc; // Expanded add / sub opcode
62 bool NegAcc; // True if the acc is negated before the add / sub.
63 bool HasLane; // True if instruction has an extra "lane" operand.
66 static const ARM_MLxEntry ARM_MLxTable[] = {
67 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
69 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
70 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
71 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
72 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
73 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
74 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
75 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
76 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
79 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
80 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
81 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
82 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
83 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
84 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
85 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
86 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
89 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
90 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
92 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
93 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
94 assert(false && "Duplicated entries?");
95 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
96 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
100 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
101 // currently defaults to no prepass hazard recognizer.
102 ScheduleHazardRecognizer *ARMBaseInstrInfo::
103 CreateTargetHazardRecognizer(const TargetMachine *TM,
104 const ScheduleDAG *DAG) const {
105 if (usePreRAHazardRecognizer()) {
106 const InstrItineraryData *II = TM->getInstrItineraryData();
107 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
109 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
112 ScheduleHazardRecognizer *ARMBaseInstrInfo::
113 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
114 const ScheduleDAG *DAG) const {
115 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
116 return (ScheduleHazardRecognizer *)
117 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
118 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
122 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
123 MachineBasicBlock::iterator &MBBI,
124 LiveVariables *LV) const {
125 // FIXME: Thumb2 support.
130 MachineInstr *MI = MBBI;
131 MachineFunction &MF = *MI->getParent()->getParent();
132 uint64_t TSFlags = MI->getDesc().TSFlags;
134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
135 default: return NULL;
136 case ARMII::IndexModePre:
139 case ARMII::IndexModePost:
143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
149 MachineInstr *UpdateMI = NULL;
150 MachineInstr *MemMI = NULL;
151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
152 const MCInstrDesc &MCID = MI->getDesc();
153 unsigned NumOps = MCID.getNumOperands();
154 bool isLoad = !MI->mayStore();
155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
158 unsigned WBReg = WB.getReg();
159 unsigned BaseReg = Base.getReg();
160 unsigned OffReg = Offset.getReg();
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
164 default: llvm_unreachable("Unknown indexed op!");
165 case ARMII::AddrMode2: {
166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
167 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
169 if (ARM_AM::getSOImmVal(Amt) == -1)
170 // Can't encode it in a so_imm operand. This transformation will
171 // add more than 1 instruction. Abandon!
173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
175 .addReg(BaseReg).addImm(Amt)
176 .addImm(Pred).addReg(0).addReg(0);
177 } else if (Amt != 0) {
178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
183 .addImm(Pred).addReg(0).addReg(0);
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 .addReg(BaseReg).addReg(OffReg)
188 .addImm(Pred).addReg(0).addReg(0);
191 case ARMII::AddrMode3 : {
192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
193 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
198 .addReg(BaseReg).addImm(Amt)
199 .addImm(Pred).addReg(0).addReg(0);
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
203 .addReg(BaseReg).addReg(OffReg)
204 .addImm(Pred).addReg(0).addReg(0);
209 std::vector<MachineInstr*> NewMIs;
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(WBReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
219 NewMIs.push_back(MemMI);
220 NewMIs.push_back(UpdateMI);
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
224 get(MemOpc), MI->getOperand(0).getReg())
225 .addReg(BaseReg).addImm(0).addImm(Pred);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc)).addReg(MI->getOperand(1).getReg())
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
231 UpdateMI->getOperand(0).setIsDead();
232 NewMIs.push_back(UpdateMI);
233 NewMIs.push_back(MemMI);
236 // Transfer LiveVariables states, kill / dead info.
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
241 unsigned Reg = MO.getReg();
243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
247 LV->addVirtualRegisterDead(Reg, NewMI);
249 if (MO.isUse() && MO.isKill()) {
250 for (unsigned j = 0; j < 2; ++j) {
251 // Look at the two new MI's in reverse order.
252 MachineInstr *NewMI = NewMIs[j];
253 if (!NewMI->readsRegister(Reg))
255 LV->addVirtualRegisterKilled(Reg, NewMI);
256 if (VI.removeKill(MI))
257 VI.Kills.push_back(NewMI);
265 MFI->insert(MBBI, NewMIs[1]);
266 MFI->insert(MBBI, NewMIs[0]);
272 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
273 MachineBasicBlock *&FBB,
274 SmallVectorImpl<MachineOperand> &Cond,
275 bool AllowModify) const {
276 // If the block has no terminators, it just falls into the block after it.
277 MachineBasicBlock::iterator I = MBB.end();
278 if (I == MBB.begin())
281 while (I->isDebugValue()) {
282 if (I == MBB.begin())
286 if (!isUnpredicatedTerminator(I))
289 // Get the last instruction in the block.
290 MachineInstr *LastInst = I;
292 // If there is only one terminator instruction, process it.
293 unsigned LastOpc = LastInst->getOpcode();
294 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
295 if (isUncondBranchOpcode(LastOpc)) {
296 TBB = LastInst->getOperand(0).getMBB();
299 if (isCondBranchOpcode(LastOpc)) {
300 // Block ends with fall-through condbranch.
301 TBB = LastInst->getOperand(0).getMBB();
302 Cond.push_back(LastInst->getOperand(1));
303 Cond.push_back(LastInst->getOperand(2));
306 return true; // Can't handle indirect branch.
309 // Get the instruction before it if it is a terminator.
310 MachineInstr *SecondLastInst = I;
311 unsigned SecondLastOpc = SecondLastInst->getOpcode();
313 // If AllowModify is true and the block ends with two or more unconditional
314 // branches, delete all but the first unconditional branch.
315 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
316 while (isUncondBranchOpcode(SecondLastOpc)) {
317 LastInst->eraseFromParent();
318 LastInst = SecondLastInst;
319 LastOpc = LastInst->getOpcode();
320 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
321 // Return now the only terminator is an unconditional branch.
322 TBB = LastInst->getOperand(0).getMBB();
326 SecondLastOpc = SecondLastInst->getOpcode();
331 // If there are three terminators, we don't know what sort of block this is.
332 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
335 // If the block ends with a B and a Bcc, handle it.
336 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
337 TBB = SecondLastInst->getOperand(0).getMBB();
338 Cond.push_back(SecondLastInst->getOperand(1));
339 Cond.push_back(SecondLastInst->getOperand(2));
340 FBB = LastInst->getOperand(0).getMBB();
344 // If the block ends with two unconditional branches, handle it. The second
345 // one is not executed, so remove it.
346 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
347 TBB = SecondLastInst->getOperand(0).getMBB();
350 I->eraseFromParent();
354 // ...likewise if it ends with a branch table followed by an unconditional
355 // branch. The branch folder can create these, and we must get rid of them for
356 // correctness of Thumb constant islands.
357 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
358 isIndirectBranchOpcode(SecondLastOpc)) &&
359 isUncondBranchOpcode(LastOpc)) {
362 I->eraseFromParent();
366 // Otherwise, can't handle this.
371 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
372 MachineBasicBlock::iterator I = MBB.end();
373 if (I == MBB.begin()) return 0;
375 while (I->isDebugValue()) {
376 if (I == MBB.begin())
380 if (!isUncondBranchOpcode(I->getOpcode()) &&
381 !isCondBranchOpcode(I->getOpcode()))
384 // Remove the branch.
385 I->eraseFromParent();
389 if (I == MBB.begin()) return 1;
391 if (!isCondBranchOpcode(I->getOpcode()))
394 // Remove the branch.
395 I->eraseFromParent();
400 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
401 MachineBasicBlock *FBB,
402 const SmallVectorImpl<MachineOperand> &Cond,
404 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
405 int BOpc = !AFI->isThumbFunction()
406 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
407 int BccOpc = !AFI->isThumbFunction()
408 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
409 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
411 // Shouldn't be a fall through.
412 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
413 assert((Cond.size() == 2 || Cond.size() == 0) &&
414 "ARM branch conditions have two components!");
417 if (Cond.empty()) { // Unconditional branch?
419 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
421 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
423 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
424 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
428 // Two-way conditional branch.
429 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
430 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
432 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
434 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
438 bool ARMBaseInstrInfo::
439 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
440 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
441 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
445 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
446 if (MI->isBundle()) {
447 MachineBasicBlock::const_instr_iterator I = MI;
448 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
449 while (++I != E && I->isInsideBundle()) {
450 int PIdx = I->findFirstPredOperandIdx();
451 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
457 int PIdx = MI->findFirstPredOperandIdx();
458 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
461 bool ARMBaseInstrInfo::
462 PredicateInstruction(MachineInstr *MI,
463 const SmallVectorImpl<MachineOperand> &Pred) const {
464 unsigned Opc = MI->getOpcode();
465 if (isUncondBranchOpcode(Opc)) {
466 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
467 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
468 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
472 int PIdx = MI->findFirstPredOperandIdx();
474 MachineOperand &PMO = MI->getOperand(PIdx);
475 PMO.setImm(Pred[0].getImm());
476 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
482 bool ARMBaseInstrInfo::
483 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
484 const SmallVectorImpl<MachineOperand> &Pred2) const {
485 if (Pred1.size() > 2 || Pred2.size() > 2)
488 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
489 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
499 return CC2 == ARMCC::HI;
501 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
503 return CC2 == ARMCC::GT;
505 return CC2 == ARMCC::LT;
509 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
510 std::vector<MachineOperand> &Pred) const {
512 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
513 const MachineOperand &MO = MI->getOperand(i);
514 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
515 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
524 /// isPredicable - Return true if the specified instruction can be predicated.
525 /// By default, this returns true for every instruction with a
526 /// PredicateOperand.
527 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
528 if (!MI->isPredicable())
531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
532 ARMFunctionInfo *AFI =
533 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
534 return AFI->isThumb2Function();
539 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
540 LLVM_ATTRIBUTE_NOINLINE
541 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
543 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
545 assert(JTI < JT.size());
546 return JT[JTI].MBBs.size();
549 /// GetInstSize - Return the size of the specified MachineInstr.
551 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
552 const MachineBasicBlock &MBB = *MI->getParent();
553 const MachineFunction *MF = MBB.getParent();
554 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
556 const MCInstrDesc &MCID = MI->getDesc();
558 return MCID.getSize();
560 // If this machine instr is an inline asm, measure it.
561 if (MI->getOpcode() == ARM::INLINEASM)
562 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
565 unsigned Opc = MI->getOpcode();
567 case TargetOpcode::IMPLICIT_DEF:
568 case TargetOpcode::KILL:
569 case TargetOpcode::PROLOG_LABEL:
570 case TargetOpcode::EH_LABEL:
571 case TargetOpcode::DBG_VALUE:
573 case TargetOpcode::BUNDLE:
574 return getInstBundleLength(MI);
575 case ARM::MOVi16_ga_pcrel:
576 case ARM::MOVTi16_ga_pcrel:
577 case ARM::t2MOVi16_ga_pcrel:
578 case ARM::t2MOVTi16_ga_pcrel:
581 case ARM::t2MOVi32imm:
583 case ARM::CONSTPOOL_ENTRY:
584 // If this machine instr is a constant pool entry, its size is recorded as
586 return MI->getOperand(2).getImm();
587 case ARM::Int_eh_sjlj_longjmp:
589 case ARM::tInt_eh_sjlj_longjmp:
591 case ARM::Int_eh_sjlj_setjmp:
592 case ARM::Int_eh_sjlj_setjmp_nofp:
594 case ARM::tInt_eh_sjlj_setjmp:
595 case ARM::t2Int_eh_sjlj_setjmp:
596 case ARM::t2Int_eh_sjlj_setjmp_nofp:
604 case ARM::t2TBH_JT: {
605 // These are jumptable branches, i.e. a branch followed by an inlined
606 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
607 // entry is one byte; TBH two byte each.
608 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
609 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
610 unsigned NumOps = MCID.getNumOperands();
611 MachineOperand JTOP =
612 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
613 unsigned JTI = JTOP.getIndex();
614 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
616 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
617 assert(JTI < JT.size());
618 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
619 // 4 aligned. The assembler / linker may add 2 byte padding just before
620 // the JT entries. The size does not include this padding; the
621 // constant islands pass does separate bookkeeping for it.
622 // FIXME: If we know the size of the function is less than (1 << 16) *2
623 // bytes, we can use 16-bit entries instead. Then there won't be an
625 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
626 unsigned NumEntries = getNumJTEntries(JT, JTI);
627 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
628 // Make sure the instruction that follows TBB is 2-byte aligned.
629 // FIXME: Constant island pass should insert an "ALIGN" instruction
632 return NumEntries * EntrySize + InstSize;
635 // Otherwise, pseudo-instruction sizes are zero.
640 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
642 MachineBasicBlock::const_instr_iterator I = MI;
643 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
644 while (++I != E && I->isInsideBundle()) {
645 assert(!I->isBundle() && "No nested bundle!");
646 Size += GetInstSizeInBytes(&*I);
651 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
652 MachineBasicBlock::iterator I, DebugLoc DL,
653 unsigned DestReg, unsigned SrcReg,
654 bool KillSrc) const {
655 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
656 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
658 if (GPRDest && GPRSrc) {
659 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
660 .addReg(SrcReg, getKillRegState(KillSrc))));
664 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
665 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
668 if (SPRDest && SPRSrc)
670 else if (GPRDest && SPRSrc)
672 else if (SPRDest && GPRSrc)
674 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
676 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
680 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
681 MIB.addReg(SrcReg, getKillRegState(KillSrc));
682 if (Opc == ARM::VORRq)
683 MIB.addReg(SrcReg, getKillRegState(KillSrc));
688 // Handle register classes that require multiple instructions.
689 unsigned BeginIdx = 0;
690 unsigned SubRegs = 0;
693 // Use VORRq when possible.
694 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
695 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
696 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
697 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
698 // Fall back to VMOVD.
699 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
700 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
701 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
703 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
706 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
707 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
708 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
709 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
710 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
711 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
713 assert(Opc && "Impossible reg-to-reg copy");
715 const TargetRegisterInfo *TRI = &getRegisterInfo();
716 MachineInstrBuilder Mov;
718 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
719 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
720 BeginIdx = BeginIdx + ((SubRegs-1)*Spacing);
724 SmallSet<unsigned, 4> DstRegs;
726 for (unsigned i = 0; i != SubRegs; ++i) {
727 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
728 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
729 assert(Dst && Src && "Bad sub-register");
731 assert(!DstRegs.count(Src) && "destructive vector copy");
734 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
736 // VORR takes two source operands.
737 if (Opc == ARM::VORRq)
739 Mov = AddDefaultPred(Mov);
741 // Add implicit super-register defs and kills to the last instruction.
742 Mov->addRegisterDefined(DestReg, TRI);
744 Mov->addRegisterKilled(SrcReg, TRI);
748 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
749 unsigned Reg, unsigned SubIdx, unsigned State,
750 const TargetRegisterInfo *TRI) {
752 return MIB.addReg(Reg, State);
754 if (TargetRegisterInfo::isPhysicalRegister(Reg))
755 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
756 return MIB.addReg(Reg, State, SubIdx);
759 void ARMBaseInstrInfo::
760 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
761 unsigned SrcReg, bool isKill, int FI,
762 const TargetRegisterClass *RC,
763 const TargetRegisterInfo *TRI) const {
765 if (I != MBB.end()) DL = I->getDebugLoc();
766 MachineFunction &MF = *MBB.getParent();
767 MachineFrameInfo &MFI = *MF.getFrameInfo();
768 unsigned Align = MFI.getObjectAlignment(FI);
770 MachineMemOperand *MMO =
771 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
772 MachineMemOperand::MOStore,
773 MFI.getObjectSize(FI),
776 switch (RC->getSize()) {
778 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
779 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
780 .addReg(SrcReg, getKillRegState(isKill))
781 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
782 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
783 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
784 .addReg(SrcReg, getKillRegState(isKill))
785 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
787 llvm_unreachable("Unknown reg class!");
790 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
791 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
792 .addReg(SrcReg, getKillRegState(isKill))
793 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
795 llvm_unreachable("Unknown reg class!");
798 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
799 // Use aligned spills if the stack can be realigned.
800 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
801 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
802 .addFrameIndex(FI).addImm(16)
803 .addReg(SrcReg, getKillRegState(isKill))
804 .addMemOperand(MMO));
806 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
807 .addReg(SrcReg, getKillRegState(isKill))
809 .addMemOperand(MMO));
812 llvm_unreachable("Unknown reg class!");
815 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
816 // Use aligned spills if the stack can be realigned.
817 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
818 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
819 .addFrameIndex(FI).addImm(16)
820 .addReg(SrcReg, getKillRegState(isKill))
821 .addMemOperand(MMO));
823 MachineInstrBuilder MIB =
824 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
827 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
828 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
829 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
832 llvm_unreachable("Unknown reg class!");
835 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
836 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
837 // FIXME: It's possible to only store part of the QQ register if the
838 // spilled def has a sub-register index.
839 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
840 .addFrameIndex(FI).addImm(16)
841 .addReg(SrcReg, getKillRegState(isKill))
842 .addMemOperand(MMO));
844 MachineInstrBuilder MIB =
845 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
851 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
854 llvm_unreachable("Unknown reg class!");
857 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
858 MachineInstrBuilder MIB =
859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
862 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
863 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
864 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
865 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
866 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
867 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
868 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
869 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
871 llvm_unreachable("Unknown reg class!");
874 llvm_unreachable("Unknown reg class!");
879 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
880 int &FrameIndex) const {
881 switch (MI->getOpcode()) {
884 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
885 if (MI->getOperand(1).isFI() &&
886 MI->getOperand(2).isReg() &&
887 MI->getOperand(3).isImm() &&
888 MI->getOperand(2).getReg() == 0 &&
889 MI->getOperand(3).getImm() == 0) {
890 FrameIndex = MI->getOperand(1).getIndex();
891 return MI->getOperand(0).getReg();
899 if (MI->getOperand(1).isFI() &&
900 MI->getOperand(2).isImm() &&
901 MI->getOperand(2).getImm() == 0) {
902 FrameIndex = MI->getOperand(1).getIndex();
903 return MI->getOperand(0).getReg();
907 case ARM::VST1d64TPseudo:
908 case ARM::VST1d64QPseudo:
909 if (MI->getOperand(0).isFI() &&
910 MI->getOperand(2).getSubReg() == 0) {
911 FrameIndex = MI->getOperand(0).getIndex();
912 return MI->getOperand(2).getReg();
916 if (MI->getOperand(1).isFI() &&
917 MI->getOperand(0).getSubReg() == 0) {
918 FrameIndex = MI->getOperand(1).getIndex();
919 return MI->getOperand(0).getReg();
927 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
928 int &FrameIndex) const {
929 const MachineMemOperand *Dummy;
930 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
933 void ARMBaseInstrInfo::
934 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
935 unsigned DestReg, int FI,
936 const TargetRegisterClass *RC,
937 const TargetRegisterInfo *TRI) const {
939 if (I != MBB.end()) DL = I->getDebugLoc();
940 MachineFunction &MF = *MBB.getParent();
941 MachineFrameInfo &MFI = *MF.getFrameInfo();
942 unsigned Align = MFI.getObjectAlignment(FI);
943 MachineMemOperand *MMO =
944 MF.getMachineMemOperand(
945 MachinePointerInfo::getFixedStack(FI),
946 MachineMemOperand::MOLoad,
947 MFI.getObjectSize(FI),
950 switch (RC->getSize()) {
952 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
953 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
954 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
956 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
957 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
958 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
960 llvm_unreachable("Unknown reg class!");
963 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
964 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
965 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
967 llvm_unreachable("Unknown reg class!");
970 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
971 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
972 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
973 .addFrameIndex(FI).addImm(16)
974 .addMemOperand(MMO));
976 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
978 .addMemOperand(MMO));
981 llvm_unreachable("Unknown reg class!");
984 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
985 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
986 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
987 .addFrameIndex(FI).addImm(16)
988 .addMemOperand(MMO));
990 MachineInstrBuilder MIB =
991 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
993 .addMemOperand(MMO));
994 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
995 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
996 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
997 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
998 MIB.addReg(DestReg, RegState::ImplicitDefine);
1001 llvm_unreachable("Unknown reg class!");
1004 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1005 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1006 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1007 .addFrameIndex(FI).addImm(16)
1008 .addMemOperand(MMO));
1010 MachineInstrBuilder MIB =
1011 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1013 .addMemOperand(MMO);
1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1018 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1019 MIB.addReg(DestReg, RegState::ImplicitDefine);
1022 llvm_unreachable("Unknown reg class!");
1025 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1026 MachineInstrBuilder MIB =
1027 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1029 .addMemOperand(MMO);
1030 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1031 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1032 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1033 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1034 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1035 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1036 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1037 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1038 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1039 MIB.addReg(DestReg, RegState::ImplicitDefine);
1041 llvm_unreachable("Unknown reg class!");
1044 llvm_unreachable("Unknown regclass!");
1049 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1050 int &FrameIndex) const {
1051 switch (MI->getOpcode()) {
1054 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1055 if (MI->getOperand(1).isFI() &&
1056 MI->getOperand(2).isReg() &&
1057 MI->getOperand(3).isImm() &&
1058 MI->getOperand(2).getReg() == 0 &&
1059 MI->getOperand(3).getImm() == 0) {
1060 FrameIndex = MI->getOperand(1).getIndex();
1061 return MI->getOperand(0).getReg();
1069 if (MI->getOperand(1).isFI() &&
1070 MI->getOperand(2).isImm() &&
1071 MI->getOperand(2).getImm() == 0) {
1072 FrameIndex = MI->getOperand(1).getIndex();
1073 return MI->getOperand(0).getReg();
1077 case ARM::VLD1d64TPseudo:
1078 case ARM::VLD1d64QPseudo:
1079 if (MI->getOperand(1).isFI() &&
1080 MI->getOperand(0).getSubReg() == 0) {
1081 FrameIndex = MI->getOperand(1).getIndex();
1082 return MI->getOperand(0).getReg();
1086 if (MI->getOperand(1).isFI() &&
1087 MI->getOperand(0).getSubReg() == 0) {
1088 FrameIndex = MI->getOperand(1).getIndex();
1089 return MI->getOperand(0).getReg();
1097 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1098 int &FrameIndex) const {
1099 const MachineMemOperand *Dummy;
1100 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1103 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1104 // This hook gets to expand COPY instructions before they become
1105 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1106 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1107 // changed into a VORR that can go down the NEON pipeline.
1108 if (!WidenVMOVS || !MI->isCopy())
1111 // Look for a copy between even S-registers. That is where we keep floats
1112 // when using NEON v2f32 instructions for f32 arithmetic.
1113 unsigned DstRegS = MI->getOperand(0).getReg();
1114 unsigned SrcRegS = MI->getOperand(1).getReg();
1115 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1118 const TargetRegisterInfo *TRI = &getRegisterInfo();
1119 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1121 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1123 if (!DstRegD || !SrcRegD)
1126 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1127 // legal if the COPY already defines the full DstRegD, and it isn't a
1128 // sub-register insertion.
1129 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1132 // A dead copy shouldn't show up here, but reject it just in case.
1133 if (MI->getOperand(0).isDead())
1136 // All clear, widen the COPY.
1137 DEBUG(dbgs() << "widening: " << *MI);
1139 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1140 // or some other super-register.
1141 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1142 if (ImpDefIdx != -1)
1143 MI->RemoveOperand(ImpDefIdx);
1145 // Change the opcode and operands.
1146 MI->setDesc(get(ARM::VMOVD));
1147 MI->getOperand(0).setReg(DstRegD);
1148 MI->getOperand(1).setReg(SrcRegD);
1149 AddDefaultPred(MachineInstrBuilder(MI));
1151 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1152 // register scavenger and machine verifier, so we need to indicate that we
1153 // are reading an undefined value from SrcRegD, but a proper value from
1155 MI->getOperand(1).setIsUndef();
1156 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1158 // SrcRegD may actually contain an unrelated value in the ssub_1
1159 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1160 if (MI->getOperand(1).isKill()) {
1161 MI->getOperand(1).setIsKill(false);
1162 MI->addRegisterKilled(SrcRegS, TRI, true);
1165 DEBUG(dbgs() << "replaced by: " << *MI);
1170 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1171 int FrameIx, uint64_t Offset,
1172 const MDNode *MDPtr,
1173 DebugLoc DL) const {
1174 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1175 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1179 /// Create a copy of a const pool value. Update CPI to the new index and return
1181 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1182 MachineConstantPool *MCP = MF.getConstantPool();
1183 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1185 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1186 assert(MCPE.isMachineConstantPoolEntry() &&
1187 "Expecting a machine constantpool entry!");
1188 ARMConstantPoolValue *ACPV =
1189 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1191 unsigned PCLabelId = AFI->createPICLabelUId();
1192 ARMConstantPoolValue *NewCPV = 0;
1193 // FIXME: The below assumes PIC relocation model and that the function
1194 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1195 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1196 // instructions, so that's probably OK, but is PIC always correct when
1198 if (ACPV->isGlobalValue())
1199 NewCPV = ARMConstantPoolConstant::
1200 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1202 else if (ACPV->isExtSymbol())
1203 NewCPV = ARMConstantPoolSymbol::
1204 Create(MF.getFunction()->getContext(),
1205 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1206 else if (ACPV->isBlockAddress())
1207 NewCPV = ARMConstantPoolConstant::
1208 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1209 ARMCP::CPBlockAddress, 4);
1210 else if (ACPV->isLSDA())
1211 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1213 else if (ACPV->isMachineBasicBlock())
1214 NewCPV = ARMConstantPoolMBB::
1215 Create(MF.getFunction()->getContext(),
1216 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1218 llvm_unreachable("Unexpected ARM constantpool value type!!");
1219 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1223 void ARMBaseInstrInfo::
1224 reMaterialize(MachineBasicBlock &MBB,
1225 MachineBasicBlock::iterator I,
1226 unsigned DestReg, unsigned SubIdx,
1227 const MachineInstr *Orig,
1228 const TargetRegisterInfo &TRI) const {
1229 unsigned Opcode = Orig->getOpcode();
1232 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1233 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1237 case ARM::tLDRpci_pic:
1238 case ARM::t2LDRpci_pic: {
1239 MachineFunction &MF = *MBB.getParent();
1240 unsigned CPI = Orig->getOperand(1).getIndex();
1241 unsigned PCLabelId = duplicateCPV(MF, CPI);
1242 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1244 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1245 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1252 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1253 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1254 switch(Orig->getOpcode()) {
1255 case ARM::tLDRpci_pic:
1256 case ARM::t2LDRpci_pic: {
1257 unsigned CPI = Orig->getOperand(1).getIndex();
1258 unsigned PCLabelId = duplicateCPV(MF, CPI);
1259 Orig->getOperand(1).setIndex(CPI);
1260 Orig->getOperand(2).setImm(PCLabelId);
1267 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1268 const MachineInstr *MI1,
1269 const MachineRegisterInfo *MRI) const {
1270 int Opcode = MI0->getOpcode();
1271 if (Opcode == ARM::t2LDRpci ||
1272 Opcode == ARM::t2LDRpci_pic ||
1273 Opcode == ARM::tLDRpci ||
1274 Opcode == ARM::tLDRpci_pic ||
1275 Opcode == ARM::MOV_ga_dyn ||
1276 Opcode == ARM::MOV_ga_pcrel ||
1277 Opcode == ARM::MOV_ga_pcrel_ldr ||
1278 Opcode == ARM::t2MOV_ga_dyn ||
1279 Opcode == ARM::t2MOV_ga_pcrel) {
1280 if (MI1->getOpcode() != Opcode)
1282 if (MI0->getNumOperands() != MI1->getNumOperands())
1285 const MachineOperand &MO0 = MI0->getOperand(1);
1286 const MachineOperand &MO1 = MI1->getOperand(1);
1287 if (MO0.getOffset() != MO1.getOffset())
1290 if (Opcode == ARM::MOV_ga_dyn ||
1291 Opcode == ARM::MOV_ga_pcrel ||
1292 Opcode == ARM::MOV_ga_pcrel_ldr ||
1293 Opcode == ARM::t2MOV_ga_dyn ||
1294 Opcode == ARM::t2MOV_ga_pcrel)
1295 // Ignore the PC labels.
1296 return MO0.getGlobal() == MO1.getGlobal();
1298 const MachineFunction *MF = MI0->getParent()->getParent();
1299 const MachineConstantPool *MCP = MF->getConstantPool();
1300 int CPI0 = MO0.getIndex();
1301 int CPI1 = MO1.getIndex();
1302 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1303 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1304 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1305 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1306 if (isARMCP0 && isARMCP1) {
1307 ARMConstantPoolValue *ACPV0 =
1308 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1309 ARMConstantPoolValue *ACPV1 =
1310 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1311 return ACPV0->hasSameValue(ACPV1);
1312 } else if (!isARMCP0 && !isARMCP1) {
1313 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1316 } else if (Opcode == ARM::PICLDR) {
1317 if (MI1->getOpcode() != Opcode)
1319 if (MI0->getNumOperands() != MI1->getNumOperands())
1322 unsigned Addr0 = MI0->getOperand(1).getReg();
1323 unsigned Addr1 = MI1->getOperand(1).getReg();
1324 if (Addr0 != Addr1) {
1326 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1327 !TargetRegisterInfo::isVirtualRegister(Addr1))
1330 // This assumes SSA form.
1331 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1332 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1333 // Check if the loaded value, e.g. a constantpool of a global address, are
1335 if (!produceSameValue(Def0, Def1, MRI))
1339 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1340 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1341 const MachineOperand &MO0 = MI0->getOperand(i);
1342 const MachineOperand &MO1 = MI1->getOperand(i);
1343 if (!MO0.isIdenticalTo(MO1))
1349 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1352 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1353 /// determine if two loads are loading from the same base address. It should
1354 /// only return true if the base pointers are the same and the only differences
1355 /// between the two addresses is the offset. It also returns the offsets by
1357 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1359 int64_t &Offset2) const {
1360 // Don't worry about Thumb: just ARM and Thumb2.
1361 if (Subtarget.isThumb1Only()) return false;
1363 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1366 switch (Load1->getMachineOpcode()) {
1379 case ARM::t2LDRSHi8:
1381 case ARM::t2LDRSHi12:
1385 switch (Load2->getMachineOpcode()) {
1397 case ARM::t2LDRSHi8:
1399 case ARM::t2LDRSHi12:
1403 // Check if base addresses and chain operands match.
1404 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1405 Load1->getOperand(4) != Load2->getOperand(4))
1408 // Index should be Reg0.
1409 if (Load1->getOperand(3) != Load2->getOperand(3))
1412 // Determine the offsets.
1413 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1414 isa<ConstantSDNode>(Load2->getOperand(1))) {
1415 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1416 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1423 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1424 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1425 /// be scheduled togther. On some targets if two loads are loading from
1426 /// addresses in the same cache line, it's better if they are scheduled
1427 /// together. This function takes two integers that represent the load offsets
1428 /// from the common base address. It returns true if it decides it's desirable
1429 /// to schedule the two loads together. "NumLoads" is the number of loads that
1430 /// have already been scheduled after Load1.
1431 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1432 int64_t Offset1, int64_t Offset2,
1433 unsigned NumLoads) const {
1434 // Don't worry about Thumb: just ARM and Thumb2.
1435 if (Subtarget.isThumb1Only()) return false;
1437 assert(Offset2 > Offset1);
1439 if ((Offset2 - Offset1) / 8 > 64)
1442 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1443 return false; // FIXME: overly conservative?
1445 // Four loads in a row should be sufficient.
1452 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1453 const MachineBasicBlock *MBB,
1454 const MachineFunction &MF) const {
1455 // Debug info is never a scheduling boundary. It's necessary to be explicit
1456 // due to the special treatment of IT instructions below, otherwise a
1457 // dbg_value followed by an IT will result in the IT instruction being
1458 // considered a scheduling hazard, which is wrong. It should be the actual
1459 // instruction preceding the dbg_value instruction(s), just like it is
1460 // when debug info is not present.
1461 if (MI->isDebugValue())
1464 // Terminators and labels can't be scheduled around.
1465 if (MI->isTerminator() || MI->isLabel())
1468 // Treat the start of the IT block as a scheduling boundary, but schedule
1469 // t2IT along with all instructions following it.
1470 // FIXME: This is a big hammer. But the alternative is to add all potential
1471 // true and anti dependencies to IT block instructions as implicit operands
1472 // to the t2IT instruction. The added compile time and complexity does not
1474 MachineBasicBlock::const_iterator I = MI;
1475 // Make sure to skip any dbg_value instructions
1476 while (++I != MBB->end() && I->isDebugValue())
1478 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1481 // Don't attempt to schedule around any instruction that defines
1482 // a stack-oriented pointer, as it's unlikely to be profitable. This
1483 // saves compile time, because it doesn't require every single
1484 // stack slot reference to depend on the instruction that does the
1486 // Calls don't actually change the stack pointer, even if they have imp-defs.
1487 // No ARM calling conventions change the stack pointer. (X86 calling
1488 // conventions sometimes do).
1489 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1495 bool ARMBaseInstrInfo::
1496 isProfitableToIfCvt(MachineBasicBlock &MBB,
1497 unsigned NumCycles, unsigned ExtraPredCycles,
1498 const BranchProbability &Probability) const {
1502 // Attempt to estimate the relative costs of predication versus branching.
1503 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1504 UnpredCost /= Probability.getDenominator();
1505 UnpredCost += 1; // The branch itself
1506 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1508 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1511 bool ARMBaseInstrInfo::
1512 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1513 unsigned TCycles, unsigned TExtra,
1514 MachineBasicBlock &FMBB,
1515 unsigned FCycles, unsigned FExtra,
1516 const BranchProbability &Probability) const {
1517 if (!TCycles || !FCycles)
1520 // Attempt to estimate the relative costs of predication versus branching.
1521 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1522 TUnpredCost /= Probability.getDenominator();
1524 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1525 unsigned FUnpredCost = Comp * FCycles;
1526 FUnpredCost /= Probability.getDenominator();
1528 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1529 UnpredCost += 1; // The branch itself
1530 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1532 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1536 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1537 MachineBasicBlock &FMBB) const {
1538 // Reduce false anti-dependencies to let Swift's out-of-order execution
1539 // engine do its thing.
1540 return Subtarget.isSwift();
1543 /// getInstrPredicate - If instruction is predicated, returns its predicate
1544 /// condition, otherwise returns AL. It also returns the condition code
1545 /// register by reference.
1547 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1548 int PIdx = MI->findFirstPredOperandIdx();
1554 PredReg = MI->getOperand(PIdx+1).getReg();
1555 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1559 int llvm::getMatchingCondBranchOpcode(int Opc) {
1564 if (Opc == ARM::t2B)
1567 llvm_unreachable("Unknown unconditional branch opcode!");
1570 /// commuteInstruction - Handle commutable instructions.
1572 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1573 switch (MI->getOpcode()) {
1575 case ARM::t2MOVCCr: {
1576 // MOVCC can be commuted by inverting the condition.
1577 unsigned PredReg = 0;
1578 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1579 // MOVCC AL can't be inverted. Shouldn't happen.
1580 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1582 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1585 // After swapping the MOVCC operands, also invert the condition.
1586 MI->getOperand(MI->findFirstPredOperandIdx())
1587 .setImm(ARMCC::getOppositeCondition(CC));
1591 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1594 /// Identify instructions that can be folded into a MOVCC instruction, and
1595 /// return the defining instruction.
1596 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1597 const MachineRegisterInfo &MRI,
1598 const TargetInstrInfo *TII) {
1599 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1601 if (!MRI.hasOneNonDBGUse(Reg))
1603 MachineInstr *MI = MRI.getVRegDef(Reg);
1606 // MI is folded into the MOVCC by predicating it.
1607 if (!MI->isPredicable())
1609 // Check if MI has any non-dead defs or physreg uses. This also detects
1610 // predicated instructions which will be reading CPSR.
1611 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1612 const MachineOperand &MO = MI->getOperand(i);
1613 // Reject frame index operands, PEI can't handle the predicated pseudos.
1614 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1618 // MI can't have any tied operands, that would conflict with predication.
1621 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1623 if (MO.isDef() && !MO.isDead())
1626 bool DontMoveAcrossStores = true;
1627 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1632 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1633 SmallVectorImpl<MachineOperand> &Cond,
1634 unsigned &TrueOp, unsigned &FalseOp,
1635 bool &Optimizable) const {
1636 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1637 "Unknown select instruction");
1642 // 3: Condition code.
1646 Cond.push_back(MI->getOperand(3));
1647 Cond.push_back(MI->getOperand(4));
1648 // We can always fold a def.
1653 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1654 bool PreferFalse) const {
1655 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1656 "Unknown select instruction");
1657 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1658 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1659 bool Invert = !DefMI;
1661 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1665 // Create a new predicated version of DefMI.
1666 // Rfalse is the first use.
1667 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1669 MI->getOperand(0).getReg());
1671 // Copy all the DefMI operands, excluding its (null) predicate.
1672 const MCInstrDesc &DefDesc = DefMI->getDesc();
1673 for (unsigned i = 1, e = DefDesc.getNumOperands();
1674 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1675 NewMI.addOperand(DefMI->getOperand(i));
1677 unsigned CondCode = MI->getOperand(3).getImm();
1679 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1681 NewMI.addImm(CondCode);
1682 NewMI.addOperand(MI->getOperand(4));
1684 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1685 if (NewMI->hasOptionalDef())
1686 AddDefaultCC(NewMI);
1688 // The output register value when the predicate is false is an implicit
1689 // register operand tied to the first def.
1690 // The tie makes the register allocator ensure the FalseReg is allocated the
1691 // same register as operand 0.
1692 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1693 FalseReg.setImplicit();
1694 NewMI->addOperand(FalseReg);
1695 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1697 // The caller will erase MI, but not DefMI.
1698 DefMI->eraseFromParent();
1702 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1703 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1706 /// This will go away once we can teach tblgen how to set the optional CPSR def
1708 struct AddSubFlagsOpcodePair {
1710 uint16_t MachineOpc;
1713 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1714 {ARM::ADDSri, ARM::ADDri},
1715 {ARM::ADDSrr, ARM::ADDrr},
1716 {ARM::ADDSrsi, ARM::ADDrsi},
1717 {ARM::ADDSrsr, ARM::ADDrsr},
1719 {ARM::SUBSri, ARM::SUBri},
1720 {ARM::SUBSrr, ARM::SUBrr},
1721 {ARM::SUBSrsi, ARM::SUBrsi},
1722 {ARM::SUBSrsr, ARM::SUBrsr},
1724 {ARM::RSBSri, ARM::RSBri},
1725 {ARM::RSBSrsi, ARM::RSBrsi},
1726 {ARM::RSBSrsr, ARM::RSBrsr},
1728 {ARM::t2ADDSri, ARM::t2ADDri},
1729 {ARM::t2ADDSrr, ARM::t2ADDrr},
1730 {ARM::t2ADDSrs, ARM::t2ADDrs},
1732 {ARM::t2SUBSri, ARM::t2SUBri},
1733 {ARM::t2SUBSrr, ARM::t2SUBrr},
1734 {ARM::t2SUBSrs, ARM::t2SUBrs},
1736 {ARM::t2RSBSri, ARM::t2RSBri},
1737 {ARM::t2RSBSrs, ARM::t2RSBrs},
1740 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1741 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1742 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1743 return AddSubFlagsOpcodeMap[i].MachineOpc;
1747 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1748 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1749 unsigned DestReg, unsigned BaseReg, int NumBytes,
1750 ARMCC::CondCodes Pred, unsigned PredReg,
1751 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1752 bool isSub = NumBytes < 0;
1753 if (isSub) NumBytes = -NumBytes;
1756 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1757 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1758 assert(ThisVal && "Didn't extract field correctly");
1760 // We will handle these bits from offset, clear them.
1761 NumBytes &= ~ThisVal;
1763 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1765 // Build the new ADD / SUB.
1766 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1767 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1768 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1769 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1770 .setMIFlags(MIFlags);
1775 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1776 unsigned FrameReg, int &Offset,
1777 const ARMBaseInstrInfo &TII) {
1778 unsigned Opcode = MI.getOpcode();
1779 const MCInstrDesc &Desc = MI.getDesc();
1780 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1783 // Memory operands in inline assembly always use AddrMode2.
1784 if (Opcode == ARM::INLINEASM)
1785 AddrMode = ARMII::AddrMode2;
1787 if (Opcode == ARM::ADDri) {
1788 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1790 // Turn it into a move.
1791 MI.setDesc(TII.get(ARM::MOVr));
1792 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1793 MI.RemoveOperand(FrameRegIdx+1);
1796 } else if (Offset < 0) {
1799 MI.setDesc(TII.get(ARM::SUBri));
1802 // Common case: small offset, fits into instruction.
1803 if (ARM_AM::getSOImmVal(Offset) != -1) {
1804 // Replace the FrameIndex with sp / fp
1805 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1806 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1811 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1813 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1814 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1816 // We will handle these bits from offset, clear them.
1817 Offset &= ~ThisImmVal;
1819 // Get the properly encoded SOImmVal field.
1820 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1821 "Bit extraction didn't work?");
1822 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1824 unsigned ImmIdx = 0;
1826 unsigned NumBits = 0;
1829 case ARMII::AddrMode_i12: {
1830 ImmIdx = FrameRegIdx + 1;
1831 InstrOffs = MI.getOperand(ImmIdx).getImm();
1835 case ARMII::AddrMode2: {
1836 ImmIdx = FrameRegIdx+2;
1837 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1838 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1843 case ARMII::AddrMode3: {
1844 ImmIdx = FrameRegIdx+2;
1845 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1846 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1851 case ARMII::AddrMode4:
1852 case ARMII::AddrMode6:
1853 // Can't fold any offset even if it's zero.
1855 case ARMII::AddrMode5: {
1856 ImmIdx = FrameRegIdx+1;
1857 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1858 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1865 llvm_unreachable("Unsupported addressing mode!");
1868 Offset += InstrOffs * Scale;
1869 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1875 // Attempt to fold address comp. if opcode has offset bits
1877 // Common case: small offset, fits into instruction.
1878 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1879 int ImmedOffset = Offset / Scale;
1880 unsigned Mask = (1 << NumBits) - 1;
1881 if ((unsigned)Offset <= Mask * Scale) {
1882 // Replace the FrameIndex with sp
1883 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1884 // FIXME: When addrmode2 goes away, this will simplify (like the
1885 // T2 version), as the LDR.i12 versions don't need the encoding
1886 // tricks for the offset value.
1888 if (AddrMode == ARMII::AddrMode_i12)
1889 ImmedOffset = -ImmedOffset;
1891 ImmedOffset |= 1 << NumBits;
1893 ImmOp.ChangeToImmediate(ImmedOffset);
1898 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1899 ImmedOffset = ImmedOffset & Mask;
1901 if (AddrMode == ARMII::AddrMode_i12)
1902 ImmedOffset = -ImmedOffset;
1904 ImmedOffset |= 1 << NumBits;
1906 ImmOp.ChangeToImmediate(ImmedOffset);
1907 Offset &= ~(Mask*Scale);
1911 Offset = (isSub) ? -Offset : Offset;
1915 /// analyzeCompare - For a comparison instruction, return the source registers
1916 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1917 /// compares against in CmpValue. Return true if the comparison instruction
1918 /// can be analyzed.
1919 bool ARMBaseInstrInfo::
1920 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1921 int &CmpMask, int &CmpValue) const {
1922 switch (MI->getOpcode()) {
1926 SrcReg = MI->getOperand(0).getReg();
1929 CmpValue = MI->getOperand(1).getImm();
1933 SrcReg = MI->getOperand(0).getReg();
1934 SrcReg2 = MI->getOperand(1).getReg();
1940 SrcReg = MI->getOperand(0).getReg();
1942 CmpMask = MI->getOperand(1).getImm();
1950 /// isSuitableForMask - Identify a suitable 'and' instruction that
1951 /// operates on the given source register and applies the same mask
1952 /// as a 'tst' instruction. Provide a limited look-through for copies.
1953 /// When successful, MI will hold the found instruction.
1954 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1955 int CmpMask, bool CommonUse) {
1956 switch (MI->getOpcode()) {
1959 if (CmpMask != MI->getOperand(2).getImm())
1961 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1965 // Walk down one instruction which is potentially an 'and'.
1966 const MachineInstr &Copy = *MI;
1967 MachineBasicBlock::iterator AND(
1968 llvm::next(MachineBasicBlock::iterator(MI)));
1969 if (AND == MI->getParent()->end()) return false;
1971 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1979 /// getSwappedCondition - assume the flags are set by MI(a,b), return
1980 /// the condition code if we modify the instructions such that flags are
1982 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
1984 default: return ARMCC::AL;
1985 case ARMCC::EQ: return ARMCC::EQ;
1986 case ARMCC::NE: return ARMCC::NE;
1987 case ARMCC::HS: return ARMCC::LS;
1988 case ARMCC::LO: return ARMCC::HI;
1989 case ARMCC::HI: return ARMCC::LO;
1990 case ARMCC::LS: return ARMCC::HS;
1991 case ARMCC::GE: return ARMCC::LE;
1992 case ARMCC::LT: return ARMCC::GT;
1993 case ARMCC::GT: return ARMCC::LT;
1994 case ARMCC::LE: return ARMCC::GE;
1998 /// isRedundantFlagInstr - check whether the first instruction, whose only
1999 /// purpose is to update flags, can be made redundant.
2000 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2001 /// CMPri can be made redundant by SUBri if the operands are the same.
2002 /// This function can be extended later on.
2003 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2004 unsigned SrcReg2, int ImmValue,
2006 if ((CmpI->getOpcode() == ARM::CMPrr ||
2007 CmpI->getOpcode() == ARM::t2CMPrr) &&
2008 (OI->getOpcode() == ARM::SUBrr ||
2009 OI->getOpcode() == ARM::t2SUBrr) &&
2010 ((OI->getOperand(1).getReg() == SrcReg &&
2011 OI->getOperand(2).getReg() == SrcReg2) ||
2012 (OI->getOperand(1).getReg() == SrcReg2 &&
2013 OI->getOperand(2).getReg() == SrcReg)))
2016 if ((CmpI->getOpcode() == ARM::CMPri ||
2017 CmpI->getOpcode() == ARM::t2CMPri) &&
2018 (OI->getOpcode() == ARM::SUBri ||
2019 OI->getOpcode() == ARM::t2SUBri) &&
2020 OI->getOperand(1).getReg() == SrcReg &&
2021 OI->getOperand(2).getImm() == ImmValue)
2026 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2027 /// comparison into one that sets the zero bit in the flags register;
2028 /// Remove a redundant Compare instruction if an earlier instruction can set the
2029 /// flags in the same way as Compare.
2030 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2031 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2032 /// condition code of instructions which use the flags.
2033 bool ARMBaseInstrInfo::
2034 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2035 int CmpMask, int CmpValue,
2036 const MachineRegisterInfo *MRI) const {
2037 // Get the unique definition of SrcReg.
2038 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2039 if (!MI) return false;
2041 // Masked compares sometimes use the same register as the corresponding 'and'.
2042 if (CmpMask != ~0) {
2043 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2045 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2046 UE = MRI->use_end(); UI != UE; ++UI) {
2047 if (UI->getParent() != CmpInstr->getParent()) continue;
2048 MachineInstr *PotentialAND = &*UI;
2049 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2050 isPredicated(PotentialAND))
2055 if (!MI) return false;
2059 // Get ready to iterate backward from CmpInstr.
2060 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2061 B = CmpInstr->getParent()->begin();
2063 // Early exit if CmpInstr is at the beginning of the BB.
2064 if (I == B) return false;
2066 // There are two possible candidates which can be changed to set CPSR:
2067 // One is MI, the other is a SUB instruction.
2068 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2069 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2070 MachineInstr *Sub = NULL;
2072 // MI is not a candidate for CMPrr.
2074 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2075 // Conservatively refuse to convert an instruction which isn't in the same
2076 // BB as the comparison.
2077 // For CMPri, we need to check Sub, thus we can't return here.
2078 if (CmpInstr->getOpcode() == ARM::CMPri ||
2079 CmpInstr->getOpcode() == ARM::t2CMPri)
2085 // Check that CPSR isn't set between the comparison instruction and the one we
2086 // want to change. At the same time, search for Sub.
2087 const TargetRegisterInfo *TRI = &getRegisterInfo();
2089 for (; I != E; --I) {
2090 const MachineInstr &Instr = *I;
2092 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2093 Instr.readsRegister(ARM::CPSR, TRI))
2094 // This instruction modifies or uses CPSR after the one we want to
2095 // change. We can't do this transformation.
2098 // Check whether CmpInstr can be made redundant by the current instruction.
2099 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2105 // The 'and' is below the comparison instruction.
2109 // Return false if no candidates exist.
2113 // The single candidate is called MI.
2116 // We can't use a predicated instruction - it doesn't always write the flags.
2117 if (isPredicated(MI))
2120 switch (MI->getOpcode()) {
2154 case ARM::t2EORri: {
2155 // Scan forward for the use of CPSR
2156 // When checking against MI: if it's a conditional code requires
2157 // checking of V bit, then this is not safe to do.
2158 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2159 // If we are done with the basic block, we need to check whether CPSR is
2161 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2163 bool isSafe = false;
2165 E = CmpInstr->getParent()->end();
2166 while (!isSafe && ++I != E) {
2167 const MachineInstr &Instr = *I;
2168 for (unsigned IO = 0, EO = Instr.getNumOperands();
2169 !isSafe && IO != EO; ++IO) {
2170 const MachineOperand &MO = Instr.getOperand(IO);
2171 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2175 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2181 // Condition code is after the operand before CPSR.
2182 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2184 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2185 if (NewCC == ARMCC::AL)
2187 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2188 // on CMP needs to be updated to be based on SUB.
2189 // Push the condition code operands to OperandsToUpdate.
2190 // If it is safe to remove CmpInstr, the condition code of these
2191 // operands will be modified.
2192 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2193 Sub->getOperand(2).getReg() == SrcReg)
2194 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2200 // CPSR can be used multiple times, we should continue.
2213 // If CPSR is not killed nor re-defined, we should check whether it is
2214 // live-out. If it is live-out, do not optimize.
2216 MachineBasicBlock *MBB = CmpInstr->getParent();
2217 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2218 SE = MBB->succ_end(); SI != SE; ++SI)
2219 if ((*SI)->isLiveIn(ARM::CPSR))
2223 // Toggle the optional operand to CPSR.
2224 MI->getOperand(5).setReg(ARM::CPSR);
2225 MI->getOperand(5).setIsDef(true);
2226 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2227 CmpInstr->eraseFromParent();
2229 // Modify the condition code of operands in OperandsToUpdate.
2230 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2231 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2232 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2233 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2241 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2242 MachineInstr *DefMI, unsigned Reg,
2243 MachineRegisterInfo *MRI) const {
2244 // Fold large immediates into add, sub, or, xor.
2245 unsigned DefOpc = DefMI->getOpcode();
2246 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2248 if (!DefMI->getOperand(1).isImm())
2249 // Could be t2MOVi32imm <ga:xx>
2252 if (!MRI->hasOneNonDBGUse(Reg))
2255 const MCInstrDesc &DefMCID = DefMI->getDesc();
2256 if (DefMCID.hasOptionalDef()) {
2257 unsigned NumOps = DefMCID.getNumOperands();
2258 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2259 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2260 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2265 const MCInstrDesc &UseMCID = UseMI->getDesc();
2266 if (UseMCID.hasOptionalDef()) {
2267 unsigned NumOps = UseMCID.getNumOperands();
2268 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2269 // If the instruction sets the flag, do not attempt this optimization
2270 // since it may change the semantics of the code.
2274 unsigned UseOpc = UseMI->getOpcode();
2275 unsigned NewUseOpc = 0;
2276 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2277 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2278 bool Commute = false;
2280 default: return false;
2288 case ARM::t2EORrr: {
2289 Commute = UseMI->getOperand(2).getReg() != Reg;
2296 NewUseOpc = ARM::SUBri;
2302 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2304 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2305 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2308 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2309 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2310 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2314 case ARM::t2SUBrr: {
2318 NewUseOpc = ARM::t2SUBri;
2323 case ARM::t2EORrr: {
2324 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2326 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2327 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2330 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2331 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2332 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2340 unsigned OpIdx = Commute ? 2 : 1;
2341 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2342 bool isKill = UseMI->getOperand(OpIdx).isKill();
2343 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2344 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2345 UseMI, UseMI->getDebugLoc(),
2346 get(NewUseOpc), NewReg)
2347 .addReg(Reg1, getKillRegState(isKill))
2348 .addImm(SOImmValV1)));
2349 UseMI->setDesc(get(NewUseOpc));
2350 UseMI->getOperand(1).setReg(NewReg);
2351 UseMI->getOperand(1).setIsKill();
2352 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2353 DefMI->eraseFromParent();
2357 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2358 const MachineInstr *MI) {
2359 switch (MI->getOpcode()) {
2361 const MCInstrDesc &Desc = MI->getDesc();
2362 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2363 assert(UOps >= 0 && "bad # UOps");
2371 unsigned ShOpVal = MI->getOperand(3).getImm();
2372 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2373 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2376 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2377 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2384 if (!MI->getOperand(2).getReg())
2387 unsigned ShOpVal = MI->getOperand(3).getImm();
2388 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2389 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2392 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2393 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2400 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2402 case ARM::LDRSB_POST:
2403 case ARM::LDRSH_POST: {
2404 unsigned Rt = MI->getOperand(0).getReg();
2405 unsigned Rm = MI->getOperand(3).getReg();
2406 return (Rt == Rm) ? 4 : 3;
2409 case ARM::LDR_PRE_REG:
2410 case ARM::LDRB_PRE_REG: {
2411 unsigned Rt = MI->getOperand(0).getReg();
2412 unsigned Rm = MI->getOperand(3).getReg();
2415 unsigned ShOpVal = MI->getOperand(4).getImm();
2416 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2417 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2420 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2421 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2426 case ARM::STR_PRE_REG:
2427 case ARM::STRB_PRE_REG: {
2428 unsigned ShOpVal = MI->getOperand(4).getImm();
2429 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2430 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2433 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2434 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2440 case ARM::STRH_PRE: {
2441 unsigned Rt = MI->getOperand(0).getReg();
2442 unsigned Rm = MI->getOperand(3).getReg();
2447 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2451 case ARM::LDR_POST_REG:
2452 case ARM::LDRB_POST_REG:
2453 case ARM::LDRH_POST: {
2454 unsigned Rt = MI->getOperand(0).getReg();
2455 unsigned Rm = MI->getOperand(3).getReg();
2456 return (Rt == Rm) ? 3 : 2;
2459 case ARM::LDR_PRE_IMM:
2460 case ARM::LDRB_PRE_IMM:
2461 case ARM::LDR_POST_IMM:
2462 case ARM::LDRB_POST_IMM:
2463 case ARM::STRB_POST_IMM:
2464 case ARM::STRB_POST_REG:
2465 case ARM::STRB_PRE_IMM:
2466 case ARM::STRH_POST:
2467 case ARM::STR_POST_IMM:
2468 case ARM::STR_POST_REG:
2469 case ARM::STR_PRE_IMM:
2472 case ARM::LDRSB_PRE:
2473 case ARM::LDRSH_PRE: {
2474 unsigned Rm = MI->getOperand(3).getReg();
2477 unsigned Rt = MI->getOperand(0).getReg();
2480 unsigned ShOpVal = MI->getOperand(4).getImm();
2481 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2482 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2485 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2486 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2492 unsigned Rt = MI->getOperand(0).getReg();
2493 unsigned Rn = MI->getOperand(2).getReg();
2494 unsigned Rm = MI->getOperand(3).getReg();
2496 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2497 return (Rt == Rn) ? 3 : 2;
2501 unsigned Rm = MI->getOperand(3).getReg();
2503 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2507 case ARM::LDRD_POST:
2508 case ARM::t2LDRD_POST:
2511 case ARM::STRD_POST:
2512 case ARM::t2STRD_POST:
2515 case ARM::LDRD_PRE: {
2516 unsigned Rt = MI->getOperand(0).getReg();
2517 unsigned Rn = MI->getOperand(3).getReg();
2518 unsigned Rm = MI->getOperand(4).getReg();
2520 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2521 return (Rt == Rn) ? 4 : 3;
2524 case ARM::t2LDRD_PRE: {
2525 unsigned Rt = MI->getOperand(0).getReg();
2526 unsigned Rn = MI->getOperand(3).getReg();
2527 return (Rt == Rn) ? 4 : 3;
2530 case ARM::STRD_PRE: {
2531 unsigned Rm = MI->getOperand(4).getReg();
2533 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2537 case ARM::t2STRD_PRE:
2540 case ARM::t2LDR_POST:
2541 case ARM::t2LDRB_POST:
2542 case ARM::t2LDRB_PRE:
2543 case ARM::t2LDRSBi12:
2544 case ARM::t2LDRSBi8:
2545 case ARM::t2LDRSBpci:
2547 case ARM::t2LDRH_POST:
2548 case ARM::t2LDRH_PRE:
2550 case ARM::t2LDRSB_POST:
2551 case ARM::t2LDRSB_PRE:
2552 case ARM::t2LDRSH_POST:
2553 case ARM::t2LDRSH_PRE:
2554 case ARM::t2LDRSHi12:
2555 case ARM::t2LDRSHi8:
2556 case ARM::t2LDRSHpci:
2560 case ARM::t2LDRDi8: {
2561 unsigned Rt = MI->getOperand(0).getReg();
2562 unsigned Rn = MI->getOperand(2).getReg();
2563 return (Rt == Rn) ? 3 : 2;
2566 case ARM::t2STRB_POST:
2567 case ARM::t2STRB_PRE:
2570 case ARM::t2STRH_POST:
2571 case ARM::t2STRH_PRE:
2573 case ARM::t2STR_POST:
2574 case ARM::t2STR_PRE:
2580 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2581 // can't be easily determined return 0 (missing MachineMemOperand).
2583 // FIXME: The current MachineInstr design does not support relying on machine
2584 // mem operands to determine the width of a memory access. Instead, we expect
2585 // the target to provide this information based on the instruction opcode and
2586 // operands. However, using MachineMemOperand is a the best solution now for
2589 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2590 // operands. This is much more dangerous than using the MachineMemOperand
2591 // sizes because CodeGen passes can insert/remove optional machine operands. In
2592 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2593 // postRA passes as well.
2595 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2596 // machine model that calls this should handle the unknown (zero size) case.
2598 // Long term, we should require a target hook that verifies MachineMemOperand
2599 // sizes during MC lowering. That target hook should be local to MC lowering
2600 // because we can't ensure that it is aware of other MI forms. Doing this will
2601 // ensure that MachineMemOperands are correctly propagated through all passes.
2602 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2604 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2605 E = MI->memoperands_end(); I != E; ++I) {
2606 Size += (*I)->getSize();
2612 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2613 const MachineInstr *MI) const {
2614 if (!ItinData || ItinData->isEmpty())
2617 const MCInstrDesc &Desc = MI->getDesc();
2618 unsigned Class = Desc.getSchedClass();
2619 int ItinUOps = ItinData->getNumMicroOps(Class);
2620 if (ItinUOps >= 0) {
2621 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2622 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2627 unsigned Opc = MI->getOpcode();
2630 llvm_unreachable("Unexpected multi-uops instruction!");
2635 // The number of uOps for load / store multiple are determined by the number
2638 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2639 // same cycle. The scheduling for the first load / store must be done
2640 // separately by assuming the address is not 64-bit aligned.
2642 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2643 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2644 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2646 case ARM::VLDMDIA_UPD:
2647 case ARM::VLDMDDB_UPD:
2649 case ARM::VLDMSIA_UPD:
2650 case ARM::VLDMSDB_UPD:
2652 case ARM::VSTMDIA_UPD:
2653 case ARM::VSTMDDB_UPD:
2655 case ARM::VSTMSIA_UPD:
2656 case ARM::VSTMSDB_UPD: {
2657 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2658 return (NumRegs / 2) + (NumRegs % 2) + 1;
2661 case ARM::LDMIA_RET:
2666 case ARM::LDMIA_UPD:
2667 case ARM::LDMDA_UPD:
2668 case ARM::LDMDB_UPD:
2669 case ARM::LDMIB_UPD:
2674 case ARM::STMIA_UPD:
2675 case ARM::STMDA_UPD:
2676 case ARM::STMDB_UPD:
2677 case ARM::STMIB_UPD:
2679 case ARM::tLDMIA_UPD:
2680 case ARM::tSTMIA_UPD:
2684 case ARM::t2LDMIA_RET:
2687 case ARM::t2LDMIA_UPD:
2688 case ARM::t2LDMDB_UPD:
2691 case ARM::t2STMIA_UPD:
2692 case ARM::t2STMDB_UPD: {
2693 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2694 if (Subtarget.isSwift()) {
2696 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2699 case ARM::VLDMDIA_UPD:
2700 case ARM::VLDMDDB_UPD:
2701 case ARM::VLDMSIA_UPD:
2702 case ARM::VLDMSDB_UPD:
2703 case ARM::VSTMDIA_UPD:
2704 case ARM::VSTMDDB_UPD:
2705 case ARM::VSTMSIA_UPD:
2706 case ARM::VSTMSDB_UPD:
2707 case ARM::LDMIA_UPD:
2708 case ARM::LDMDA_UPD:
2709 case ARM::LDMDB_UPD:
2710 case ARM::LDMIB_UPD:
2711 case ARM::STMIA_UPD:
2712 case ARM::STMDA_UPD:
2713 case ARM::STMDB_UPD:
2714 case ARM::STMIB_UPD:
2715 case ARM::tLDMIA_UPD:
2716 case ARM::tSTMIA_UPD:
2717 case ARM::t2LDMIA_UPD:
2718 case ARM::t2LDMDB_UPD:
2719 case ARM::t2STMIA_UPD:
2720 case ARM::t2STMDB_UPD:
2721 ++UOps; // One for base register writeback.
2723 case ARM::LDMIA_RET:
2725 case ARM::t2LDMIA_RET:
2726 UOps += 2; // One for base reg wb, one for write to pc.
2730 } else if (Subtarget.isCortexA8()) {
2733 // 4 registers would be issued: 2, 2.
2734 // 5 registers would be issued: 2, 2, 1.
2735 int A8UOps = (NumRegs / 2);
2739 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2740 int A9UOps = (NumRegs / 2);
2741 // If there are odd number of registers or if it's not 64-bit aligned,
2742 // then it takes an extra AGU (Address Generation Unit) cycle.
2743 if ((NumRegs % 2) ||
2744 !MI->hasOneMemOperand() ||
2745 (*MI->memoperands_begin())->getAlignment() < 8)
2749 // Assume the worst.
2757 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2758 const MCInstrDesc &DefMCID,
2760 unsigned DefIdx, unsigned DefAlign) const {
2761 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2763 // Def is the address writeback.
2764 return ItinData->getOperandCycle(DefClass, DefIdx);
2767 if (Subtarget.isCortexA8()) {
2768 // (regno / 2) + (regno % 2) + 1
2769 DefCycle = RegNo / 2 + 1;
2772 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2774 bool isSLoad = false;
2776 switch (DefMCID.getOpcode()) {
2779 case ARM::VLDMSIA_UPD:
2780 case ARM::VLDMSDB_UPD:
2785 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2786 // then it takes an extra cycle.
2787 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2790 // Assume the worst.
2791 DefCycle = RegNo + 2;
2798 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2799 const MCInstrDesc &DefMCID,
2801 unsigned DefIdx, unsigned DefAlign) const {
2802 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2804 // Def is the address writeback.
2805 return ItinData->getOperandCycle(DefClass, DefIdx);
2808 if (Subtarget.isCortexA8()) {
2809 // 4 registers would be issued: 1, 2, 1.
2810 // 5 registers would be issued: 1, 2, 2.
2811 DefCycle = RegNo / 2;
2814 // Result latency is issue cycle + 2: E2.
2816 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2817 DefCycle = (RegNo / 2);
2818 // If there are odd number of registers or if it's not 64-bit aligned,
2819 // then it takes an extra AGU (Address Generation Unit) cycle.
2820 if ((RegNo % 2) || DefAlign < 8)
2822 // Result latency is AGU cycles + 2.
2825 // Assume the worst.
2826 DefCycle = RegNo + 2;
2833 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2834 const MCInstrDesc &UseMCID,
2836 unsigned UseIdx, unsigned UseAlign) const {
2837 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2839 return ItinData->getOperandCycle(UseClass, UseIdx);
2842 if (Subtarget.isCortexA8()) {
2843 // (regno / 2) + (regno % 2) + 1
2844 UseCycle = RegNo / 2 + 1;
2847 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2849 bool isSStore = false;
2851 switch (UseMCID.getOpcode()) {
2854 case ARM::VSTMSIA_UPD:
2855 case ARM::VSTMSDB_UPD:
2860 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2861 // then it takes an extra cycle.
2862 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2865 // Assume the worst.
2866 UseCycle = RegNo + 2;
2873 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2874 const MCInstrDesc &UseMCID,
2876 unsigned UseIdx, unsigned UseAlign) const {
2877 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2879 return ItinData->getOperandCycle(UseClass, UseIdx);
2882 if (Subtarget.isCortexA8()) {
2883 UseCycle = RegNo / 2;
2888 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2889 UseCycle = (RegNo / 2);
2890 // If there are odd number of registers or if it's not 64-bit aligned,
2891 // then it takes an extra AGU (Address Generation Unit) cycle.
2892 if ((RegNo % 2) || UseAlign < 8)
2895 // Assume the worst.
2902 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2903 const MCInstrDesc &DefMCID,
2904 unsigned DefIdx, unsigned DefAlign,
2905 const MCInstrDesc &UseMCID,
2906 unsigned UseIdx, unsigned UseAlign) const {
2907 unsigned DefClass = DefMCID.getSchedClass();
2908 unsigned UseClass = UseMCID.getSchedClass();
2910 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2911 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2913 // This may be a def / use of a variable_ops instruction, the operand
2914 // latency might be determinable dynamically. Let the target try to
2917 bool LdmBypass = false;
2918 switch (DefMCID.getOpcode()) {
2920 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2924 case ARM::VLDMDIA_UPD:
2925 case ARM::VLDMDDB_UPD:
2927 case ARM::VLDMSIA_UPD:
2928 case ARM::VLDMSDB_UPD:
2929 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2932 case ARM::LDMIA_RET:
2937 case ARM::LDMIA_UPD:
2938 case ARM::LDMDA_UPD:
2939 case ARM::LDMDB_UPD:
2940 case ARM::LDMIB_UPD:
2942 case ARM::tLDMIA_UPD:
2944 case ARM::t2LDMIA_RET:
2947 case ARM::t2LDMIA_UPD:
2948 case ARM::t2LDMDB_UPD:
2950 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2955 // We can't seem to determine the result latency of the def, assume it's 2.
2959 switch (UseMCID.getOpcode()) {
2961 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2965 case ARM::VSTMDIA_UPD:
2966 case ARM::VSTMDDB_UPD:
2968 case ARM::VSTMSIA_UPD:
2969 case ARM::VSTMSDB_UPD:
2970 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2977 case ARM::STMIA_UPD:
2978 case ARM::STMDA_UPD:
2979 case ARM::STMDB_UPD:
2980 case ARM::STMIB_UPD:
2981 case ARM::tSTMIA_UPD:
2986 case ARM::t2STMIA_UPD:
2987 case ARM::t2STMDB_UPD:
2988 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2993 // Assume it's read in the first stage.
2996 UseCycle = DefCycle - UseCycle + 1;
2999 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3000 // first def operand.
3001 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3004 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3005 UseClass, UseIdx)) {
3013 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3014 const MachineInstr *MI, unsigned Reg,
3015 unsigned &DefIdx, unsigned &Dist) {
3018 MachineBasicBlock::const_iterator I = MI; ++I;
3019 MachineBasicBlock::const_instr_iterator II =
3020 llvm::prior(I.getInstrIterator());
3021 assert(II->isInsideBundle() && "Empty bundle?");
3024 while (II->isInsideBundle()) {
3025 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3032 assert(Idx != -1 && "Cannot find bundled definition!");
3037 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3038 const MachineInstr *MI, unsigned Reg,
3039 unsigned &UseIdx, unsigned &Dist) {
3042 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3043 assert(II->isInsideBundle() && "Empty bundle?");
3044 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3046 // FIXME: This doesn't properly handle multiple uses.
3048 while (II != E && II->isInsideBundle()) {
3049 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3052 if (II->getOpcode() != ARM::t2IT)
3066 /// Return the number of cycles to add to (or subtract from) the static
3067 /// itinerary based on the def opcode and alignment. The caller will ensure that
3068 /// adjusted latency is at least one cycle.
3069 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3070 const MachineInstr *DefMI,
3071 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3073 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3074 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3075 // variants are one cycle cheaper.
3076 switch (DefMCID->getOpcode()) {
3080 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3081 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3083 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3090 case ARM::t2LDRSHs: {
3091 // Thumb2 mode: lsl only.
3092 unsigned ShAmt = DefMI->getOperand(3).getImm();
3093 if (ShAmt == 0 || ShAmt == 2)
3098 } else if (Subtarget.isSwift()) {
3099 // FIXME: Properly handle all of the latency adjustments for address
3101 switch (DefMCID->getOpcode()) {
3105 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3106 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3107 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3110 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3111 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3114 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3121 case ARM::t2LDRSHs: {
3122 // Thumb2 mode: lsl only.
3123 unsigned ShAmt = DefMI->getOperand(3).getImm();
3124 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3131 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3132 switch (DefMCID->getOpcode()) {
3138 case ARM::VLD1q8wb_fixed:
3139 case ARM::VLD1q16wb_fixed:
3140 case ARM::VLD1q32wb_fixed:
3141 case ARM::VLD1q64wb_fixed:
3142 case ARM::VLD1q8wb_register:
3143 case ARM::VLD1q16wb_register:
3144 case ARM::VLD1q32wb_register:
3145 case ARM::VLD1q64wb_register:
3152 case ARM::VLD2d8wb_fixed:
3153 case ARM::VLD2d16wb_fixed:
3154 case ARM::VLD2d32wb_fixed:
3155 case ARM::VLD2q8wb_fixed:
3156 case ARM::VLD2q16wb_fixed:
3157 case ARM::VLD2q32wb_fixed:
3158 case ARM::VLD2d8wb_register:
3159 case ARM::VLD2d16wb_register:
3160 case ARM::VLD2d32wb_register:
3161 case ARM::VLD2q8wb_register:
3162 case ARM::VLD2q16wb_register:
3163 case ARM::VLD2q32wb_register:
3168 case ARM::VLD3d8_UPD:
3169 case ARM::VLD3d16_UPD:
3170 case ARM::VLD3d32_UPD:
3171 case ARM::VLD1d64Twb_fixed:
3172 case ARM::VLD1d64Twb_register:
3173 case ARM::VLD3q8_UPD:
3174 case ARM::VLD3q16_UPD:
3175 case ARM::VLD3q32_UPD:
3180 case ARM::VLD4d8_UPD:
3181 case ARM::VLD4d16_UPD:
3182 case ARM::VLD4d32_UPD:
3183 case ARM::VLD1d64Qwb_fixed:
3184 case ARM::VLD1d64Qwb_register:
3185 case ARM::VLD4q8_UPD:
3186 case ARM::VLD4q16_UPD:
3187 case ARM::VLD4q32_UPD:
3188 case ARM::VLD1DUPq8:
3189 case ARM::VLD1DUPq16:
3190 case ARM::VLD1DUPq32:
3191 case ARM::VLD1DUPq8wb_fixed:
3192 case ARM::VLD1DUPq16wb_fixed:
3193 case ARM::VLD1DUPq32wb_fixed:
3194 case ARM::VLD1DUPq8wb_register:
3195 case ARM::VLD1DUPq16wb_register:
3196 case ARM::VLD1DUPq32wb_register:
3197 case ARM::VLD2DUPd8:
3198 case ARM::VLD2DUPd16:
3199 case ARM::VLD2DUPd32:
3200 case ARM::VLD2DUPd8wb_fixed:
3201 case ARM::VLD2DUPd16wb_fixed:
3202 case ARM::VLD2DUPd32wb_fixed:
3203 case ARM::VLD2DUPd8wb_register:
3204 case ARM::VLD2DUPd16wb_register:
3205 case ARM::VLD2DUPd32wb_register:
3206 case ARM::VLD4DUPd8:
3207 case ARM::VLD4DUPd16:
3208 case ARM::VLD4DUPd32:
3209 case ARM::VLD4DUPd8_UPD:
3210 case ARM::VLD4DUPd16_UPD:
3211 case ARM::VLD4DUPd32_UPD:
3213 case ARM::VLD1LNd16:
3214 case ARM::VLD1LNd32:
3215 case ARM::VLD1LNd8_UPD:
3216 case ARM::VLD1LNd16_UPD:
3217 case ARM::VLD1LNd32_UPD:
3219 case ARM::VLD2LNd16:
3220 case ARM::VLD2LNd32:
3221 case ARM::VLD2LNq16:
3222 case ARM::VLD2LNq32:
3223 case ARM::VLD2LNd8_UPD:
3224 case ARM::VLD2LNd16_UPD:
3225 case ARM::VLD2LNd32_UPD:
3226 case ARM::VLD2LNq16_UPD:
3227 case ARM::VLD2LNq32_UPD:
3229 case ARM::VLD4LNd16:
3230 case ARM::VLD4LNd32:
3231 case ARM::VLD4LNq16:
3232 case ARM::VLD4LNq32:
3233 case ARM::VLD4LNd8_UPD:
3234 case ARM::VLD4LNd16_UPD:
3235 case ARM::VLD4LNd32_UPD:
3236 case ARM::VLD4LNq16_UPD:
3237 case ARM::VLD4LNq32_UPD:
3238 // If the address is not 64-bit aligned, the latencies of these
3239 // instructions increases by one.
3250 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3251 const MachineInstr *DefMI, unsigned DefIdx,
3252 const MachineInstr *UseMI,
3253 unsigned UseIdx) const {
3254 // No operand latency. The caller may fall back to getInstrLatency.
3255 if (!ItinData || ItinData->isEmpty())
3258 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3259 unsigned Reg = DefMO.getReg();
3260 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3261 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3263 unsigned DefAdj = 0;
3264 if (DefMI->isBundle()) {
3265 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3266 DefMCID = &DefMI->getDesc();
3268 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3269 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3273 unsigned UseAdj = 0;
3274 if (UseMI->isBundle()) {
3276 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3277 Reg, NewUseIdx, UseAdj);
3283 UseMCID = &UseMI->getDesc();
3286 if (Reg == ARM::CPSR) {
3287 if (DefMI->getOpcode() == ARM::FMSTAT) {
3288 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3289 return Subtarget.isLikeA9() ? 1 : 20;
3292 // CPSR set and branch can be paired in the same cycle.
3293 if (UseMI->isBranch())
3296 // Otherwise it takes the instruction latency (generally one).
3297 unsigned Latency = getInstrLatency(ItinData, DefMI);
3299 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3300 // its uses. Instructions which are otherwise scheduled between them may
3301 // incur a code size penalty (not able to use the CPSR setting 16-bit
3303 if (Latency > 0 && Subtarget.isThumb2()) {
3304 const MachineFunction *MF = DefMI->getParent()->getParent();
3305 if (MF->getFunction()->getFnAttributes().
3306 hasAttribute(Attributes::OptimizeForSize))
3312 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3315 unsigned DefAlign = DefMI->hasOneMemOperand()
3316 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3317 unsigned UseAlign = UseMI->hasOneMemOperand()
3318 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3320 // Get the itinerary's latency if possible, and handle variable_ops.
3321 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3322 *UseMCID, UseIdx, UseAlign);
3323 // Unable to find operand latency. The caller may resort to getInstrLatency.
3327 // Adjust for IT block position.
3328 int Adj = DefAdj + UseAdj;
3330 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3331 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3332 if (Adj >= 0 || (int)Latency > -Adj) {
3333 return Latency + Adj;
3335 // Return the itinerary latency, which may be zero but not less than zero.
3340 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3341 SDNode *DefNode, unsigned DefIdx,
3342 SDNode *UseNode, unsigned UseIdx) const {
3343 if (!DefNode->isMachineOpcode())
3346 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3348 if (isZeroCost(DefMCID.Opcode))
3351 if (!ItinData || ItinData->isEmpty())
3352 return DefMCID.mayLoad() ? 3 : 1;
3354 if (!UseNode->isMachineOpcode()) {
3355 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3356 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3357 return Latency <= 2 ? 1 : Latency - 1;
3359 return Latency <= 3 ? 1 : Latency - 2;
3362 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3363 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3364 unsigned DefAlign = !DefMN->memoperands_empty()
3365 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3366 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3367 unsigned UseAlign = !UseMN->memoperands_empty()
3368 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3369 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3370 UseMCID, UseIdx, UseAlign);
3373 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3374 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3375 // variants are one cycle cheaper.
3376 switch (DefMCID.getOpcode()) {
3381 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3382 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3384 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3391 case ARM::t2LDRSHs: {
3392 // Thumb2 mode: lsl only.
3394 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3395 if (ShAmt == 0 || ShAmt == 2)
3400 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3401 // FIXME: Properly handle all of the latency adjustments for address
3403 switch (DefMCID.getOpcode()) {
3408 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3409 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3411 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3412 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3414 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3421 case ARM::t2LDRSHs: {
3422 // Thumb2 mode: lsl 0-3 only.
3429 if (DefAlign < 8 && Subtarget.isLikeA9())
3430 switch (DefMCID.getOpcode()) {
3436 case ARM::VLD1q8wb_register:
3437 case ARM::VLD1q16wb_register:
3438 case ARM::VLD1q32wb_register:
3439 case ARM::VLD1q64wb_register:
3440 case ARM::VLD1q8wb_fixed:
3441 case ARM::VLD1q16wb_fixed:
3442 case ARM::VLD1q32wb_fixed:
3443 case ARM::VLD1q64wb_fixed:
3447 case ARM::VLD2q8Pseudo:
3448 case ARM::VLD2q16Pseudo:
3449 case ARM::VLD2q32Pseudo:
3450 case ARM::VLD2d8wb_fixed:
3451 case ARM::VLD2d16wb_fixed:
3452 case ARM::VLD2d32wb_fixed:
3453 case ARM::VLD2q8PseudoWB_fixed:
3454 case ARM::VLD2q16PseudoWB_fixed:
3455 case ARM::VLD2q32PseudoWB_fixed:
3456 case ARM::VLD2d8wb_register:
3457 case ARM::VLD2d16wb_register:
3458 case ARM::VLD2d32wb_register:
3459 case ARM::VLD2q8PseudoWB_register:
3460 case ARM::VLD2q16PseudoWB_register:
3461 case ARM::VLD2q32PseudoWB_register:
3462 case ARM::VLD3d8Pseudo:
3463 case ARM::VLD3d16Pseudo:
3464 case ARM::VLD3d32Pseudo:
3465 case ARM::VLD1d64TPseudo:
3466 case ARM::VLD3d8Pseudo_UPD:
3467 case ARM::VLD3d16Pseudo_UPD:
3468 case ARM::VLD3d32Pseudo_UPD:
3469 case ARM::VLD3q8Pseudo_UPD:
3470 case ARM::VLD3q16Pseudo_UPD:
3471 case ARM::VLD3q32Pseudo_UPD:
3472 case ARM::VLD3q8oddPseudo:
3473 case ARM::VLD3q16oddPseudo:
3474 case ARM::VLD3q32oddPseudo:
3475 case ARM::VLD3q8oddPseudo_UPD:
3476 case ARM::VLD3q16oddPseudo_UPD:
3477 case ARM::VLD3q32oddPseudo_UPD:
3478 case ARM::VLD4d8Pseudo:
3479 case ARM::VLD4d16Pseudo:
3480 case ARM::VLD4d32Pseudo:
3481 case ARM::VLD1d64QPseudo:
3482 case ARM::VLD4d8Pseudo_UPD:
3483 case ARM::VLD4d16Pseudo_UPD:
3484 case ARM::VLD4d32Pseudo_UPD:
3485 case ARM::VLD4q8Pseudo_UPD:
3486 case ARM::VLD4q16Pseudo_UPD:
3487 case ARM::VLD4q32Pseudo_UPD:
3488 case ARM::VLD4q8oddPseudo:
3489 case ARM::VLD4q16oddPseudo:
3490 case ARM::VLD4q32oddPseudo:
3491 case ARM::VLD4q8oddPseudo_UPD:
3492 case ARM::VLD4q16oddPseudo_UPD:
3493 case ARM::VLD4q32oddPseudo_UPD:
3494 case ARM::VLD1DUPq8:
3495 case ARM::VLD1DUPq16:
3496 case ARM::VLD1DUPq32:
3497 case ARM::VLD1DUPq8wb_fixed:
3498 case ARM::VLD1DUPq16wb_fixed:
3499 case ARM::VLD1DUPq32wb_fixed:
3500 case ARM::VLD1DUPq8wb_register:
3501 case ARM::VLD1DUPq16wb_register:
3502 case ARM::VLD1DUPq32wb_register:
3503 case ARM::VLD2DUPd8:
3504 case ARM::VLD2DUPd16:
3505 case ARM::VLD2DUPd32:
3506 case ARM::VLD2DUPd8wb_fixed:
3507 case ARM::VLD2DUPd16wb_fixed:
3508 case ARM::VLD2DUPd32wb_fixed:
3509 case ARM::VLD2DUPd8wb_register:
3510 case ARM::VLD2DUPd16wb_register:
3511 case ARM::VLD2DUPd32wb_register:
3512 case ARM::VLD4DUPd8Pseudo:
3513 case ARM::VLD4DUPd16Pseudo:
3514 case ARM::VLD4DUPd32Pseudo:
3515 case ARM::VLD4DUPd8Pseudo_UPD:
3516 case ARM::VLD4DUPd16Pseudo_UPD:
3517 case ARM::VLD4DUPd32Pseudo_UPD:
3518 case ARM::VLD1LNq8Pseudo:
3519 case ARM::VLD1LNq16Pseudo:
3520 case ARM::VLD1LNq32Pseudo:
3521 case ARM::VLD1LNq8Pseudo_UPD:
3522 case ARM::VLD1LNq16Pseudo_UPD:
3523 case ARM::VLD1LNq32Pseudo_UPD:
3524 case ARM::VLD2LNd8Pseudo:
3525 case ARM::VLD2LNd16Pseudo:
3526 case ARM::VLD2LNd32Pseudo:
3527 case ARM::VLD2LNq16Pseudo:
3528 case ARM::VLD2LNq32Pseudo:
3529 case ARM::VLD2LNd8Pseudo_UPD:
3530 case ARM::VLD2LNd16Pseudo_UPD:
3531 case ARM::VLD2LNd32Pseudo_UPD:
3532 case ARM::VLD2LNq16Pseudo_UPD:
3533 case ARM::VLD2LNq32Pseudo_UPD:
3534 case ARM::VLD4LNd8Pseudo:
3535 case ARM::VLD4LNd16Pseudo:
3536 case ARM::VLD4LNd32Pseudo:
3537 case ARM::VLD4LNq16Pseudo:
3538 case ARM::VLD4LNq32Pseudo:
3539 case ARM::VLD4LNd8Pseudo_UPD:
3540 case ARM::VLD4LNd16Pseudo_UPD:
3541 case ARM::VLD4LNd32Pseudo_UPD:
3542 case ARM::VLD4LNq16Pseudo_UPD:
3543 case ARM::VLD4LNq32Pseudo_UPD:
3544 // If the address is not 64-bit aligned, the latencies of these
3545 // instructions increases by one.
3553 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3554 const MachineInstr *MI,
3555 unsigned *PredCost) const {
3556 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3557 MI->isRegSequence() || MI->isImplicitDef())
3560 // An instruction scheduler typically runs on unbundled instructions, however
3561 // other passes may query the latency of a bundled instruction.
3562 if (MI->isBundle()) {
3563 unsigned Latency = 0;
3564 MachineBasicBlock::const_instr_iterator I = MI;
3565 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3566 while (++I != E && I->isInsideBundle()) {
3567 if (I->getOpcode() != ARM::t2IT)
3568 Latency += getInstrLatency(ItinData, I, PredCost);
3573 const MCInstrDesc &MCID = MI->getDesc();
3574 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3575 // When predicated, CPSR is an additional source operand for CPSR updating
3576 // instructions, this apparently increases their latencies.
3579 // Be sure to call getStageLatency for an empty itinerary in case it has a
3580 // valid MinLatency property.
3582 return MI->mayLoad() ? 3 : 1;
3584 unsigned Class = MCID.getSchedClass();
3586 // For instructions with variable uops, use uops as latency.
3587 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3588 return getNumMicroOps(ItinData, MI);
3590 // For the common case, fall back on the itinerary's latency.
3591 unsigned Latency = ItinData->getStageLatency(Class);
3593 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3594 unsigned DefAlign = MI->hasOneMemOperand()
3595 ? (*MI->memoperands_begin())->getAlignment() : 0;
3596 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3597 if (Adj >= 0 || (int)Latency > -Adj) {
3598 return Latency + Adj;
3603 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3604 SDNode *Node) const {
3605 if (!Node->isMachineOpcode())
3608 if (!ItinData || ItinData->isEmpty())
3611 unsigned Opcode = Node->getMachineOpcode();
3614 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3621 bool ARMBaseInstrInfo::
3622 hasHighOperandLatency(const InstrItineraryData *ItinData,
3623 const MachineRegisterInfo *MRI,
3624 const MachineInstr *DefMI, unsigned DefIdx,
3625 const MachineInstr *UseMI, unsigned UseIdx) const {
3626 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3627 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3628 if (Subtarget.isCortexA8() &&
3629 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3630 // CortexA8 VFP instructions are not pipelined.
3633 // Hoist VFP / NEON instructions with 4 or higher latency.
3634 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3637 Latency = getInstrLatency(ItinData, DefMI);
3640 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3641 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3644 bool ARMBaseInstrInfo::
3645 hasLowDefLatency(const InstrItineraryData *ItinData,
3646 const MachineInstr *DefMI, unsigned DefIdx) const {
3647 if (!ItinData || ItinData->isEmpty())
3650 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3651 if (DDomain == ARMII::DomainGeneral) {
3652 unsigned DefClass = DefMI->getDesc().getSchedClass();
3653 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3654 return (DefCycle != -1 && DefCycle <= 2);
3659 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3660 StringRef &ErrInfo) const {
3661 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3662 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3669 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3670 unsigned &AddSubOpc,
3671 bool &NegAcc, bool &HasLane) const {
3672 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3673 if (I == MLxEntryMap.end())
3676 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3677 MulOpc = Entry.MulOpc;
3678 AddSubOpc = Entry.AddSubOpc;
3679 NegAcc = Entry.NegAcc;
3680 HasLane = Entry.HasLane;
3684 //===----------------------------------------------------------------------===//
3685 // Execution domains.
3686 //===----------------------------------------------------------------------===//
3688 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3689 // and some can go down both. The vmov instructions go down the VFP pipeline,
3690 // but they can be changed to vorr equivalents that are executed by the NEON
3693 // We use the following execution domain numbering:
3701 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3703 std::pair<uint16_t, uint16_t>
3704 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3705 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3706 // if they are not predicated.
3707 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3708 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3710 // A9-like cores are particularly picky about mixing the two and want these
3712 if (Subtarget.isLikeA9() && !isPredicated(MI) &&
3713 (MI->getOpcode() == ARM::VMOVRS ||
3714 MI->getOpcode() == ARM::VMOVSR ||
3715 MI->getOpcode() == ARM::VMOVS))
3716 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3718 // No other instructions can be swizzled, so just determine their domain.
3719 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3721 if (Domain & ARMII::DomainNEON)
3722 return std::make_pair(ExeNEON, 0);
3724 // Certain instructions can go either way on Cortex-A8.
3725 // Treat them as NEON instructions.
3726 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3727 return std::make_pair(ExeNEON, 0);
3729 if (Domain & ARMII::DomainVFP)
3730 return std::make_pair(ExeVFP, 0);
3732 return std::make_pair(ExeGeneric, 0);
3735 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3736 unsigned SReg, unsigned &Lane) {
3737 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3740 if (DReg != ARM::NoRegister)
3744 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3746 assert(DReg && "S-register with no D super-register?");
3750 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
3751 /// set ImplicitSReg to a register number that must be marked as implicit-use or
3752 /// zero if no register needs to be defined as implicit-use.
3754 /// If the function cannot determine if an SPR should be marked implicit use or
3755 /// not, it returns false.
3757 /// This function handles cases where an instruction is being modified from taking
3758 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
3759 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
3760 /// lane of the DPR).
3762 /// If the other SPR is defined, an implicit-use of it should be added. Else,
3763 /// (including the case where the DPR itself is defined), it should not.
3765 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
3767 unsigned DReg, unsigned Lane,
3768 unsigned &ImplicitSReg) {
3769 // If the DPR is defined or used already, the other SPR lane will be chained
3770 // correctly, so there is nothing to be done.
3771 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
3776 // Otherwise we need to go searching to see if the SPR is set explicitly.
3777 ImplicitSReg = TRI->getSubReg(DReg,
3778 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
3779 MachineBasicBlock::LivenessQueryResult LQR =
3780 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
3782 if (LQR == MachineBasicBlock::LQR_Live)
3784 else if (LQR == MachineBasicBlock::LQR_Unknown)
3787 // If the register is known not to be live, there is no need to add an
3794 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3795 unsigned DstReg, SrcReg, DReg;
3797 MachineInstrBuilder MIB(MI);
3798 const TargetRegisterInfo *TRI = &getRegisterInfo();
3799 switch (MI->getOpcode()) {
3801 llvm_unreachable("cannot handle opcode!");
3804 if (Domain != ExeNEON)
3807 // Zap the predicate operands.
3808 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3810 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
3811 DstReg = MI->getOperand(0).getReg();
3812 SrcReg = MI->getOperand(1).getReg();
3814 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3815 MI->RemoveOperand(i-1);
3817 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
3818 MI->setDesc(get(ARM::VORRd));
3819 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3824 if (Domain != ExeNEON)
3826 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3828 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
3829 DstReg = MI->getOperand(0).getReg();
3830 SrcReg = MI->getOperand(1).getReg();
3832 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3833 MI->RemoveOperand(i-1);
3835 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
3837 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
3838 // Note that DSrc has been widened and the other lane may be undef, which
3839 // contaminates the entire register.
3840 MI->setDesc(get(ARM::VGETLNi32));
3841 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3842 .addReg(DReg, RegState::Undef)
3845 // The old source should be an implicit use, otherwise we might think it
3846 // was dead before here.
3847 MIB.addReg(SrcReg, RegState::Implicit);
3850 if (Domain != ExeNEON)
3852 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3854 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
3855 DstReg = MI->getOperand(0).getReg();
3856 SrcReg = MI->getOperand(1).getReg();
3858 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
3860 unsigned ImplicitSReg;
3861 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
3864 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3865 MI->RemoveOperand(i-1);
3867 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
3868 // Again DDst may be undefined at the beginning of this instruction.
3869 MI->setDesc(get(ARM::VSETLNi32));
3870 MIB.addReg(DReg, RegState::Define)
3871 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
3874 AddDefaultPred(MIB);
3876 // The narrower destination must be marked as set to keep previous chains
3878 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3879 if (ImplicitSReg != 0)
3880 MIB.addReg(ImplicitSReg, RegState::Implicit);
3884 if (Domain != ExeNEON)
3887 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
3888 DstReg = MI->getOperand(0).getReg();
3889 SrcReg = MI->getOperand(1).getReg();
3891 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
3892 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
3893 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
3895 unsigned ImplicitSReg;
3896 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
3899 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3900 MI->RemoveOperand(i-1);
3903 // Destination can be:
3904 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
3905 MI->setDesc(get(ARM::VDUPLN32d));
3906 MIB.addReg(DDst, RegState::Define)
3907 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
3909 AddDefaultPred(MIB);
3911 // Neither the source or the destination are naturally represented any
3912 // more, so add them in manually.
3913 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3914 MIB.addReg(SrcReg, RegState::Implicit);
3915 if (ImplicitSReg != 0)
3916 MIB.addReg(ImplicitSReg, RegState::Implicit);
3920 // In general there's no single instruction that can perform an S <-> S
3921 // move in NEON space, but a pair of VEXT instructions *can* do the
3922 // job. It turns out that the VEXTs needed will only use DSrc once, with
3923 // the position based purely on the combination of lane-0 and lane-1
3924 // involved. For example
3925 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
3926 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
3927 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
3928 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
3930 // Pattern of the MachineInstrs is:
3931 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
3932 MachineInstrBuilder NewMIB;
3933 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
3934 get(ARM::VEXTd32), DDst);
3936 // On the first instruction, both DSrc and DDst may be <undef> if present.
3937 // Specifically when the original instruction didn't have them as an
3939 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
3940 bool CurUndef = !MI->readsRegister(CurReg, TRI);
3941 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
3943 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
3944 CurUndef = !MI->readsRegister(CurReg, TRI);
3945 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
3948 AddDefaultPred(NewMIB);
3950 if (SrcLane == DstLane)
3951 NewMIB.addReg(SrcReg, RegState::Implicit);
3953 MI->setDesc(get(ARM::VEXTd32));
3954 MIB.addReg(DDst, RegState::Define);
3956 // On the second instruction, DDst has definitely been defined above, so
3957 // it is not <undef>. DSrc, if present, can be <undef> as above.
3958 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
3959 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
3960 MIB.addReg(CurReg, getUndefRegState(CurUndef));
3962 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
3963 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
3964 MIB.addReg(CurReg, getUndefRegState(CurUndef));
3967 AddDefaultPred(MIB);
3969 if (SrcLane != DstLane)
3970 MIB.addReg(SrcReg, RegState::Implicit);
3972 // As before, the original destination is no longer represented, add it
3974 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3975 if (ImplicitSReg != 0)
3976 MIB.addReg(ImplicitSReg, RegState::Implicit);
3983 //===----------------------------------------------------------------------===//
3984 // Partial register updates
3985 //===----------------------------------------------------------------------===//
3987 // Swift renames NEON registers with 64-bit granularity. That means any
3988 // instruction writing an S-reg implicitly reads the containing D-reg. The
3989 // problem is mostly avoided by translating f32 operations to v2f32 operations
3990 // on D-registers, but f32 loads are still a problem.
3992 // These instructions can load an f32 into a NEON register:
3994 // VLDRS - Only writes S, partial D update.
3995 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
3996 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
3998 // FCONSTD can be used as a dependency-breaking instruction.
4001 unsigned ARMBaseInstrInfo::
4002 getPartialRegUpdateClearance(const MachineInstr *MI,
4004 const TargetRegisterInfo *TRI) const {
4005 // Only Swift has partial register update problems.
4006 if (!SwiftPartialUpdateClearance || !Subtarget.isSwift())
4009 assert(TRI && "Need TRI instance");
4011 const MachineOperand &MO = MI->getOperand(OpNum);
4014 unsigned Reg = MO.getReg();
4017 switch(MI->getOpcode()) {
4018 // Normal instructions writing only an S-register.
4022 // rdar://problem/8791586
4024 case ARM::VMOVv4i16:
4025 case ARM::VMOVv2i32:
4026 case ARM::VMOVv2f32:
4027 case ARM::VMOVv1i64:
4028 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4031 // Explicitly reads the dependency.
4032 case ARM::VLD1LNd32:
4039 // If this instruction actually reads a value from Reg, there is no unwanted
4041 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4044 // We must be able to clobber the whole D-reg.
4045 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4046 // Virtual register must be a foo:ssub_0<def,undef> operand.
4047 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4049 } else if (ARM::SPRRegClass.contains(Reg)) {
4050 // Physical register: MI must define the full D-reg.
4051 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4053 if (!DReg || !MI->definesRegister(DReg, TRI))
4057 // MI has an unwanted D-register dependency.
4058 // Avoid defs in the previous N instructrions.
4059 return SwiftPartialUpdateClearance;
4062 // Break a partial register dependency after getPartialRegUpdateClearance
4063 // returned non-zero.
4064 void ARMBaseInstrInfo::
4065 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4067 const TargetRegisterInfo *TRI) const {
4068 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4069 assert(TRI && "Need TRI instance");
4071 const MachineOperand &MO = MI->getOperand(OpNum);
4072 unsigned Reg = MO.getReg();
4073 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4074 "Can't break virtual register dependencies.");
4075 unsigned DReg = Reg;
4077 // If MI defines an S-reg, find the corresponding D super-register.
4078 if (ARM::SPRRegClass.contains(Reg)) {
4079 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4080 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4083 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4084 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4086 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4087 // the full D-register by loading the same value to both lanes. The
4088 // instruction is micro-coded with 2 uops, so don't do this until we can
4089 // properly schedule micro-coded instuctions. The dispatcher stalls cause
4090 // too big regressions.
4092 // Insert the dependency-breaking FCONSTD before MI.
4093 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4094 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4095 get(ARM::FCONSTD), DReg).addImm(96));
4096 MI->addRegisterKilled(DReg, TRI, true);
4099 bool ARMBaseInstrInfo::hasNOP() const {
4100 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;