1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/Support/BranchProbability.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
43 #define DEBUG_TYPE "arm-instrinfo"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "ARMGenInstrInfo.inc"
49 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
50 cl::desc("Enable ARM 2-addr to 3-addr conv"));
53 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
54 cl::desc("Widen ARM vmovs to vmovd when possible"));
56 static cl::opt<unsigned>
57 SwiftPartialUpdateClearance("swift-partial-update-clearance",
58 cl::Hidden, cl::init(12),
59 cl::desc("Clearance before partial register updates"));
61 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
63 uint16_t MLxOpc; // MLA / MLS opcode
64 uint16_t MulOpc; // Expanded multiplication opcode
65 uint16_t AddSubOpc; // Expanded add / sub opcode
66 bool NegAcc; // True if the acc is negated before the add / sub.
67 bool HasLane; // True if instruction has an extra "lane" operand.
70 static const ARM_MLxEntry ARM_MLxTable[] = {
71 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
73 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
74 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
75 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
76 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
77 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
78 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
79 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
80 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
83 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
84 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
85 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
86 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
87 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
88 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
89 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
90 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
93 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
94 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
96 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
97 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
98 assert(false && "Duplicated entries?");
99 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
100 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
104 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
105 // currently defaults to no prepass hazard recognizer.
106 ScheduleHazardRecognizer *
107 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
108 const ScheduleDAG *DAG) const {
109 if (usePreRAHazardRecognizer()) {
110 const InstrItineraryData *II =
111 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
112 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
114 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
117 ScheduleHazardRecognizer *ARMBaseInstrInfo::
118 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
119 const ScheduleDAG *DAG) const {
120 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
121 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
122 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
126 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
127 MachineBasicBlock::iterator &MBBI,
128 LiveVariables *LV) const {
129 // FIXME: Thumb2 support.
134 MachineInstr *MI = MBBI;
135 MachineFunction &MF = *MI->getParent()->getParent();
136 uint64_t TSFlags = MI->getDesc().TSFlags;
138 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
139 default: return nullptr;
140 case ARMII::IndexModePre:
143 case ARMII::IndexModePost:
147 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
149 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
153 MachineInstr *UpdateMI = nullptr;
154 MachineInstr *MemMI = nullptr;
155 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
156 const MCInstrDesc &MCID = MI->getDesc();
157 unsigned NumOps = MCID.getNumOperands();
158 bool isLoad = !MI->mayStore();
159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
160 const MachineOperand &Base = MI->getOperand(2);
161 const MachineOperand &Offset = MI->getOperand(NumOps-3);
162 unsigned WBReg = WB.getReg();
163 unsigned BaseReg = Base.getReg();
164 unsigned OffReg = Offset.getReg();
165 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
168 default: llvm_unreachable("Unknown indexed op!");
169 case ARMII::AddrMode2: {
170 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
171 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
173 if (ARM_AM::getSOImmVal(Amt) == -1)
174 // Can't encode it in a so_imm operand. This transformation will
175 // add more than 1 instruction. Abandon!
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
179 .addReg(BaseReg).addImm(Amt)
180 .addImm(Pred).addReg(0).addReg(0);
181 } else if (Amt != 0) {
182 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
183 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
184 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
186 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
187 .addImm(Pred).addReg(0).addReg(0);
189 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
190 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
191 .addReg(BaseReg).addReg(OffReg)
192 .addImm(Pred).addReg(0).addReg(0);
195 case ARMII::AddrMode3 : {
196 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
197 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
199 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
200 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
202 .addReg(BaseReg).addImm(Amt)
203 .addImm(Pred).addReg(0).addReg(0);
205 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
206 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
207 .addReg(BaseReg).addReg(OffReg)
208 .addImm(Pred).addReg(0).addReg(0);
213 std::vector<MachineInstr*> NewMIs;
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc), MI->getOperand(0).getReg())
218 .addReg(WBReg).addImm(0).addImm(Pred);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc)).addReg(MI->getOperand(1).getReg())
222 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
223 NewMIs.push_back(MemMI);
224 NewMIs.push_back(UpdateMI);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc), MI->getOperand(0).getReg())
229 .addReg(BaseReg).addImm(0).addImm(Pred);
231 MemMI = BuildMI(MF, MI->getDebugLoc(),
232 get(MemOpc)).addReg(MI->getOperand(1).getReg())
233 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
235 UpdateMI->getOperand(0).setIsDead();
236 NewMIs.push_back(UpdateMI);
237 NewMIs.push_back(MemMI);
240 // Transfer LiveVariables states, kill / dead info.
242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243 MachineOperand &MO = MI->getOperand(i);
244 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
245 unsigned Reg = MO.getReg();
247 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
249 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
251 LV->addVirtualRegisterDead(Reg, NewMI);
253 if (MO.isUse() && MO.isKill()) {
254 for (unsigned j = 0; j < 2; ++j) {
255 // Look at the two new MI's in reverse order.
256 MachineInstr *NewMI = NewMIs[j];
257 if (!NewMI->readsRegister(Reg))
259 LV->addVirtualRegisterKilled(Reg, NewMI);
260 if (VI.removeKill(MI))
261 VI.Kills.push_back(NewMI);
269 MFI->insert(MBBI, NewMIs[1]);
270 MFI->insert(MBBI, NewMIs[0]);
276 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
277 MachineBasicBlock *&FBB,
278 SmallVectorImpl<MachineOperand> &Cond,
279 bool AllowModify) const {
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin())
285 return false; // Empty blocks are easy.
288 // Walk backwards from the end of the basic block until the branch is
289 // analyzed or we give up.
290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
292 // Flag to be raised on unanalyzeable instructions. This is useful in cases
293 // where we want to clean up on the end of the basic block before we bail
295 bool CantAnalyze = false;
297 // Skip over DEBUG values and predicated nonterminators.
298 while (I->isDebugValue() || !I->isTerminator()) {
299 if (I == MBB.begin())
304 if (isIndirectBranchOpcode(I->getOpcode()) ||
305 isJumpTableBranchOpcode(I->getOpcode())) {
306 // Indirect branches and jump tables can't be analyzed, but we still want
307 // to clean up any instructions at the tail of the basic block.
309 } else if (isUncondBranchOpcode(I->getOpcode())) {
310 TBB = I->getOperand(0).getMBB();
311 } else if (isCondBranchOpcode(I->getOpcode())) {
312 // Bail out if we encounter multiple conditional branches.
316 assert(!FBB && "FBB should have been null.");
318 TBB = I->getOperand(0).getMBB();
319 Cond.push_back(I->getOperand(1));
320 Cond.push_back(I->getOperand(2));
321 } else if (I->isReturn()) {
322 // Returns can't be analyzed, but we should run cleanup.
323 CantAnalyze = !isPredicated(I);
325 // We encountered other unrecognized terminator. Bail out immediately.
329 // Cleanup code - to be run for unpredicated unconditional branches and
331 if (!isPredicated(I) &&
332 (isUncondBranchOpcode(I->getOpcode()) ||
333 isIndirectBranchOpcode(I->getOpcode()) ||
334 isJumpTableBranchOpcode(I->getOpcode()) ||
336 // Forget any previous condition branch information - it no longer applies.
340 // If we can modify the function, delete everything below this
341 // unconditional branch.
343 MachineBasicBlock::iterator DI = std::next(I);
344 while (DI != MBB.end()) {
345 MachineInstr *InstToDelete = DI;
347 InstToDelete->eraseFromParent();
355 if (I == MBB.begin())
361 // We made it past the terminators without bailing out - we must have
362 // analyzed this branch successfully.
367 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
368 MachineBasicBlock::iterator I = MBB.end();
369 if (I == MBB.begin()) return 0;
371 while (I->isDebugValue()) {
372 if (I == MBB.begin())
376 if (!isUncondBranchOpcode(I->getOpcode()) &&
377 !isCondBranchOpcode(I->getOpcode()))
380 // Remove the branch.
381 I->eraseFromParent();
385 if (I == MBB.begin()) return 1;
387 if (!isCondBranchOpcode(I->getOpcode()))
390 // Remove the branch.
391 I->eraseFromParent();
396 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
397 MachineBasicBlock *FBB,
398 const SmallVectorImpl<MachineOperand> &Cond,
400 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
401 int BOpc = !AFI->isThumbFunction()
402 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
403 int BccOpc = !AFI->isThumbFunction()
404 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
405 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
407 // Shouldn't be a fall through.
408 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
409 assert((Cond.size() == 2 || Cond.size() == 0) &&
410 "ARM branch conditions have two components!");
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI,
459 const SmallVectorImpl<MachineOperand> &Pred) const {
460 unsigned Opc = MI->getOpcode();
461 if (isUncondBranchOpcode(Opc)) {
462 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
463 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
464 .addImm(Pred[0].getImm())
465 .addReg(Pred[1].getReg());
469 int PIdx = MI->findFirstPredOperandIdx();
471 MachineOperand &PMO = MI->getOperand(PIdx);
472 PMO.setImm(Pred[0].getImm());
473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
479 bool ARMBaseInstrInfo::
480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
481 const SmallVectorImpl<MachineOperand> &Pred2) const {
482 if (Pred1.size() > 2 || Pred2.size() > 2)
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
496 return CC2 == ARMCC::HI;
498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
500 return CC2 == ARMCC::GT;
502 return CC2 == ARMCC::LT;
506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
507 std::vector<MachineOperand> &Pred) const {
509 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
510 const MachineOperand &MO = MI->getOperand(i);
511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
512 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
521 static bool isCPSRDefined(const MachineInstr *MI) {
522 for (const auto &MO : MI->operands())
523 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
528 static bool isEligibleForITBlock(const MachineInstr *MI) {
529 switch (MI->getOpcode()) {
530 default: return true;
531 case ARM::tADC: // ADC (register) T1
532 case ARM::tADDi3: // ADD (immediate) T1
533 case ARM::tADDi8: // ADD (immediate) T2
534 case ARM::tADDrr: // ADD (register) T1
535 case ARM::tAND: // AND (register) T1
536 case ARM::tASRri: // ASR (immediate) T1
537 case ARM::tASRrr: // ASR (register) T1
538 case ARM::tBIC: // BIC (register) T1
539 case ARM::tEOR: // EOR (register) T1
540 case ARM::tLSLri: // LSL (immediate) T1
541 case ARM::tLSLrr: // LSL (register) T1
542 case ARM::tLSRri: // LSR (immediate) T1
543 case ARM::tLSRrr: // LSR (register) T1
544 case ARM::tMUL: // MUL T1
545 case ARM::tMVN: // MVN (register) T1
546 case ARM::tORR: // ORR (register) T1
547 case ARM::tROR: // ROR (register) T1
548 case ARM::tRSB: // RSB (immediate) T1
549 case ARM::tSBC: // SBC (register) T1
550 case ARM::tSUBi3: // SUB (immediate) T1
551 case ARM::tSUBi8: // SUB (immediate) T2
552 case ARM::tSUBrr: // SUB (register) T1
553 return !isCPSRDefined(MI);
557 /// isPredicable - Return true if the specified instruction can be predicated.
558 /// By default, this returns true for every instruction with a
559 /// PredicateOperand.
560 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
561 if (!MI->isPredicable())
564 if (!isEligibleForITBlock(MI))
567 ARMFunctionInfo *AFI =
568 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
570 if (AFI->isThumb2Function()) {
571 if (getSubtarget().restrictIT())
572 return isV8EligibleForIT(MI);
573 } else { // non-Thumb
574 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
582 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584 const MachineOperand &MO = MI->getOperand(i);
585 if (!MO.isReg() || MO.isUndef() || MO.isUse())
587 if (MO.getReg() != ARM::CPSR)
592 // all definitions of CPSR are dead
597 /// GetInstSize - Return the size of the specified MachineInstr.
599 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
600 const MachineBasicBlock &MBB = *MI->getParent();
601 const MachineFunction *MF = MBB.getParent();
602 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
604 const MCInstrDesc &MCID = MI->getDesc();
606 return MCID.getSize();
608 // If this machine instr is an inline asm, measure it.
609 if (MI->getOpcode() == ARM::INLINEASM)
610 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
611 unsigned Opc = MI->getOpcode();
614 // pseudo-instruction sizes are zero.
616 case TargetOpcode::BUNDLE:
617 return getInstBundleLength(MI);
618 case ARM::MOVi16_ga_pcrel:
619 case ARM::MOVTi16_ga_pcrel:
620 case ARM::t2MOVi16_ga_pcrel:
621 case ARM::t2MOVTi16_ga_pcrel:
624 case ARM::t2MOVi32imm:
626 case ARM::CONSTPOOL_ENTRY:
627 // If this machine instr is a constant pool entry, its size is recorded as
629 return MI->getOperand(2).getImm();
630 case ARM::Int_eh_sjlj_longjmp:
632 case ARM::tInt_eh_sjlj_longjmp:
634 case ARM::Int_eh_sjlj_setjmp:
635 case ARM::Int_eh_sjlj_setjmp_nofp:
637 case ARM::tInt_eh_sjlj_setjmp:
638 case ARM::t2Int_eh_sjlj_setjmp:
639 case ARM::t2Int_eh_sjlj_setjmp_nofp:
647 case ARM::t2TBH_JT: {
648 // These are jumptable branches, i.e. a branch followed by an inlined
649 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
650 // entry is one byte; TBH two byte each.
651 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
652 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
653 unsigned NumOps = MCID.getNumOperands();
654 MachineOperand JTOP =
655 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
656 unsigned JTI = JTOP.getIndex();
657 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
658 assert(MJTI != nullptr);
659 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
660 assert(JTI < JT.size());
661 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
662 // 4 aligned. The assembler / linker may add 2 byte padding just before
663 // the JT entries. The size does not include this padding; the
664 // constant islands pass does separate bookkeeping for it.
665 // FIXME: If we know the size of the function is less than (1 << 16) *2
666 // bytes, we can use 16-bit entries instead. Then there won't be an
668 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
669 unsigned NumEntries = JT[JTI].MBBs.size();
670 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
671 // Make sure the instruction that follows TBB is 2-byte aligned.
672 // FIXME: Constant island pass should insert an "ALIGN" instruction
675 return NumEntries * EntrySize + InstSize;
678 return MI->getOperand(1).getImm();
682 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
684 MachineBasicBlock::const_instr_iterator I = MI;
685 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
686 while (++I != E && I->isInsideBundle()) {
687 assert(!I->isBundle() && "No nested bundle!");
688 Size += GetInstSizeInBytes(&*I);
693 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
694 MachineBasicBlock::iterator I,
695 unsigned DestReg, bool KillSrc,
696 const ARMSubtarget &Subtarget) const {
697 unsigned Opc = Subtarget.isThumb()
698 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
701 MachineInstrBuilder MIB =
702 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
704 // There is only 1 A/R class MRS instruction, and it always refers to
705 // APSR. However, there are lots of other possibilities on M-class cores.
706 if (Subtarget.isMClass())
711 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
714 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
715 MachineBasicBlock::iterator I,
716 unsigned SrcReg, bool KillSrc,
717 const ARMSubtarget &Subtarget) const {
718 unsigned Opc = Subtarget.isThumb()
719 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
722 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
724 if (Subtarget.isMClass())
729 MIB.addReg(SrcReg, getKillRegState(KillSrc));
733 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
736 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
737 MachineBasicBlock::iterator I, DebugLoc DL,
738 unsigned DestReg, unsigned SrcReg,
739 bool KillSrc) const {
740 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
741 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
743 if (GPRDest && GPRSrc) {
744 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
745 .addReg(SrcReg, getKillRegState(KillSrc))));
749 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
750 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
753 if (SPRDest && SPRSrc)
755 else if (GPRDest && SPRSrc)
757 else if (SPRDest && GPRSrc)
759 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
761 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
765 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
766 MIB.addReg(SrcReg, getKillRegState(KillSrc));
767 if (Opc == ARM::VORRq)
768 MIB.addReg(SrcReg, getKillRegState(KillSrc));
773 // Handle register classes that require multiple instructions.
774 unsigned BeginIdx = 0;
775 unsigned SubRegs = 0;
778 // Use VORRq when possible.
779 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
781 BeginIdx = ARM::qsub_0;
783 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
785 BeginIdx = ARM::qsub_0;
787 // Fall back to VMOVD.
788 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
790 BeginIdx = ARM::dsub_0;
792 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
794 BeginIdx = ARM::dsub_0;
796 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
798 BeginIdx = ARM::dsub_0;
800 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
801 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
802 BeginIdx = ARM::gsub_0;
804 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
806 BeginIdx = ARM::dsub_0;
809 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
811 BeginIdx = ARM::dsub_0;
814 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
816 BeginIdx = ARM::dsub_0;
819 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
821 BeginIdx = ARM::ssub_0;
823 } else if (SrcReg == ARM::CPSR) {
824 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
826 } else if (DestReg == ARM::CPSR) {
827 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
831 assert(Opc && "Impossible reg-to-reg copy");
833 const TargetRegisterInfo *TRI = &getRegisterInfo();
834 MachineInstrBuilder Mov;
836 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
837 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
838 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
842 SmallSet<unsigned, 4> DstRegs;
844 for (unsigned i = 0; i != SubRegs; ++i) {
845 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
846 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
847 assert(Dst && Src && "Bad sub-register");
849 assert(!DstRegs.count(Src) && "destructive vector copy");
852 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
853 // VORR takes two source operands.
854 if (Opc == ARM::VORRq)
856 Mov = AddDefaultPred(Mov);
858 if (Opc == ARM::MOVr)
859 Mov = AddDefaultCC(Mov);
861 // Add implicit super-register defs and kills to the last instruction.
862 Mov->addRegisterDefined(DestReg, TRI);
864 Mov->addRegisterKilled(SrcReg, TRI);
867 const MachineInstrBuilder &
868 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
869 unsigned SubIdx, unsigned State,
870 const TargetRegisterInfo *TRI) const {
872 return MIB.addReg(Reg, State);
874 if (TargetRegisterInfo::isPhysicalRegister(Reg))
875 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
876 return MIB.addReg(Reg, State, SubIdx);
879 void ARMBaseInstrInfo::
880 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
881 unsigned SrcReg, bool isKill, int FI,
882 const TargetRegisterClass *RC,
883 const TargetRegisterInfo *TRI) const {
885 if (I != MBB.end()) DL = I->getDebugLoc();
886 MachineFunction &MF = *MBB.getParent();
887 MachineFrameInfo &MFI = *MF.getFrameInfo();
888 unsigned Align = MFI.getObjectAlignment(FI);
890 MachineMemOperand *MMO =
891 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
892 MachineMemOperand::MOStore,
893 MFI.getObjectSize(FI),
896 switch (RC->getSize()) {
898 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
899 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
900 .addReg(SrcReg, getKillRegState(isKill))
901 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
902 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
903 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
904 .addReg(SrcReg, getKillRegState(isKill))
905 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
907 llvm_unreachable("Unknown reg class!");
910 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
912 .addReg(SrcReg, getKillRegState(isKill))
913 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
914 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
915 if (Subtarget.hasV5TEOps()) {
916 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
917 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
918 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
919 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
923 // Fallback to STM instruction, which has existed since the dawn of
925 MachineInstrBuilder MIB =
926 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
927 .addFrameIndex(FI).addMemOperand(MMO));
928 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
929 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
932 llvm_unreachable("Unknown reg class!");
935 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
936 // Use aligned spills if the stack can be realigned.
937 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
938 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
939 .addFrameIndex(FI).addImm(16)
940 .addReg(SrcReg, getKillRegState(isKill))
941 .addMemOperand(MMO));
943 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
944 .addReg(SrcReg, getKillRegState(isKill))
946 .addMemOperand(MMO));
949 llvm_unreachable("Unknown reg class!");
952 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
953 // Use aligned spills if the stack can be realigned.
954 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
955 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
956 .addFrameIndex(FI).addImm(16)
957 .addReg(SrcReg, getKillRegState(isKill))
958 .addMemOperand(MMO));
960 MachineInstrBuilder MIB =
961 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
964 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
966 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
969 llvm_unreachable("Unknown reg class!");
972 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
973 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
974 // FIXME: It's possible to only store part of the QQ register if the
975 // spilled def has a sub-register index.
976 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
977 .addFrameIndex(FI).addImm(16)
978 .addReg(SrcReg, getKillRegState(isKill))
979 .addMemOperand(MMO));
981 MachineInstrBuilder MIB =
982 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
985 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
986 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
987 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
988 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
991 llvm_unreachable("Unknown reg class!");
994 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
995 MachineInstrBuilder MIB =
996 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
999 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1000 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1001 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1002 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1003 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1004 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1005 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1006 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1008 llvm_unreachable("Unknown reg class!");
1011 llvm_unreachable("Unknown reg class!");
1016 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1017 int &FrameIndex) const {
1018 switch (MI->getOpcode()) {
1021 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1022 if (MI->getOperand(1).isFI() &&
1023 MI->getOperand(2).isReg() &&
1024 MI->getOperand(3).isImm() &&
1025 MI->getOperand(2).getReg() == 0 &&
1026 MI->getOperand(3).getImm() == 0) {
1027 FrameIndex = MI->getOperand(1).getIndex();
1028 return MI->getOperand(0).getReg();
1036 if (MI->getOperand(1).isFI() &&
1037 MI->getOperand(2).isImm() &&
1038 MI->getOperand(2).getImm() == 0) {
1039 FrameIndex = MI->getOperand(1).getIndex();
1040 return MI->getOperand(0).getReg();
1044 case ARM::VST1d64TPseudo:
1045 case ARM::VST1d64QPseudo:
1046 if (MI->getOperand(0).isFI() &&
1047 MI->getOperand(2).getSubReg() == 0) {
1048 FrameIndex = MI->getOperand(0).getIndex();
1049 return MI->getOperand(2).getReg();
1053 if (MI->getOperand(1).isFI() &&
1054 MI->getOperand(0).getSubReg() == 0) {
1055 FrameIndex = MI->getOperand(1).getIndex();
1056 return MI->getOperand(0).getReg();
1064 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1065 int &FrameIndex) const {
1066 const MachineMemOperand *Dummy;
1067 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1070 void ARMBaseInstrInfo::
1071 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1072 unsigned DestReg, int FI,
1073 const TargetRegisterClass *RC,
1074 const TargetRegisterInfo *TRI) const {
1076 if (I != MBB.end()) DL = I->getDebugLoc();
1077 MachineFunction &MF = *MBB.getParent();
1078 MachineFrameInfo &MFI = *MF.getFrameInfo();
1079 unsigned Align = MFI.getObjectAlignment(FI);
1080 MachineMemOperand *MMO =
1081 MF.getMachineMemOperand(
1082 MachinePointerInfo::getFixedStack(FI),
1083 MachineMemOperand::MOLoad,
1084 MFI.getObjectSize(FI),
1087 switch (RC->getSize()) {
1089 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1090 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1091 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1093 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1094 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1095 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1097 llvm_unreachable("Unknown reg class!");
1100 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1103 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1104 MachineInstrBuilder MIB;
1106 if (Subtarget.hasV5TEOps()) {
1107 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1108 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1109 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1110 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1112 AddDefaultPred(MIB);
1114 // Fallback to LDM instruction, which has existed since the dawn of
1116 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1117 .addFrameIndex(FI).addMemOperand(MMO));
1118 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1119 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1122 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1123 MIB.addReg(DestReg, RegState::ImplicitDefine);
1125 llvm_unreachable("Unknown reg class!");
1128 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1129 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1131 .addFrameIndex(FI).addImm(16)
1132 .addMemOperand(MMO));
1134 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1136 .addMemOperand(MMO));
1139 llvm_unreachable("Unknown reg class!");
1142 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1143 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1144 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1145 .addFrameIndex(FI).addImm(16)
1146 .addMemOperand(MMO));
1148 MachineInstrBuilder MIB =
1149 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1151 .addMemOperand(MMO));
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1155 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1156 MIB.addReg(DestReg, RegState::ImplicitDefine);
1159 llvm_unreachable("Unknown reg class!");
1162 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1163 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1164 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1165 .addFrameIndex(FI).addImm(16)
1166 .addMemOperand(MMO));
1168 MachineInstrBuilder MIB =
1169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1171 .addMemOperand(MMO);
1172 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1173 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1174 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1175 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1176 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1177 MIB.addReg(DestReg, RegState::ImplicitDefine);
1180 llvm_unreachable("Unknown reg class!");
1183 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1184 MachineInstrBuilder MIB =
1185 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1187 .addMemOperand(MMO);
1188 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1189 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1190 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1191 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1192 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1193 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1194 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1195 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1196 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1197 MIB.addReg(DestReg, RegState::ImplicitDefine);
1199 llvm_unreachable("Unknown reg class!");
1202 llvm_unreachable("Unknown regclass!");
1207 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1208 int &FrameIndex) const {
1209 switch (MI->getOpcode()) {
1212 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1213 if (MI->getOperand(1).isFI() &&
1214 MI->getOperand(2).isReg() &&
1215 MI->getOperand(3).isImm() &&
1216 MI->getOperand(2).getReg() == 0 &&
1217 MI->getOperand(3).getImm() == 0) {
1218 FrameIndex = MI->getOperand(1).getIndex();
1219 return MI->getOperand(0).getReg();
1227 if (MI->getOperand(1).isFI() &&
1228 MI->getOperand(2).isImm() &&
1229 MI->getOperand(2).getImm() == 0) {
1230 FrameIndex = MI->getOperand(1).getIndex();
1231 return MI->getOperand(0).getReg();
1235 case ARM::VLD1d64TPseudo:
1236 case ARM::VLD1d64QPseudo:
1237 if (MI->getOperand(1).isFI() &&
1238 MI->getOperand(0).getSubReg() == 0) {
1239 FrameIndex = MI->getOperand(1).getIndex();
1240 return MI->getOperand(0).getReg();
1244 if (MI->getOperand(1).isFI() &&
1245 MI->getOperand(0).getSubReg() == 0) {
1246 FrameIndex = MI->getOperand(1).getIndex();
1247 return MI->getOperand(0).getReg();
1255 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1256 int &FrameIndex) const {
1257 const MachineMemOperand *Dummy;
1258 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1262 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1263 MachineFunction &MF = *MI->getParent()->getParent();
1264 Reloc::Model RM = MF.getTarget().getRelocationModel();
1266 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1267 assert(getSubtarget().getTargetTriple().getObjectFormat() ==
1269 "LOAD_STACK_GUARD currently supported only for MachO.");
1270 expandLoadStackGuard(MI, RM);
1271 MI->getParent()->erase(MI);
1275 // This hook gets to expand COPY instructions before they become
1276 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1277 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1278 // changed into a VORR that can go down the NEON pipeline.
1279 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1280 Subtarget.isFPOnlySP())
1283 // Look for a copy between even S-registers. That is where we keep floats
1284 // when using NEON v2f32 instructions for f32 arithmetic.
1285 unsigned DstRegS = MI->getOperand(0).getReg();
1286 unsigned SrcRegS = MI->getOperand(1).getReg();
1287 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1290 const TargetRegisterInfo *TRI = &getRegisterInfo();
1291 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1293 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1295 if (!DstRegD || !SrcRegD)
1298 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1299 // legal if the COPY already defines the full DstRegD, and it isn't a
1300 // sub-register insertion.
1301 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1304 // A dead copy shouldn't show up here, but reject it just in case.
1305 if (MI->getOperand(0).isDead())
1308 // All clear, widen the COPY.
1309 DEBUG(dbgs() << "widening: " << *MI);
1310 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1312 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1313 // or some other super-register.
1314 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1315 if (ImpDefIdx != -1)
1316 MI->RemoveOperand(ImpDefIdx);
1318 // Change the opcode and operands.
1319 MI->setDesc(get(ARM::VMOVD));
1320 MI->getOperand(0).setReg(DstRegD);
1321 MI->getOperand(1).setReg(SrcRegD);
1322 AddDefaultPred(MIB);
1324 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1325 // register scavenger and machine verifier, so we need to indicate that we
1326 // are reading an undefined value from SrcRegD, but a proper value from
1328 MI->getOperand(1).setIsUndef();
1329 MIB.addReg(SrcRegS, RegState::Implicit);
1331 // SrcRegD may actually contain an unrelated value in the ssub_1
1332 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1333 if (MI->getOperand(1).isKill()) {
1334 MI->getOperand(1).setIsKill(false);
1335 MI->addRegisterKilled(SrcRegS, TRI, true);
1338 DEBUG(dbgs() << "replaced by: " << *MI);
1342 /// Create a copy of a const pool value. Update CPI to the new index and return
1344 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1345 MachineConstantPool *MCP = MF.getConstantPool();
1346 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1348 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1349 assert(MCPE.isMachineConstantPoolEntry() &&
1350 "Expecting a machine constantpool entry!");
1351 ARMConstantPoolValue *ACPV =
1352 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1354 unsigned PCLabelId = AFI->createPICLabelUId();
1355 ARMConstantPoolValue *NewCPV = nullptr;
1357 // FIXME: The below assumes PIC relocation model and that the function
1358 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1359 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1360 // instructions, so that's probably OK, but is PIC always correct when
1362 if (ACPV->isGlobalValue())
1363 NewCPV = ARMConstantPoolConstant::
1364 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1366 else if (ACPV->isExtSymbol())
1367 NewCPV = ARMConstantPoolSymbol::
1368 Create(MF.getFunction()->getContext(),
1369 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1370 else if (ACPV->isBlockAddress())
1371 NewCPV = ARMConstantPoolConstant::
1372 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1373 ARMCP::CPBlockAddress, 4);
1374 else if (ACPV->isLSDA())
1375 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1377 else if (ACPV->isMachineBasicBlock())
1378 NewCPV = ARMConstantPoolMBB::
1379 Create(MF.getFunction()->getContext(),
1380 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1382 llvm_unreachable("Unexpected ARM constantpool value type!!");
1383 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1387 void ARMBaseInstrInfo::
1388 reMaterialize(MachineBasicBlock &MBB,
1389 MachineBasicBlock::iterator I,
1390 unsigned DestReg, unsigned SubIdx,
1391 const MachineInstr *Orig,
1392 const TargetRegisterInfo &TRI) const {
1393 unsigned Opcode = Orig->getOpcode();
1396 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1397 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1401 case ARM::tLDRpci_pic:
1402 case ARM::t2LDRpci_pic: {
1403 MachineFunction &MF = *MBB.getParent();
1404 unsigned CPI = Orig->getOperand(1).getIndex();
1405 unsigned PCLabelId = duplicateCPV(MF, CPI);
1406 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1408 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1409 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1416 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1417 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1418 switch(Orig->getOpcode()) {
1419 case ARM::tLDRpci_pic:
1420 case ARM::t2LDRpci_pic: {
1421 unsigned CPI = Orig->getOperand(1).getIndex();
1422 unsigned PCLabelId = duplicateCPV(MF, CPI);
1423 Orig->getOperand(1).setIndex(CPI);
1424 Orig->getOperand(2).setImm(PCLabelId);
1431 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1432 const MachineInstr *MI1,
1433 const MachineRegisterInfo *MRI) const {
1434 int Opcode = MI0->getOpcode();
1435 if (Opcode == ARM::t2LDRpci ||
1436 Opcode == ARM::t2LDRpci_pic ||
1437 Opcode == ARM::tLDRpci ||
1438 Opcode == ARM::tLDRpci_pic ||
1439 Opcode == ARM::LDRLIT_ga_pcrel ||
1440 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1441 Opcode == ARM::tLDRLIT_ga_pcrel ||
1442 Opcode == ARM::MOV_ga_pcrel ||
1443 Opcode == ARM::MOV_ga_pcrel_ldr ||
1444 Opcode == ARM::t2MOV_ga_pcrel) {
1445 if (MI1->getOpcode() != Opcode)
1447 if (MI0->getNumOperands() != MI1->getNumOperands())
1450 const MachineOperand &MO0 = MI0->getOperand(1);
1451 const MachineOperand &MO1 = MI1->getOperand(1);
1452 if (MO0.getOffset() != MO1.getOffset())
1455 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1456 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1457 Opcode == ARM::tLDRLIT_ga_pcrel ||
1458 Opcode == ARM::MOV_ga_pcrel ||
1459 Opcode == ARM::MOV_ga_pcrel_ldr ||
1460 Opcode == ARM::t2MOV_ga_pcrel)
1461 // Ignore the PC labels.
1462 return MO0.getGlobal() == MO1.getGlobal();
1464 const MachineFunction *MF = MI0->getParent()->getParent();
1465 const MachineConstantPool *MCP = MF->getConstantPool();
1466 int CPI0 = MO0.getIndex();
1467 int CPI1 = MO1.getIndex();
1468 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1469 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1470 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1471 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1472 if (isARMCP0 && isARMCP1) {
1473 ARMConstantPoolValue *ACPV0 =
1474 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1475 ARMConstantPoolValue *ACPV1 =
1476 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1477 return ACPV0->hasSameValue(ACPV1);
1478 } else if (!isARMCP0 && !isARMCP1) {
1479 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1482 } else if (Opcode == ARM::PICLDR) {
1483 if (MI1->getOpcode() != Opcode)
1485 if (MI0->getNumOperands() != MI1->getNumOperands())
1488 unsigned Addr0 = MI0->getOperand(1).getReg();
1489 unsigned Addr1 = MI1->getOperand(1).getReg();
1490 if (Addr0 != Addr1) {
1492 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1493 !TargetRegisterInfo::isVirtualRegister(Addr1))
1496 // This assumes SSA form.
1497 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1498 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1499 // Check if the loaded value, e.g. a constantpool of a global address, are
1501 if (!produceSameValue(Def0, Def1, MRI))
1505 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1506 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1507 const MachineOperand &MO0 = MI0->getOperand(i);
1508 const MachineOperand &MO1 = MI1->getOperand(i);
1509 if (!MO0.isIdenticalTo(MO1))
1515 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1518 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1519 /// determine if two loads are loading from the same base address. It should
1520 /// only return true if the base pointers are the same and the only differences
1521 /// between the two addresses is the offset. It also returns the offsets by
1524 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1525 /// is permanently disabled.
1526 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1528 int64_t &Offset2) const {
1529 // Don't worry about Thumb: just ARM and Thumb2.
1530 if (Subtarget.isThumb1Only()) return false;
1532 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1535 switch (Load1->getMachineOpcode()) {
1549 case ARM::t2LDRSHi8:
1551 case ARM::t2LDRBi12:
1552 case ARM::t2LDRSHi12:
1556 switch (Load2->getMachineOpcode()) {
1569 case ARM::t2LDRSHi8:
1571 case ARM::t2LDRBi12:
1572 case ARM::t2LDRSHi12:
1576 // Check if base addresses and chain operands match.
1577 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1578 Load1->getOperand(4) != Load2->getOperand(4))
1581 // Index should be Reg0.
1582 if (Load1->getOperand(3) != Load2->getOperand(3))
1585 // Determine the offsets.
1586 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1587 isa<ConstantSDNode>(Load2->getOperand(1))) {
1588 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1589 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1596 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1597 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1598 /// be scheduled togther. On some targets if two loads are loading from
1599 /// addresses in the same cache line, it's better if they are scheduled
1600 /// together. This function takes two integers that represent the load offsets
1601 /// from the common base address. It returns true if it decides it's desirable
1602 /// to schedule the two loads together. "NumLoads" is the number of loads that
1603 /// have already been scheduled after Load1.
1605 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1606 /// is permanently disabled.
1607 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1608 int64_t Offset1, int64_t Offset2,
1609 unsigned NumLoads) const {
1610 // Don't worry about Thumb: just ARM and Thumb2.
1611 if (Subtarget.isThumb1Only()) return false;
1613 assert(Offset2 > Offset1);
1615 if ((Offset2 - Offset1) / 8 > 64)
1618 // Check if the machine opcodes are different. If they are different
1619 // then we consider them to not be of the same base address,
1620 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1621 // In this case, they are considered to be the same because they are different
1622 // encoding forms of the same basic instruction.
1623 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1624 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1625 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1626 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1627 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1628 return false; // FIXME: overly conservative?
1630 // Four loads in a row should be sufficient.
1637 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1638 const MachineBasicBlock *MBB,
1639 const MachineFunction &MF) const {
1640 // Debug info is never a scheduling boundary. It's necessary to be explicit
1641 // due to the special treatment of IT instructions below, otherwise a
1642 // dbg_value followed by an IT will result in the IT instruction being
1643 // considered a scheduling hazard, which is wrong. It should be the actual
1644 // instruction preceding the dbg_value instruction(s), just like it is
1645 // when debug info is not present.
1646 if (MI->isDebugValue())
1649 // Terminators and labels can't be scheduled around.
1650 if (MI->isTerminator() || MI->isPosition())
1653 // Treat the start of the IT block as a scheduling boundary, but schedule
1654 // t2IT along with all instructions following it.
1655 // FIXME: This is a big hammer. But the alternative is to add all potential
1656 // true and anti dependencies to IT block instructions as implicit operands
1657 // to the t2IT instruction. The added compile time and complexity does not
1659 MachineBasicBlock::const_iterator I = MI;
1660 // Make sure to skip any dbg_value instructions
1661 while (++I != MBB->end() && I->isDebugValue())
1663 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1666 // Don't attempt to schedule around any instruction that defines
1667 // a stack-oriented pointer, as it's unlikely to be profitable. This
1668 // saves compile time, because it doesn't require every single
1669 // stack slot reference to depend on the instruction that does the
1671 // Calls don't actually change the stack pointer, even if they have imp-defs.
1672 // No ARM calling conventions change the stack pointer. (X86 calling
1673 // conventions sometimes do).
1674 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1680 bool ARMBaseInstrInfo::
1681 isProfitableToIfCvt(MachineBasicBlock &MBB,
1682 unsigned NumCycles, unsigned ExtraPredCycles,
1683 const BranchProbability &Probability) const {
1687 // Attempt to estimate the relative costs of predication versus branching.
1688 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1689 UnpredCost /= Probability.getDenominator();
1690 UnpredCost += 1; // The branch itself
1691 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1693 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1696 bool ARMBaseInstrInfo::
1697 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1698 unsigned TCycles, unsigned TExtra,
1699 MachineBasicBlock &FMBB,
1700 unsigned FCycles, unsigned FExtra,
1701 const BranchProbability &Probability) const {
1702 if (!TCycles || !FCycles)
1705 // Attempt to estimate the relative costs of predication versus branching.
1706 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1707 TUnpredCost /= Probability.getDenominator();
1709 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1710 unsigned FUnpredCost = Comp * FCycles;
1711 FUnpredCost /= Probability.getDenominator();
1713 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1714 UnpredCost += 1; // The branch itself
1715 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1717 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1721 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1722 MachineBasicBlock &FMBB) const {
1723 // Reduce false anti-dependencies to let Swift's out-of-order execution
1724 // engine do its thing.
1725 return Subtarget.isSwift();
1728 /// getInstrPredicate - If instruction is predicated, returns its predicate
1729 /// condition, otherwise returns AL. It also returns the condition code
1730 /// register by reference.
1732 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1733 int PIdx = MI->findFirstPredOperandIdx();
1739 PredReg = MI->getOperand(PIdx+1).getReg();
1740 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1744 int llvm::getMatchingCondBranchOpcode(int Opc) {
1749 if (Opc == ARM::t2B)
1752 llvm_unreachable("Unknown unconditional branch opcode!");
1755 /// commuteInstruction - Handle commutable instructions.
1757 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1758 switch (MI->getOpcode()) {
1760 case ARM::t2MOVCCr: {
1761 // MOVCC can be commuted by inverting the condition.
1762 unsigned PredReg = 0;
1763 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1764 // MOVCC AL can't be inverted. Shouldn't happen.
1765 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1767 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1770 // After swapping the MOVCC operands, also invert the condition.
1771 MI->getOperand(MI->findFirstPredOperandIdx())
1772 .setImm(ARMCC::getOppositeCondition(CC));
1776 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1779 /// Identify instructions that can be folded into a MOVCC instruction, and
1780 /// return the defining instruction.
1781 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1782 const MachineRegisterInfo &MRI,
1783 const TargetInstrInfo *TII) {
1784 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1786 if (!MRI.hasOneNonDBGUse(Reg))
1788 MachineInstr *MI = MRI.getVRegDef(Reg);
1791 // MI is folded into the MOVCC by predicating it.
1792 if (!MI->isPredicable())
1794 // Check if MI has any non-dead defs or physreg uses. This also detects
1795 // predicated instructions which will be reading CPSR.
1796 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1797 const MachineOperand &MO = MI->getOperand(i);
1798 // Reject frame index operands, PEI can't handle the predicated pseudos.
1799 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1803 // MI can't have any tied operands, that would conflict with predication.
1806 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1808 if (MO.isDef() && !MO.isDead())
1811 bool DontMoveAcrossStores = true;
1812 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr,
1813 DontMoveAcrossStores))
1818 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1819 SmallVectorImpl<MachineOperand> &Cond,
1820 unsigned &TrueOp, unsigned &FalseOp,
1821 bool &Optimizable) const {
1822 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1823 "Unknown select instruction");
1828 // 3: Condition code.
1832 Cond.push_back(MI->getOperand(3));
1833 Cond.push_back(MI->getOperand(4));
1834 // We can always fold a def.
1840 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1841 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1842 bool PreferFalse) const {
1843 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1844 "Unknown select instruction");
1845 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1846 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1847 bool Invert = !DefMI;
1849 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1853 // Find new register class to use.
1854 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1855 unsigned DestReg = MI->getOperand(0).getReg();
1856 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1857 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1860 // Create a new predicated version of DefMI.
1861 // Rfalse is the first use.
1862 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1863 DefMI->getDesc(), DestReg);
1865 // Copy all the DefMI operands, excluding its (null) predicate.
1866 const MCInstrDesc &DefDesc = DefMI->getDesc();
1867 for (unsigned i = 1, e = DefDesc.getNumOperands();
1868 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1869 NewMI.addOperand(DefMI->getOperand(i));
1871 unsigned CondCode = MI->getOperand(3).getImm();
1873 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1875 NewMI.addImm(CondCode);
1876 NewMI.addOperand(MI->getOperand(4));
1878 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1879 if (NewMI->hasOptionalDef())
1880 AddDefaultCC(NewMI);
1882 // The output register value when the predicate is false is an implicit
1883 // register operand tied to the first def.
1884 // The tie makes the register allocator ensure the FalseReg is allocated the
1885 // same register as operand 0.
1886 FalseReg.setImplicit();
1887 NewMI.addOperand(FalseReg);
1888 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1890 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1891 SeenMIs.insert(NewMI);
1892 SeenMIs.erase(DefMI);
1894 // The caller will erase MI, but not DefMI.
1895 DefMI->eraseFromParent();
1899 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1900 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1903 /// This will go away once we can teach tblgen how to set the optional CPSR def
1905 struct AddSubFlagsOpcodePair {
1907 uint16_t MachineOpc;
1910 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1911 {ARM::ADDSri, ARM::ADDri},
1912 {ARM::ADDSrr, ARM::ADDrr},
1913 {ARM::ADDSrsi, ARM::ADDrsi},
1914 {ARM::ADDSrsr, ARM::ADDrsr},
1916 {ARM::SUBSri, ARM::SUBri},
1917 {ARM::SUBSrr, ARM::SUBrr},
1918 {ARM::SUBSrsi, ARM::SUBrsi},
1919 {ARM::SUBSrsr, ARM::SUBrsr},
1921 {ARM::RSBSri, ARM::RSBri},
1922 {ARM::RSBSrsi, ARM::RSBrsi},
1923 {ARM::RSBSrsr, ARM::RSBrsr},
1925 {ARM::t2ADDSri, ARM::t2ADDri},
1926 {ARM::t2ADDSrr, ARM::t2ADDrr},
1927 {ARM::t2ADDSrs, ARM::t2ADDrs},
1929 {ARM::t2SUBSri, ARM::t2SUBri},
1930 {ARM::t2SUBSrr, ARM::t2SUBrr},
1931 {ARM::t2SUBSrs, ARM::t2SUBrs},
1933 {ARM::t2RSBSri, ARM::t2RSBri},
1934 {ARM::t2RSBSrs, ARM::t2RSBrs},
1937 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1938 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1939 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1940 return AddSubFlagsOpcodeMap[i].MachineOpc;
1944 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1945 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1946 unsigned DestReg, unsigned BaseReg, int NumBytes,
1947 ARMCC::CondCodes Pred, unsigned PredReg,
1948 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1949 if (NumBytes == 0 && DestReg != BaseReg) {
1950 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1951 .addReg(BaseReg, RegState::Kill)
1952 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1953 .setMIFlags(MIFlags);
1957 bool isSub = NumBytes < 0;
1958 if (isSub) NumBytes = -NumBytes;
1961 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1962 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1963 assert(ThisVal && "Didn't extract field correctly");
1965 // We will handle these bits from offset, clear them.
1966 NumBytes &= ~ThisVal;
1968 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1970 // Build the new ADD / SUB.
1971 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1972 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1973 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1974 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1975 .setMIFlags(MIFlags);
1980 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1982 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1983 Subreg.isValid(); ++Subreg)
1984 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1985 MachineBasicBlock::LQR_Dead)
1989 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1990 MachineFunction &MF, MachineInstr *MI,
1991 unsigned NumBytes) {
1992 // This optimisation potentially adds lots of load and store
1993 // micro-operations, it's only really a great benefit to code-size.
1994 if (!MF.getFunction()->hasFnAttribute(Attribute::MinSize))
1997 // If only one register is pushed/popped, LLVM can use an LDR/STR
1998 // instead. We can't modify those so make sure we're dealing with an
1999 // instruction we understand.
2000 bool IsPop = isPopOpcode(MI->getOpcode());
2001 bool IsPush = isPushOpcode(MI->getOpcode());
2002 if (!IsPush && !IsPop)
2005 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2006 MI->getOpcode() == ARM::VLDMDIA_UPD;
2007 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2008 MI->getOpcode() == ARM::tPOP ||
2009 MI->getOpcode() == ARM::tPOP_RET;
2011 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2012 MI->getOperand(1).getReg() == ARM::SP)) &&
2013 "trying to fold sp update into non-sp-updating push/pop");
2015 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2016 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2017 // if this is violated.
2018 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2021 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2022 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2023 int RegListIdx = IsT1PushPop ? 2 : 4;
2025 // Calculate the space we'll need in terms of registers.
2026 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2027 unsigned RD0Reg, RegsNeeded;
2030 RegsNeeded = NumBytes / 8;
2033 RegsNeeded = NumBytes / 4;
2036 // We're going to have to strip all list operands off before
2037 // re-adding them since the order matters, so save the existing ones
2039 SmallVector<MachineOperand, 4> RegList;
2040 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2041 RegList.push_back(MI->getOperand(i));
2043 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2044 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2046 // Now try to find enough space in the reglist to allocate NumBytes.
2047 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2050 // Pushing any register is completely harmless, mark the
2051 // register involved as undef since we don't care about it in
2053 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2054 false, false, true));
2059 // However, we can only pop an extra register if it's not live. For
2060 // registers live within the function we might clobber a return value
2061 // register; the other way a register can be live here is if it's
2063 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2064 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2065 // can replace isAnySubRegLive().
2066 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2067 isAnySubRegLive(CurReg, TRI, MI)) {
2068 // VFP pops don't allow holes in the register list, so any skip is fatal
2069 // for our transformation. GPR pops do, so we should just keep looking.
2076 // Mark the unimportant registers as <def,dead> in the POP.
2077 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2085 // Finally we know we can profitably perform the optimisation so go
2086 // ahead: strip all existing registers off and add them back again
2087 // in the right order.
2088 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2089 MI->RemoveOperand(i);
2091 // Add the complete list back in.
2092 MachineInstrBuilder MIB(MF, &*MI);
2093 for (int i = RegList.size() - 1; i >= 0; --i)
2094 MIB.addOperand(RegList[i]);
2099 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2100 unsigned FrameReg, int &Offset,
2101 const ARMBaseInstrInfo &TII) {
2102 unsigned Opcode = MI.getOpcode();
2103 const MCInstrDesc &Desc = MI.getDesc();
2104 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2107 // Memory operands in inline assembly always use AddrMode2.
2108 if (Opcode == ARM::INLINEASM)
2109 AddrMode = ARMII::AddrMode2;
2111 if (Opcode == ARM::ADDri) {
2112 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2114 // Turn it into a move.
2115 MI.setDesc(TII.get(ARM::MOVr));
2116 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2117 MI.RemoveOperand(FrameRegIdx+1);
2120 } else if (Offset < 0) {
2123 MI.setDesc(TII.get(ARM::SUBri));
2126 // Common case: small offset, fits into instruction.
2127 if (ARM_AM::getSOImmVal(Offset) != -1) {
2128 // Replace the FrameIndex with sp / fp
2129 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2130 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2135 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2137 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2138 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2140 // We will handle these bits from offset, clear them.
2141 Offset &= ~ThisImmVal;
2143 // Get the properly encoded SOImmVal field.
2144 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2145 "Bit extraction didn't work?");
2146 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2148 unsigned ImmIdx = 0;
2150 unsigned NumBits = 0;
2153 case ARMII::AddrMode_i12: {
2154 ImmIdx = FrameRegIdx + 1;
2155 InstrOffs = MI.getOperand(ImmIdx).getImm();
2159 case ARMII::AddrMode2: {
2160 ImmIdx = FrameRegIdx+2;
2161 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2162 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2167 case ARMII::AddrMode3: {
2168 ImmIdx = FrameRegIdx+2;
2169 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2170 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2175 case ARMII::AddrMode4:
2176 case ARMII::AddrMode6:
2177 // Can't fold any offset even if it's zero.
2179 case ARMII::AddrMode5: {
2180 ImmIdx = FrameRegIdx+1;
2181 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2182 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2189 llvm_unreachable("Unsupported addressing mode!");
2192 Offset += InstrOffs * Scale;
2193 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2199 // Attempt to fold address comp. if opcode has offset bits
2201 // Common case: small offset, fits into instruction.
2202 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2203 int ImmedOffset = Offset / Scale;
2204 unsigned Mask = (1 << NumBits) - 1;
2205 if ((unsigned)Offset <= Mask * Scale) {
2206 // Replace the FrameIndex with sp
2207 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2208 // FIXME: When addrmode2 goes away, this will simplify (like the
2209 // T2 version), as the LDR.i12 versions don't need the encoding
2210 // tricks for the offset value.
2212 if (AddrMode == ARMII::AddrMode_i12)
2213 ImmedOffset = -ImmedOffset;
2215 ImmedOffset |= 1 << NumBits;
2217 ImmOp.ChangeToImmediate(ImmedOffset);
2222 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2223 ImmedOffset = ImmedOffset & Mask;
2225 if (AddrMode == ARMII::AddrMode_i12)
2226 ImmedOffset = -ImmedOffset;
2228 ImmedOffset |= 1 << NumBits;
2230 ImmOp.ChangeToImmediate(ImmedOffset);
2231 Offset &= ~(Mask*Scale);
2235 Offset = (isSub) ? -Offset : Offset;
2239 /// analyzeCompare - For a comparison instruction, return the source registers
2240 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2241 /// compares against in CmpValue. Return true if the comparison instruction
2242 /// can be analyzed.
2243 bool ARMBaseInstrInfo::
2244 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2245 int &CmpMask, int &CmpValue) const {
2246 switch (MI->getOpcode()) {
2250 SrcReg = MI->getOperand(0).getReg();
2253 CmpValue = MI->getOperand(1).getImm();
2257 SrcReg = MI->getOperand(0).getReg();
2258 SrcReg2 = MI->getOperand(1).getReg();
2264 SrcReg = MI->getOperand(0).getReg();
2266 CmpMask = MI->getOperand(1).getImm();
2274 /// isSuitableForMask - Identify a suitable 'and' instruction that
2275 /// operates on the given source register and applies the same mask
2276 /// as a 'tst' instruction. Provide a limited look-through for copies.
2277 /// When successful, MI will hold the found instruction.
2278 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2279 int CmpMask, bool CommonUse) {
2280 switch (MI->getOpcode()) {
2283 if (CmpMask != MI->getOperand(2).getImm())
2285 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2289 // Walk down one instruction which is potentially an 'and'.
2290 const MachineInstr &Copy = *MI;
2291 MachineBasicBlock::iterator AND(
2292 std::next(MachineBasicBlock::iterator(MI)));
2293 if (AND == MI->getParent()->end()) return false;
2295 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2303 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2304 /// the condition code if we modify the instructions such that flags are
2306 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2308 default: return ARMCC::AL;
2309 case ARMCC::EQ: return ARMCC::EQ;
2310 case ARMCC::NE: return ARMCC::NE;
2311 case ARMCC::HS: return ARMCC::LS;
2312 case ARMCC::LO: return ARMCC::HI;
2313 case ARMCC::HI: return ARMCC::LO;
2314 case ARMCC::LS: return ARMCC::HS;
2315 case ARMCC::GE: return ARMCC::LE;
2316 case ARMCC::LT: return ARMCC::GT;
2317 case ARMCC::GT: return ARMCC::LT;
2318 case ARMCC::LE: return ARMCC::GE;
2322 /// isRedundantFlagInstr - check whether the first instruction, whose only
2323 /// purpose is to update flags, can be made redundant.
2324 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2325 /// CMPri can be made redundant by SUBri if the operands are the same.
2326 /// This function can be extended later on.
2327 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2328 unsigned SrcReg2, int ImmValue,
2330 if ((CmpI->getOpcode() == ARM::CMPrr ||
2331 CmpI->getOpcode() == ARM::t2CMPrr) &&
2332 (OI->getOpcode() == ARM::SUBrr ||
2333 OI->getOpcode() == ARM::t2SUBrr) &&
2334 ((OI->getOperand(1).getReg() == SrcReg &&
2335 OI->getOperand(2).getReg() == SrcReg2) ||
2336 (OI->getOperand(1).getReg() == SrcReg2 &&
2337 OI->getOperand(2).getReg() == SrcReg)))
2340 if ((CmpI->getOpcode() == ARM::CMPri ||
2341 CmpI->getOpcode() == ARM::t2CMPri) &&
2342 (OI->getOpcode() == ARM::SUBri ||
2343 OI->getOpcode() == ARM::t2SUBri) &&
2344 OI->getOperand(1).getReg() == SrcReg &&
2345 OI->getOperand(2).getImm() == ImmValue)
2350 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2351 /// comparison into one that sets the zero bit in the flags register;
2352 /// Remove a redundant Compare instruction if an earlier instruction can set the
2353 /// flags in the same way as Compare.
2354 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2355 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2356 /// condition code of instructions which use the flags.
2357 bool ARMBaseInstrInfo::
2358 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2359 int CmpMask, int CmpValue,
2360 const MachineRegisterInfo *MRI) const {
2361 // Get the unique definition of SrcReg.
2362 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2363 if (!MI) return false;
2365 // Masked compares sometimes use the same register as the corresponding 'and'.
2366 if (CmpMask != ~0) {
2367 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2369 for (MachineRegisterInfo::use_instr_iterator
2370 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2372 if (UI->getParent() != CmpInstr->getParent()) continue;
2373 MachineInstr *PotentialAND = &*UI;
2374 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2375 isPredicated(PotentialAND))
2380 if (!MI) return false;
2384 // Get ready to iterate backward from CmpInstr.
2385 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2386 B = CmpInstr->getParent()->begin();
2388 // Early exit if CmpInstr is at the beginning of the BB.
2389 if (I == B) return false;
2391 // There are two possible candidates which can be changed to set CPSR:
2392 // One is MI, the other is a SUB instruction.
2393 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2394 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2395 MachineInstr *Sub = nullptr;
2397 // MI is not a candidate for CMPrr.
2399 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2400 // Conservatively refuse to convert an instruction which isn't in the same
2401 // BB as the comparison.
2402 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2403 // Thus we cannot return here.
2404 if (CmpInstr->getOpcode() == ARM::CMPri ||
2405 CmpInstr->getOpcode() == ARM::t2CMPri)
2411 // Check that CPSR isn't set between the comparison instruction and the one we
2412 // want to change. At the same time, search for Sub.
2413 const TargetRegisterInfo *TRI = &getRegisterInfo();
2415 for (; I != E; --I) {
2416 const MachineInstr &Instr = *I;
2418 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2419 Instr.readsRegister(ARM::CPSR, TRI))
2420 // This instruction modifies or uses CPSR after the one we want to
2421 // change. We can't do this transformation.
2424 // Check whether CmpInstr can be made redundant by the current instruction.
2425 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2431 // The 'and' is below the comparison instruction.
2435 // Return false if no candidates exist.
2439 // The single candidate is called MI.
2442 // We can't use a predicated instruction - it doesn't always write the flags.
2443 if (isPredicated(MI))
2446 switch (MI->getOpcode()) {
2480 case ARM::t2EORri: {
2481 // Scan forward for the use of CPSR
2482 // When checking against MI: if it's a conditional code that requires
2483 // checking of the V bit or C bit, then this is not safe to do.
2484 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2485 // If we are done with the basic block, we need to check whether CPSR is
2487 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2489 bool isSafe = false;
2491 E = CmpInstr->getParent()->end();
2492 while (!isSafe && ++I != E) {
2493 const MachineInstr &Instr = *I;
2494 for (unsigned IO = 0, EO = Instr.getNumOperands();
2495 !isSafe && IO != EO; ++IO) {
2496 const MachineOperand &MO = Instr.getOperand(IO);
2497 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2501 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2507 // Condition code is after the operand before CPSR except for VSELs.
2508 ARMCC::CondCodes CC;
2509 bool IsInstrVSel = true;
2510 switch (Instr.getOpcode()) {
2512 IsInstrVSel = false;
2513 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2534 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2535 if (NewCC == ARMCC::AL)
2537 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2538 // on CMP needs to be updated to be based on SUB.
2539 // Push the condition code operands to OperandsToUpdate.
2540 // If it is safe to remove CmpInstr, the condition code of these
2541 // operands will be modified.
2542 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2543 Sub->getOperand(2).getReg() == SrcReg) {
2544 // VSel doesn't support condition code update.
2547 OperandsToUpdate.push_back(
2548 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2551 // No Sub, so this is x = <op> y, z; cmp x, 0.
2553 case ARMCC::EQ: // Z
2554 case ARMCC::NE: // Z
2555 case ARMCC::MI: // N
2556 case ARMCC::PL: // N
2557 case ARMCC::AL: // none
2558 // CPSR can be used multiple times, we should continue.
2560 case ARMCC::HS: // C
2561 case ARMCC::LO: // C
2562 case ARMCC::VS: // V
2563 case ARMCC::VC: // V
2564 case ARMCC::HI: // C Z
2565 case ARMCC::LS: // C Z
2566 case ARMCC::GE: // N V
2567 case ARMCC::LT: // N V
2568 case ARMCC::GT: // Z N V
2569 case ARMCC::LE: // Z N V
2570 // The instruction uses the V bit or C bit which is not safe.
2577 // If CPSR is not killed nor re-defined, we should check whether it is
2578 // live-out. If it is live-out, do not optimize.
2580 MachineBasicBlock *MBB = CmpInstr->getParent();
2581 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2582 SE = MBB->succ_end(); SI != SE; ++SI)
2583 if ((*SI)->isLiveIn(ARM::CPSR))
2587 // Toggle the optional operand to CPSR.
2588 MI->getOperand(5).setReg(ARM::CPSR);
2589 MI->getOperand(5).setIsDef(true);
2590 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2591 CmpInstr->eraseFromParent();
2593 // Modify the condition code of operands in OperandsToUpdate.
2594 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2595 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2596 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2597 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2605 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2606 MachineInstr *DefMI, unsigned Reg,
2607 MachineRegisterInfo *MRI) const {
2608 // Fold large immediates into add, sub, or, xor.
2609 unsigned DefOpc = DefMI->getOpcode();
2610 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2612 if (!DefMI->getOperand(1).isImm())
2613 // Could be t2MOVi32imm <ga:xx>
2616 if (!MRI->hasOneNonDBGUse(Reg))
2619 const MCInstrDesc &DefMCID = DefMI->getDesc();
2620 if (DefMCID.hasOptionalDef()) {
2621 unsigned NumOps = DefMCID.getNumOperands();
2622 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2623 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2624 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2629 const MCInstrDesc &UseMCID = UseMI->getDesc();
2630 if (UseMCID.hasOptionalDef()) {
2631 unsigned NumOps = UseMCID.getNumOperands();
2632 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2633 // If the instruction sets the flag, do not attempt this optimization
2634 // since it may change the semantics of the code.
2638 unsigned UseOpc = UseMI->getOpcode();
2639 unsigned NewUseOpc = 0;
2640 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2641 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2642 bool Commute = false;
2644 default: return false;
2652 case ARM::t2EORrr: {
2653 Commute = UseMI->getOperand(2).getReg() != Reg;
2660 NewUseOpc = ARM::SUBri;
2666 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2668 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2669 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2672 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2673 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2674 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2678 case ARM::t2SUBrr: {
2682 NewUseOpc = ARM::t2SUBri;
2687 case ARM::t2EORrr: {
2688 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2690 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2691 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2694 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2695 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2696 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2704 unsigned OpIdx = Commute ? 2 : 1;
2705 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2706 bool isKill = UseMI->getOperand(OpIdx).isKill();
2707 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2708 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2709 UseMI, UseMI->getDebugLoc(),
2710 get(NewUseOpc), NewReg)
2711 .addReg(Reg1, getKillRegState(isKill))
2712 .addImm(SOImmValV1)));
2713 UseMI->setDesc(get(NewUseOpc));
2714 UseMI->getOperand(1).setReg(NewReg);
2715 UseMI->getOperand(1).setIsKill();
2716 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2717 DefMI->eraseFromParent();
2721 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2722 const MachineInstr *MI) {
2723 switch (MI->getOpcode()) {
2725 const MCInstrDesc &Desc = MI->getDesc();
2726 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2727 assert(UOps >= 0 && "bad # UOps");
2735 unsigned ShOpVal = MI->getOperand(3).getImm();
2736 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2737 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2740 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2741 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2748 if (!MI->getOperand(2).getReg())
2751 unsigned ShOpVal = MI->getOperand(3).getImm();
2752 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2753 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2756 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2757 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2764 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2766 case ARM::LDRSB_POST:
2767 case ARM::LDRSH_POST: {
2768 unsigned Rt = MI->getOperand(0).getReg();
2769 unsigned Rm = MI->getOperand(3).getReg();
2770 return (Rt == Rm) ? 4 : 3;
2773 case ARM::LDR_PRE_REG:
2774 case ARM::LDRB_PRE_REG: {
2775 unsigned Rt = MI->getOperand(0).getReg();
2776 unsigned Rm = MI->getOperand(3).getReg();
2779 unsigned ShOpVal = MI->getOperand(4).getImm();
2780 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2781 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2784 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2785 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2790 case ARM::STR_PRE_REG:
2791 case ARM::STRB_PRE_REG: {
2792 unsigned ShOpVal = MI->getOperand(4).getImm();
2793 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2794 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2797 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2798 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2804 case ARM::STRH_PRE: {
2805 unsigned Rt = MI->getOperand(0).getReg();
2806 unsigned Rm = MI->getOperand(3).getReg();
2811 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2815 case ARM::LDR_POST_REG:
2816 case ARM::LDRB_POST_REG:
2817 case ARM::LDRH_POST: {
2818 unsigned Rt = MI->getOperand(0).getReg();
2819 unsigned Rm = MI->getOperand(3).getReg();
2820 return (Rt == Rm) ? 3 : 2;
2823 case ARM::LDR_PRE_IMM:
2824 case ARM::LDRB_PRE_IMM:
2825 case ARM::LDR_POST_IMM:
2826 case ARM::LDRB_POST_IMM:
2827 case ARM::STRB_POST_IMM:
2828 case ARM::STRB_POST_REG:
2829 case ARM::STRB_PRE_IMM:
2830 case ARM::STRH_POST:
2831 case ARM::STR_POST_IMM:
2832 case ARM::STR_POST_REG:
2833 case ARM::STR_PRE_IMM:
2836 case ARM::LDRSB_PRE:
2837 case ARM::LDRSH_PRE: {
2838 unsigned Rm = MI->getOperand(3).getReg();
2841 unsigned Rt = MI->getOperand(0).getReg();
2844 unsigned ShOpVal = MI->getOperand(4).getImm();
2845 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2846 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2849 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2850 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2856 unsigned Rt = MI->getOperand(0).getReg();
2857 unsigned Rn = MI->getOperand(2).getReg();
2858 unsigned Rm = MI->getOperand(3).getReg();
2860 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2861 return (Rt == Rn) ? 3 : 2;
2865 unsigned Rm = MI->getOperand(3).getReg();
2867 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2871 case ARM::LDRD_POST:
2872 case ARM::t2LDRD_POST:
2875 case ARM::STRD_POST:
2876 case ARM::t2STRD_POST:
2879 case ARM::LDRD_PRE: {
2880 unsigned Rt = MI->getOperand(0).getReg();
2881 unsigned Rn = MI->getOperand(3).getReg();
2882 unsigned Rm = MI->getOperand(4).getReg();
2884 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2885 return (Rt == Rn) ? 4 : 3;
2888 case ARM::t2LDRD_PRE: {
2889 unsigned Rt = MI->getOperand(0).getReg();
2890 unsigned Rn = MI->getOperand(3).getReg();
2891 return (Rt == Rn) ? 4 : 3;
2894 case ARM::STRD_PRE: {
2895 unsigned Rm = MI->getOperand(4).getReg();
2897 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2901 case ARM::t2STRD_PRE:
2904 case ARM::t2LDR_POST:
2905 case ARM::t2LDRB_POST:
2906 case ARM::t2LDRB_PRE:
2907 case ARM::t2LDRSBi12:
2908 case ARM::t2LDRSBi8:
2909 case ARM::t2LDRSBpci:
2911 case ARM::t2LDRH_POST:
2912 case ARM::t2LDRH_PRE:
2914 case ARM::t2LDRSB_POST:
2915 case ARM::t2LDRSB_PRE:
2916 case ARM::t2LDRSH_POST:
2917 case ARM::t2LDRSH_PRE:
2918 case ARM::t2LDRSHi12:
2919 case ARM::t2LDRSHi8:
2920 case ARM::t2LDRSHpci:
2924 case ARM::t2LDRDi8: {
2925 unsigned Rt = MI->getOperand(0).getReg();
2926 unsigned Rn = MI->getOperand(2).getReg();
2927 return (Rt == Rn) ? 3 : 2;
2930 case ARM::t2STRB_POST:
2931 case ARM::t2STRB_PRE:
2934 case ARM::t2STRH_POST:
2935 case ARM::t2STRH_PRE:
2937 case ARM::t2STR_POST:
2938 case ARM::t2STR_PRE:
2944 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2945 // can't be easily determined return 0 (missing MachineMemOperand).
2947 // FIXME: The current MachineInstr design does not support relying on machine
2948 // mem operands to determine the width of a memory access. Instead, we expect
2949 // the target to provide this information based on the instruction opcode and
2950 // operands. However, using MachineMemOperand is the best solution now for
2953 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2954 // operands. This is much more dangerous than using the MachineMemOperand
2955 // sizes because CodeGen passes can insert/remove optional machine operands. In
2956 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2957 // postRA passes as well.
2959 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2960 // machine model that calls this should handle the unknown (zero size) case.
2962 // Long term, we should require a target hook that verifies MachineMemOperand
2963 // sizes during MC lowering. That target hook should be local to MC lowering
2964 // because we can't ensure that it is aware of other MI forms. Doing this will
2965 // ensure that MachineMemOperands are correctly propagated through all passes.
2966 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2968 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2969 E = MI->memoperands_end(); I != E; ++I) {
2970 Size += (*I)->getSize();
2976 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2977 const MachineInstr *MI) const {
2978 if (!ItinData || ItinData->isEmpty())
2981 const MCInstrDesc &Desc = MI->getDesc();
2982 unsigned Class = Desc.getSchedClass();
2983 int ItinUOps = ItinData->getNumMicroOps(Class);
2984 if (ItinUOps >= 0) {
2985 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2986 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2991 unsigned Opc = MI->getOpcode();
2994 llvm_unreachable("Unexpected multi-uops instruction!");
2999 // The number of uOps for load / store multiple are determined by the number
3002 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3003 // same cycle. The scheduling for the first load / store must be done
3004 // separately by assuming the address is not 64-bit aligned.
3006 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3007 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3008 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3010 case ARM::VLDMDIA_UPD:
3011 case ARM::VLDMDDB_UPD:
3013 case ARM::VLDMSIA_UPD:
3014 case ARM::VLDMSDB_UPD:
3016 case ARM::VSTMDIA_UPD:
3017 case ARM::VSTMDDB_UPD:
3019 case ARM::VSTMSIA_UPD:
3020 case ARM::VSTMSDB_UPD: {
3021 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3022 return (NumRegs / 2) + (NumRegs % 2) + 1;
3025 case ARM::LDMIA_RET:
3030 case ARM::LDMIA_UPD:
3031 case ARM::LDMDA_UPD:
3032 case ARM::LDMDB_UPD:
3033 case ARM::LDMIB_UPD:
3038 case ARM::STMIA_UPD:
3039 case ARM::STMDA_UPD:
3040 case ARM::STMDB_UPD:
3041 case ARM::STMIB_UPD:
3043 case ARM::tLDMIA_UPD:
3044 case ARM::tSTMIA_UPD:
3048 case ARM::t2LDMIA_RET:
3051 case ARM::t2LDMIA_UPD:
3052 case ARM::t2LDMDB_UPD:
3055 case ARM::t2STMIA_UPD:
3056 case ARM::t2STMDB_UPD: {
3057 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3058 if (Subtarget.isSwift()) {
3059 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3062 case ARM::VLDMDIA_UPD:
3063 case ARM::VLDMDDB_UPD:
3064 case ARM::VLDMSIA_UPD:
3065 case ARM::VLDMSDB_UPD:
3066 case ARM::VSTMDIA_UPD:
3067 case ARM::VSTMDDB_UPD:
3068 case ARM::VSTMSIA_UPD:
3069 case ARM::VSTMSDB_UPD:
3070 case ARM::LDMIA_UPD:
3071 case ARM::LDMDA_UPD:
3072 case ARM::LDMDB_UPD:
3073 case ARM::LDMIB_UPD:
3074 case ARM::STMIA_UPD:
3075 case ARM::STMDA_UPD:
3076 case ARM::STMDB_UPD:
3077 case ARM::STMIB_UPD:
3078 case ARM::tLDMIA_UPD:
3079 case ARM::tSTMIA_UPD:
3080 case ARM::t2LDMIA_UPD:
3081 case ARM::t2LDMDB_UPD:
3082 case ARM::t2STMIA_UPD:
3083 case ARM::t2STMDB_UPD:
3084 ++UOps; // One for base register writeback.
3086 case ARM::LDMIA_RET:
3088 case ARM::t2LDMIA_RET:
3089 UOps += 2; // One for base reg wb, one for write to pc.
3093 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3096 // 4 registers would be issued: 2, 2.
3097 // 5 registers would be issued: 2, 2, 1.
3098 int A8UOps = (NumRegs / 2);
3102 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3103 int A9UOps = (NumRegs / 2);
3104 // If there are odd number of registers or if it's not 64-bit aligned,
3105 // then it takes an extra AGU (Address Generation Unit) cycle.
3106 if ((NumRegs % 2) ||
3107 !MI->hasOneMemOperand() ||
3108 (*MI->memoperands_begin())->getAlignment() < 8)
3112 // Assume the worst.
3120 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3121 const MCInstrDesc &DefMCID,
3123 unsigned DefIdx, unsigned DefAlign) const {
3124 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3126 // Def is the address writeback.
3127 return ItinData->getOperandCycle(DefClass, DefIdx);
3130 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3131 // (regno / 2) + (regno % 2) + 1
3132 DefCycle = RegNo / 2 + 1;
3135 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3137 bool isSLoad = false;
3139 switch (DefMCID.getOpcode()) {
3142 case ARM::VLDMSIA_UPD:
3143 case ARM::VLDMSDB_UPD:
3148 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3149 // then it takes an extra cycle.
3150 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3153 // Assume the worst.
3154 DefCycle = RegNo + 2;
3161 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3162 const MCInstrDesc &DefMCID,
3164 unsigned DefIdx, unsigned DefAlign) const {
3165 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3167 // Def is the address writeback.
3168 return ItinData->getOperandCycle(DefClass, DefIdx);
3171 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3172 // 4 registers would be issued: 1, 2, 1.
3173 // 5 registers would be issued: 1, 2, 2.
3174 DefCycle = RegNo / 2;
3177 // Result latency is issue cycle + 2: E2.
3179 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3180 DefCycle = (RegNo / 2);
3181 // If there are odd number of registers or if it's not 64-bit aligned,
3182 // then it takes an extra AGU (Address Generation Unit) cycle.
3183 if ((RegNo % 2) || DefAlign < 8)
3185 // Result latency is AGU cycles + 2.
3188 // Assume the worst.
3189 DefCycle = RegNo + 2;
3196 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3197 const MCInstrDesc &UseMCID,
3199 unsigned UseIdx, unsigned UseAlign) const {
3200 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3202 return ItinData->getOperandCycle(UseClass, UseIdx);
3205 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3206 // (regno / 2) + (regno % 2) + 1
3207 UseCycle = RegNo / 2 + 1;
3210 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3212 bool isSStore = false;
3214 switch (UseMCID.getOpcode()) {
3217 case ARM::VSTMSIA_UPD:
3218 case ARM::VSTMSDB_UPD:
3223 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3224 // then it takes an extra cycle.
3225 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3228 // Assume the worst.
3229 UseCycle = RegNo + 2;
3236 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3237 const MCInstrDesc &UseMCID,
3239 unsigned UseIdx, unsigned UseAlign) const {
3240 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3242 return ItinData->getOperandCycle(UseClass, UseIdx);
3245 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3246 UseCycle = RegNo / 2;
3251 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3252 UseCycle = (RegNo / 2);
3253 // If there are odd number of registers or if it's not 64-bit aligned,
3254 // then it takes an extra AGU (Address Generation Unit) cycle.
3255 if ((RegNo % 2) || UseAlign < 8)
3258 // Assume the worst.
3265 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3266 const MCInstrDesc &DefMCID,
3267 unsigned DefIdx, unsigned DefAlign,
3268 const MCInstrDesc &UseMCID,
3269 unsigned UseIdx, unsigned UseAlign) const {
3270 unsigned DefClass = DefMCID.getSchedClass();
3271 unsigned UseClass = UseMCID.getSchedClass();
3273 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3274 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3276 // This may be a def / use of a variable_ops instruction, the operand
3277 // latency might be determinable dynamically. Let the target try to
3280 bool LdmBypass = false;
3281 switch (DefMCID.getOpcode()) {
3283 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3287 case ARM::VLDMDIA_UPD:
3288 case ARM::VLDMDDB_UPD:
3290 case ARM::VLDMSIA_UPD:
3291 case ARM::VLDMSDB_UPD:
3292 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3295 case ARM::LDMIA_RET:
3300 case ARM::LDMIA_UPD:
3301 case ARM::LDMDA_UPD:
3302 case ARM::LDMDB_UPD:
3303 case ARM::LDMIB_UPD:
3305 case ARM::tLDMIA_UPD:
3307 case ARM::t2LDMIA_RET:
3310 case ARM::t2LDMIA_UPD:
3311 case ARM::t2LDMDB_UPD:
3313 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3318 // We can't seem to determine the result latency of the def, assume it's 2.
3322 switch (UseMCID.getOpcode()) {
3324 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3328 case ARM::VSTMDIA_UPD:
3329 case ARM::VSTMDDB_UPD:
3331 case ARM::VSTMSIA_UPD:
3332 case ARM::VSTMSDB_UPD:
3333 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3340 case ARM::STMIA_UPD:
3341 case ARM::STMDA_UPD:
3342 case ARM::STMDB_UPD:
3343 case ARM::STMIB_UPD:
3344 case ARM::tSTMIA_UPD:
3349 case ARM::t2STMIA_UPD:
3350 case ARM::t2STMDB_UPD:
3351 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3356 // Assume it's read in the first stage.
3359 UseCycle = DefCycle - UseCycle + 1;
3362 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3363 // first def operand.
3364 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3367 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3368 UseClass, UseIdx)) {
3376 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3377 const MachineInstr *MI, unsigned Reg,
3378 unsigned &DefIdx, unsigned &Dist) {
3381 MachineBasicBlock::const_iterator I = MI; ++I;
3382 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3383 assert(II->isInsideBundle() && "Empty bundle?");
3386 while (II->isInsideBundle()) {
3387 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3394 assert(Idx != -1 && "Cannot find bundled definition!");
3399 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3400 const MachineInstr *MI, unsigned Reg,
3401 unsigned &UseIdx, unsigned &Dist) {
3404 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3405 assert(II->isInsideBundle() && "Empty bundle?");
3406 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3408 // FIXME: This doesn't properly handle multiple uses.
3410 while (II != E && II->isInsideBundle()) {
3411 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3414 if (II->getOpcode() != ARM::t2IT)
3428 /// Return the number of cycles to add to (or subtract from) the static
3429 /// itinerary based on the def opcode and alignment. The caller will ensure that
3430 /// adjusted latency is at least one cycle.
3431 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3432 const MachineInstr *DefMI,
3433 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3435 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3436 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3437 // variants are one cycle cheaper.
3438 switch (DefMCID->getOpcode()) {
3442 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3443 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3445 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3452 case ARM::t2LDRSHs: {
3453 // Thumb2 mode: lsl only.
3454 unsigned ShAmt = DefMI->getOperand(3).getImm();
3455 if (ShAmt == 0 || ShAmt == 2)
3460 } else if (Subtarget.isSwift()) {
3461 // FIXME: Properly handle all of the latency adjustments for address
3463 switch (DefMCID->getOpcode()) {
3467 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3468 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3469 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3472 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3473 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3476 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3483 case ARM::t2LDRSHs: {
3484 // Thumb2 mode: lsl only.
3485 unsigned ShAmt = DefMI->getOperand(3).getImm();
3486 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3493 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3494 switch (DefMCID->getOpcode()) {
3500 case ARM::VLD1q8wb_fixed:
3501 case ARM::VLD1q16wb_fixed:
3502 case ARM::VLD1q32wb_fixed:
3503 case ARM::VLD1q64wb_fixed:
3504 case ARM::VLD1q8wb_register:
3505 case ARM::VLD1q16wb_register:
3506 case ARM::VLD1q32wb_register:
3507 case ARM::VLD1q64wb_register:
3514 case ARM::VLD2d8wb_fixed:
3515 case ARM::VLD2d16wb_fixed:
3516 case ARM::VLD2d32wb_fixed:
3517 case ARM::VLD2q8wb_fixed:
3518 case ARM::VLD2q16wb_fixed:
3519 case ARM::VLD2q32wb_fixed:
3520 case ARM::VLD2d8wb_register:
3521 case ARM::VLD2d16wb_register:
3522 case ARM::VLD2d32wb_register:
3523 case ARM::VLD2q8wb_register:
3524 case ARM::VLD2q16wb_register:
3525 case ARM::VLD2q32wb_register:
3530 case ARM::VLD3d8_UPD:
3531 case ARM::VLD3d16_UPD:
3532 case ARM::VLD3d32_UPD:
3533 case ARM::VLD1d64Twb_fixed:
3534 case ARM::VLD1d64Twb_register:
3535 case ARM::VLD3q8_UPD:
3536 case ARM::VLD3q16_UPD:
3537 case ARM::VLD3q32_UPD:
3542 case ARM::VLD4d8_UPD:
3543 case ARM::VLD4d16_UPD:
3544 case ARM::VLD4d32_UPD:
3545 case ARM::VLD1d64Qwb_fixed:
3546 case ARM::VLD1d64Qwb_register:
3547 case ARM::VLD4q8_UPD:
3548 case ARM::VLD4q16_UPD:
3549 case ARM::VLD4q32_UPD:
3550 case ARM::VLD1DUPq8:
3551 case ARM::VLD1DUPq16:
3552 case ARM::VLD1DUPq32:
3553 case ARM::VLD1DUPq8wb_fixed:
3554 case ARM::VLD1DUPq16wb_fixed:
3555 case ARM::VLD1DUPq32wb_fixed:
3556 case ARM::VLD1DUPq8wb_register:
3557 case ARM::VLD1DUPq16wb_register:
3558 case ARM::VLD1DUPq32wb_register:
3559 case ARM::VLD2DUPd8:
3560 case ARM::VLD2DUPd16:
3561 case ARM::VLD2DUPd32:
3562 case ARM::VLD2DUPd8wb_fixed:
3563 case ARM::VLD2DUPd16wb_fixed:
3564 case ARM::VLD2DUPd32wb_fixed:
3565 case ARM::VLD2DUPd8wb_register:
3566 case ARM::VLD2DUPd16wb_register:
3567 case ARM::VLD2DUPd32wb_register:
3568 case ARM::VLD4DUPd8:
3569 case ARM::VLD4DUPd16:
3570 case ARM::VLD4DUPd32:
3571 case ARM::VLD4DUPd8_UPD:
3572 case ARM::VLD4DUPd16_UPD:
3573 case ARM::VLD4DUPd32_UPD:
3575 case ARM::VLD1LNd16:
3576 case ARM::VLD1LNd32:
3577 case ARM::VLD1LNd8_UPD:
3578 case ARM::VLD1LNd16_UPD:
3579 case ARM::VLD1LNd32_UPD:
3581 case ARM::VLD2LNd16:
3582 case ARM::VLD2LNd32:
3583 case ARM::VLD2LNq16:
3584 case ARM::VLD2LNq32:
3585 case ARM::VLD2LNd8_UPD:
3586 case ARM::VLD2LNd16_UPD:
3587 case ARM::VLD2LNd32_UPD:
3588 case ARM::VLD2LNq16_UPD:
3589 case ARM::VLD2LNq32_UPD:
3591 case ARM::VLD4LNd16:
3592 case ARM::VLD4LNd32:
3593 case ARM::VLD4LNq16:
3594 case ARM::VLD4LNq32:
3595 case ARM::VLD4LNd8_UPD:
3596 case ARM::VLD4LNd16_UPD:
3597 case ARM::VLD4LNd32_UPD:
3598 case ARM::VLD4LNq16_UPD:
3599 case ARM::VLD4LNq32_UPD:
3600 // If the address is not 64-bit aligned, the latencies of these
3601 // instructions increases by one.
3612 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3613 const MachineInstr *DefMI, unsigned DefIdx,
3614 const MachineInstr *UseMI,
3615 unsigned UseIdx) const {
3616 // No operand latency. The caller may fall back to getInstrLatency.
3617 if (!ItinData || ItinData->isEmpty())
3620 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3621 unsigned Reg = DefMO.getReg();
3622 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3623 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3625 unsigned DefAdj = 0;
3626 if (DefMI->isBundle()) {
3627 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3628 DefMCID = &DefMI->getDesc();
3630 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3631 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3635 unsigned UseAdj = 0;
3636 if (UseMI->isBundle()) {
3638 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3639 Reg, NewUseIdx, UseAdj);
3645 UseMCID = &UseMI->getDesc();
3648 if (Reg == ARM::CPSR) {
3649 if (DefMI->getOpcode() == ARM::FMSTAT) {
3650 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3651 return Subtarget.isLikeA9() ? 1 : 20;
3654 // CPSR set and branch can be paired in the same cycle.
3655 if (UseMI->isBranch())
3658 // Otherwise it takes the instruction latency (generally one).
3659 unsigned Latency = getInstrLatency(ItinData, DefMI);
3661 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3662 // its uses. Instructions which are otherwise scheduled between them may
3663 // incur a code size penalty (not able to use the CPSR setting 16-bit
3665 if (Latency > 0 && Subtarget.isThumb2()) {
3666 const MachineFunction *MF = DefMI->getParent()->getParent();
3667 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3673 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3676 unsigned DefAlign = DefMI->hasOneMemOperand()
3677 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3678 unsigned UseAlign = UseMI->hasOneMemOperand()
3679 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3681 // Get the itinerary's latency if possible, and handle variable_ops.
3682 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3683 *UseMCID, UseIdx, UseAlign);
3684 // Unable to find operand latency. The caller may resort to getInstrLatency.
3688 // Adjust for IT block position.
3689 int Adj = DefAdj + UseAdj;
3691 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3692 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3693 if (Adj >= 0 || (int)Latency > -Adj) {
3694 return Latency + Adj;
3696 // Return the itinerary latency, which may be zero but not less than zero.
3701 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3702 SDNode *DefNode, unsigned DefIdx,
3703 SDNode *UseNode, unsigned UseIdx) const {
3704 if (!DefNode->isMachineOpcode())
3707 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3709 if (isZeroCost(DefMCID.Opcode))
3712 if (!ItinData || ItinData->isEmpty())
3713 return DefMCID.mayLoad() ? 3 : 1;
3715 if (!UseNode->isMachineOpcode()) {
3716 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3717 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3718 return Latency <= 2 ? 1 : Latency - 1;
3720 return Latency <= 3 ? 1 : Latency - 2;
3723 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3724 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3725 unsigned DefAlign = !DefMN->memoperands_empty()
3726 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3727 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3728 unsigned UseAlign = !UseMN->memoperands_empty()
3729 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3730 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3731 UseMCID, UseIdx, UseAlign);
3734 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3735 Subtarget.isCortexA7())) {
3736 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3737 // variants are one cycle cheaper.
3738 switch (DefMCID.getOpcode()) {
3743 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3744 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3746 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3753 case ARM::t2LDRSHs: {
3754 // Thumb2 mode: lsl only.
3756 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3757 if (ShAmt == 0 || ShAmt == 2)
3762 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3763 // FIXME: Properly handle all of the latency adjustments for address
3765 switch (DefMCID.getOpcode()) {
3770 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3771 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3773 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3774 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3776 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3783 case ARM::t2LDRSHs: {
3784 // Thumb2 mode: lsl 0-3 only.
3791 if (DefAlign < 8 && Subtarget.isLikeA9())
3792 switch (DefMCID.getOpcode()) {
3798 case ARM::VLD1q8wb_register:
3799 case ARM::VLD1q16wb_register:
3800 case ARM::VLD1q32wb_register:
3801 case ARM::VLD1q64wb_register:
3802 case ARM::VLD1q8wb_fixed:
3803 case ARM::VLD1q16wb_fixed:
3804 case ARM::VLD1q32wb_fixed:
3805 case ARM::VLD1q64wb_fixed:
3809 case ARM::VLD2q8Pseudo:
3810 case ARM::VLD2q16Pseudo:
3811 case ARM::VLD2q32Pseudo:
3812 case ARM::VLD2d8wb_fixed:
3813 case ARM::VLD2d16wb_fixed:
3814 case ARM::VLD2d32wb_fixed:
3815 case ARM::VLD2q8PseudoWB_fixed:
3816 case ARM::VLD2q16PseudoWB_fixed:
3817 case ARM::VLD2q32PseudoWB_fixed:
3818 case ARM::VLD2d8wb_register:
3819 case ARM::VLD2d16wb_register:
3820 case ARM::VLD2d32wb_register:
3821 case ARM::VLD2q8PseudoWB_register:
3822 case ARM::VLD2q16PseudoWB_register:
3823 case ARM::VLD2q32PseudoWB_register:
3824 case ARM::VLD3d8Pseudo:
3825 case ARM::VLD3d16Pseudo:
3826 case ARM::VLD3d32Pseudo:
3827 case ARM::VLD1d64TPseudo:
3828 case ARM::VLD1d64TPseudoWB_fixed:
3829 case ARM::VLD3d8Pseudo_UPD:
3830 case ARM::VLD3d16Pseudo_UPD:
3831 case ARM::VLD3d32Pseudo_UPD:
3832 case ARM::VLD3q8Pseudo_UPD:
3833 case ARM::VLD3q16Pseudo_UPD:
3834 case ARM::VLD3q32Pseudo_UPD:
3835 case ARM::VLD3q8oddPseudo:
3836 case ARM::VLD3q16oddPseudo:
3837 case ARM::VLD3q32oddPseudo:
3838 case ARM::VLD3q8oddPseudo_UPD:
3839 case ARM::VLD3q16oddPseudo_UPD:
3840 case ARM::VLD3q32oddPseudo_UPD:
3841 case ARM::VLD4d8Pseudo:
3842 case ARM::VLD4d16Pseudo:
3843 case ARM::VLD4d32Pseudo:
3844 case ARM::VLD1d64QPseudo:
3845 case ARM::VLD1d64QPseudoWB_fixed:
3846 case ARM::VLD4d8Pseudo_UPD:
3847 case ARM::VLD4d16Pseudo_UPD:
3848 case ARM::VLD4d32Pseudo_UPD:
3849 case ARM::VLD4q8Pseudo_UPD:
3850 case ARM::VLD4q16Pseudo_UPD:
3851 case ARM::VLD4q32Pseudo_UPD:
3852 case ARM::VLD4q8oddPseudo:
3853 case ARM::VLD4q16oddPseudo:
3854 case ARM::VLD4q32oddPseudo:
3855 case ARM::VLD4q8oddPseudo_UPD:
3856 case ARM::VLD4q16oddPseudo_UPD:
3857 case ARM::VLD4q32oddPseudo_UPD:
3858 case ARM::VLD1DUPq8:
3859 case ARM::VLD1DUPq16:
3860 case ARM::VLD1DUPq32:
3861 case ARM::VLD1DUPq8wb_fixed:
3862 case ARM::VLD1DUPq16wb_fixed:
3863 case ARM::VLD1DUPq32wb_fixed:
3864 case ARM::VLD1DUPq8wb_register:
3865 case ARM::VLD1DUPq16wb_register:
3866 case ARM::VLD1DUPq32wb_register:
3867 case ARM::VLD2DUPd8:
3868 case ARM::VLD2DUPd16:
3869 case ARM::VLD2DUPd32:
3870 case ARM::VLD2DUPd8wb_fixed:
3871 case ARM::VLD2DUPd16wb_fixed:
3872 case ARM::VLD2DUPd32wb_fixed:
3873 case ARM::VLD2DUPd8wb_register:
3874 case ARM::VLD2DUPd16wb_register:
3875 case ARM::VLD2DUPd32wb_register:
3876 case ARM::VLD4DUPd8Pseudo:
3877 case ARM::VLD4DUPd16Pseudo:
3878 case ARM::VLD4DUPd32Pseudo:
3879 case ARM::VLD4DUPd8Pseudo_UPD:
3880 case ARM::VLD4DUPd16Pseudo_UPD:
3881 case ARM::VLD4DUPd32Pseudo_UPD:
3882 case ARM::VLD1LNq8Pseudo:
3883 case ARM::VLD1LNq16Pseudo:
3884 case ARM::VLD1LNq32Pseudo:
3885 case ARM::VLD1LNq8Pseudo_UPD:
3886 case ARM::VLD1LNq16Pseudo_UPD:
3887 case ARM::VLD1LNq32Pseudo_UPD:
3888 case ARM::VLD2LNd8Pseudo:
3889 case ARM::VLD2LNd16Pseudo:
3890 case ARM::VLD2LNd32Pseudo:
3891 case ARM::VLD2LNq16Pseudo:
3892 case ARM::VLD2LNq32Pseudo:
3893 case ARM::VLD2LNd8Pseudo_UPD:
3894 case ARM::VLD2LNd16Pseudo_UPD:
3895 case ARM::VLD2LNd32Pseudo_UPD:
3896 case ARM::VLD2LNq16Pseudo_UPD:
3897 case ARM::VLD2LNq32Pseudo_UPD:
3898 case ARM::VLD4LNd8Pseudo:
3899 case ARM::VLD4LNd16Pseudo:
3900 case ARM::VLD4LNd32Pseudo:
3901 case ARM::VLD4LNq16Pseudo:
3902 case ARM::VLD4LNq32Pseudo:
3903 case ARM::VLD4LNd8Pseudo_UPD:
3904 case ARM::VLD4LNd16Pseudo_UPD:
3905 case ARM::VLD4LNd32Pseudo_UPD:
3906 case ARM::VLD4LNq16Pseudo_UPD:
3907 case ARM::VLD4LNq32Pseudo_UPD:
3908 // If the address is not 64-bit aligned, the latencies of these
3909 // instructions increases by one.
3917 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3918 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3919 MI->isRegSequence() || MI->isImplicitDef())
3925 const MCInstrDesc &MCID = MI->getDesc();
3927 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3928 // When predicated, CPSR is an additional source operand for CPSR updating
3929 // instructions, this apparently increases their latencies.
3935 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3936 const MachineInstr *MI,
3937 unsigned *PredCost) const {
3938 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3939 MI->isRegSequence() || MI->isImplicitDef())
3942 // An instruction scheduler typically runs on unbundled instructions, however
3943 // other passes may query the latency of a bundled instruction.
3944 if (MI->isBundle()) {
3945 unsigned Latency = 0;
3946 MachineBasicBlock::const_instr_iterator I = MI;
3947 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3948 while (++I != E && I->isInsideBundle()) {
3949 if (I->getOpcode() != ARM::t2IT)
3950 Latency += getInstrLatency(ItinData, I, PredCost);
3955 const MCInstrDesc &MCID = MI->getDesc();
3956 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3957 // When predicated, CPSR is an additional source operand for CPSR updating
3958 // instructions, this apparently increases their latencies.
3961 // Be sure to call getStageLatency for an empty itinerary in case it has a
3962 // valid MinLatency property.
3964 return MI->mayLoad() ? 3 : 1;
3966 unsigned Class = MCID.getSchedClass();
3968 // For instructions with variable uops, use uops as latency.
3969 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3970 return getNumMicroOps(ItinData, MI);
3972 // For the common case, fall back on the itinerary's latency.
3973 unsigned Latency = ItinData->getStageLatency(Class);
3975 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3976 unsigned DefAlign = MI->hasOneMemOperand()
3977 ? (*MI->memoperands_begin())->getAlignment() : 0;
3978 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3979 if (Adj >= 0 || (int)Latency > -Adj) {
3980 return Latency + Adj;
3985 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3986 SDNode *Node) const {
3987 if (!Node->isMachineOpcode())
3990 if (!ItinData || ItinData->isEmpty())
3993 unsigned Opcode = Node->getMachineOpcode();
3996 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4003 bool ARMBaseInstrInfo::
4004 hasHighOperandLatency(const InstrItineraryData *ItinData,
4005 const MachineRegisterInfo *MRI,
4006 const MachineInstr *DefMI, unsigned DefIdx,
4007 const MachineInstr *UseMI, unsigned UseIdx) const {
4008 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4009 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
4010 if (Subtarget.isCortexA8() &&
4011 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4012 // CortexA8 VFP instructions are not pipelined.
4015 // Hoist VFP / NEON instructions with 4 or higher latency.
4016 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
4018 Latency = getInstrLatency(ItinData, DefMI);
4021 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4022 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4025 bool ARMBaseInstrInfo::
4026 hasLowDefLatency(const InstrItineraryData *ItinData,
4027 const MachineInstr *DefMI, unsigned DefIdx) const {
4028 if (!ItinData || ItinData->isEmpty())
4031 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4032 if (DDomain == ARMII::DomainGeneral) {
4033 unsigned DefClass = DefMI->getDesc().getSchedClass();
4034 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4035 return (DefCycle != -1 && DefCycle <= 2);
4040 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4041 StringRef &ErrInfo) const {
4042 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4043 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4049 // LoadStackGuard has so far only been implemented for MachO. Different code
4050 // sequence is needed for other targets.
4051 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4052 unsigned LoadImmOpc,
4054 Reloc::Model RM) const {
4055 MachineBasicBlock &MBB = *MI->getParent();
4056 DebugLoc DL = MI->getDebugLoc();
4057 unsigned Reg = MI->getOperand(0).getReg();
4058 const GlobalValue *GV =
4059 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4060 MachineInstrBuilder MIB;
4062 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4063 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4065 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4066 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4067 MIB.addReg(Reg, RegState::Kill).addImm(0);
4068 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4069 MachineMemOperand *MMO = MBB.getParent()->
4070 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4071 MIB.addMemOperand(MMO);
4072 AddDefaultPred(MIB);
4075 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4076 MIB.addReg(Reg, RegState::Kill).addImm(0);
4077 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4078 AddDefaultPred(MIB);
4082 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4083 unsigned &AddSubOpc,
4084 bool &NegAcc, bool &HasLane) const {
4085 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4086 if (I == MLxEntryMap.end())
4089 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4090 MulOpc = Entry.MulOpc;
4091 AddSubOpc = Entry.AddSubOpc;
4092 NegAcc = Entry.NegAcc;
4093 HasLane = Entry.HasLane;
4097 //===----------------------------------------------------------------------===//
4098 // Execution domains.
4099 //===----------------------------------------------------------------------===//
4101 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4102 // and some can go down both. The vmov instructions go down the VFP pipeline,
4103 // but they can be changed to vorr equivalents that are executed by the NEON
4106 // We use the following execution domain numbering:
4114 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4116 std::pair<uint16_t, uint16_t>
4117 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4118 // If we don't have access to NEON instructions then we won't be able
4119 // to swizzle anything to the NEON domain. Check to make sure.
4120 if (Subtarget.hasNEON()) {
4121 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4122 // if they are not predicated.
4123 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4124 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4126 // CortexA9 is particularly picky about mixing the two and wants these
4128 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4129 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4130 MI->getOpcode() == ARM::VMOVS))
4131 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4133 // No other instructions can be swizzled, so just determine their domain.
4134 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4136 if (Domain & ARMII::DomainNEON)
4137 return std::make_pair(ExeNEON, 0);
4139 // Certain instructions can go either way on Cortex-A8.
4140 // Treat them as NEON instructions.
4141 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4142 return std::make_pair(ExeNEON, 0);
4144 if (Domain & ARMII::DomainVFP)
4145 return std::make_pair(ExeVFP, 0);
4147 return std::make_pair(ExeGeneric, 0);
4150 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4151 unsigned SReg, unsigned &Lane) {
4152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4155 if (DReg != ARM::NoRegister)
4159 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4161 assert(DReg && "S-register with no D super-register?");
4165 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4166 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4167 /// zero if no register needs to be defined as implicit-use.
4169 /// If the function cannot determine if an SPR should be marked implicit use or
4170 /// not, it returns false.
4172 /// This function handles cases where an instruction is being modified from taking
4173 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4174 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4175 /// lane of the DPR).
4177 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4178 /// (including the case where the DPR itself is defined), it should not.
4180 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4182 unsigned DReg, unsigned Lane,
4183 unsigned &ImplicitSReg) {
4184 // If the DPR is defined or used already, the other SPR lane will be chained
4185 // correctly, so there is nothing to be done.
4186 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4191 // Otherwise we need to go searching to see if the SPR is set explicitly.
4192 ImplicitSReg = TRI->getSubReg(DReg,
4193 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4194 MachineBasicBlock::LivenessQueryResult LQR =
4195 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4197 if (LQR == MachineBasicBlock::LQR_Live)
4199 else if (LQR == MachineBasicBlock::LQR_Unknown)
4202 // If the register is known not to be live, there is no need to add an
4209 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4210 unsigned DstReg, SrcReg, DReg;
4212 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4213 const TargetRegisterInfo *TRI = &getRegisterInfo();
4214 switch (MI->getOpcode()) {
4216 llvm_unreachable("cannot handle opcode!");
4219 if (Domain != ExeNEON)
4222 // Zap the predicate operands.
4223 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4225 // Make sure we've got NEON instructions.
4226 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4228 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4229 DstReg = MI->getOperand(0).getReg();
4230 SrcReg = MI->getOperand(1).getReg();
4232 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4233 MI->RemoveOperand(i-1);
4235 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4236 MI->setDesc(get(ARM::VORRd));
4237 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4242 if (Domain != ExeNEON)
4244 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4246 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4247 DstReg = MI->getOperand(0).getReg();
4248 SrcReg = MI->getOperand(1).getReg();
4250 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4251 MI->RemoveOperand(i-1);
4253 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4255 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4256 // Note that DSrc has been widened and the other lane may be undef, which
4257 // contaminates the entire register.
4258 MI->setDesc(get(ARM::VGETLNi32));
4259 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4260 .addReg(DReg, RegState::Undef)
4263 // The old source should be an implicit use, otherwise we might think it
4264 // was dead before here.
4265 MIB.addReg(SrcReg, RegState::Implicit);
4268 if (Domain != ExeNEON)
4270 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4272 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4273 DstReg = MI->getOperand(0).getReg();
4274 SrcReg = MI->getOperand(1).getReg();
4276 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4278 unsigned ImplicitSReg;
4279 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4282 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4283 MI->RemoveOperand(i-1);
4285 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4286 // Again DDst may be undefined at the beginning of this instruction.
4287 MI->setDesc(get(ARM::VSETLNi32));
4288 MIB.addReg(DReg, RegState::Define)
4289 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4292 AddDefaultPred(MIB);
4294 // The narrower destination must be marked as set to keep previous chains
4296 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4297 if (ImplicitSReg != 0)
4298 MIB.addReg(ImplicitSReg, RegState::Implicit);
4302 if (Domain != ExeNEON)
4305 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4306 DstReg = MI->getOperand(0).getReg();
4307 SrcReg = MI->getOperand(1).getReg();
4309 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4310 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4311 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4313 unsigned ImplicitSReg;
4314 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4317 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4318 MI->RemoveOperand(i-1);
4321 // Destination can be:
4322 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4323 MI->setDesc(get(ARM::VDUPLN32d));
4324 MIB.addReg(DDst, RegState::Define)
4325 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4327 AddDefaultPred(MIB);
4329 // Neither the source or the destination are naturally represented any
4330 // more, so add them in manually.
4331 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4332 MIB.addReg(SrcReg, RegState::Implicit);
4333 if (ImplicitSReg != 0)
4334 MIB.addReg(ImplicitSReg, RegState::Implicit);
4338 // In general there's no single instruction that can perform an S <-> S
4339 // move in NEON space, but a pair of VEXT instructions *can* do the
4340 // job. It turns out that the VEXTs needed will only use DSrc once, with
4341 // the position based purely on the combination of lane-0 and lane-1
4342 // involved. For example
4343 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4344 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4345 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4346 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4348 // Pattern of the MachineInstrs is:
4349 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4350 MachineInstrBuilder NewMIB;
4351 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4352 get(ARM::VEXTd32), DDst);
4354 // On the first instruction, both DSrc and DDst may be <undef> if present.
4355 // Specifically when the original instruction didn't have them as an
4357 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4358 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4359 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4361 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4362 CurUndef = !MI->readsRegister(CurReg, TRI);
4363 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4366 AddDefaultPred(NewMIB);
4368 if (SrcLane == DstLane)
4369 NewMIB.addReg(SrcReg, RegState::Implicit);
4371 MI->setDesc(get(ARM::VEXTd32));
4372 MIB.addReg(DDst, RegState::Define);
4374 // On the second instruction, DDst has definitely been defined above, so
4375 // it is not <undef>. DSrc, if present, can be <undef> as above.
4376 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4377 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4378 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4380 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4381 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4382 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4385 AddDefaultPred(MIB);
4387 if (SrcLane != DstLane)
4388 MIB.addReg(SrcReg, RegState::Implicit);
4390 // As before, the original destination is no longer represented, add it
4392 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4393 if (ImplicitSReg != 0)
4394 MIB.addReg(ImplicitSReg, RegState::Implicit);
4401 //===----------------------------------------------------------------------===//
4402 // Partial register updates
4403 //===----------------------------------------------------------------------===//
4405 // Swift renames NEON registers with 64-bit granularity. That means any
4406 // instruction writing an S-reg implicitly reads the containing D-reg. The
4407 // problem is mostly avoided by translating f32 operations to v2f32 operations
4408 // on D-registers, but f32 loads are still a problem.
4410 // These instructions can load an f32 into a NEON register:
4412 // VLDRS - Only writes S, partial D update.
4413 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4414 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4416 // FCONSTD can be used as a dependency-breaking instruction.
4417 unsigned ARMBaseInstrInfo::
4418 getPartialRegUpdateClearance(const MachineInstr *MI,
4420 const TargetRegisterInfo *TRI) const {
4421 if (!SwiftPartialUpdateClearance ||
4422 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4425 assert(TRI && "Need TRI instance");
4427 const MachineOperand &MO = MI->getOperand(OpNum);
4430 unsigned Reg = MO.getReg();
4433 switch(MI->getOpcode()) {
4434 // Normal instructions writing only an S-register.
4439 case ARM::VMOVv4i16:
4440 case ARM::VMOVv2i32:
4441 case ARM::VMOVv2f32:
4442 case ARM::VMOVv1i64:
4443 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4446 // Explicitly reads the dependency.
4447 case ARM::VLD1LNd32:
4454 // If this instruction actually reads a value from Reg, there is no unwanted
4456 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4459 // We must be able to clobber the whole D-reg.
4460 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4461 // Virtual register must be a foo:ssub_0<def,undef> operand.
4462 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4464 } else if (ARM::SPRRegClass.contains(Reg)) {
4465 // Physical register: MI must define the full D-reg.
4466 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4468 if (!DReg || !MI->definesRegister(DReg, TRI))
4472 // MI has an unwanted D-register dependency.
4473 // Avoid defs in the previous N instructrions.
4474 return SwiftPartialUpdateClearance;
4477 // Break a partial register dependency after getPartialRegUpdateClearance
4478 // returned non-zero.
4479 void ARMBaseInstrInfo::
4480 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4482 const TargetRegisterInfo *TRI) const {
4483 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4484 assert(TRI && "Need TRI instance");
4486 const MachineOperand &MO = MI->getOperand(OpNum);
4487 unsigned Reg = MO.getReg();
4488 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4489 "Can't break virtual register dependencies.");
4490 unsigned DReg = Reg;
4492 // If MI defines an S-reg, find the corresponding D super-register.
4493 if (ARM::SPRRegClass.contains(Reg)) {
4494 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4495 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4498 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4499 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4501 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4502 // the full D-register by loading the same value to both lanes. The
4503 // instruction is micro-coded with 2 uops, so don't do this until we can
4504 // properly schedule micro-coded instructions. The dispatcher stalls cause
4505 // too big regressions.
4507 // Insert the dependency-breaking FCONSTD before MI.
4508 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4509 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4510 get(ARM::FCONSTD), DReg).addImm(96));
4511 MI->addRegisterKilled(DReg, TRI, true);
4514 bool ARMBaseInstrInfo::hasNOP() const {
4515 return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
4518 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4519 if (MI->getNumOperands() < 4)
4521 unsigned ShOpVal = MI->getOperand(3).getImm();
4522 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4523 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4524 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4525 ((ShImm == 1 || ShImm == 2) &&
4526 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4532 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4533 const MachineInstr &MI, unsigned DefIdx,
4534 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4535 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4536 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4538 switch (MI.getOpcode()) {
4540 // dX = VMOVDRR rY, rZ
4542 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4543 // Populate the InputRegs accordingly.
4545 const MachineOperand *MOReg = &MI.getOperand(1);
4546 InputRegs.push_back(
4547 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4549 MOReg = &MI.getOperand(2);
4550 InputRegs.push_back(
4551 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4554 llvm_unreachable("Target dependent opcode missing");
4557 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4558 const MachineInstr &MI, unsigned DefIdx,
4559 RegSubRegPairAndIdx &InputReg) const {
4560 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4561 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4563 switch (MI.getOpcode()) {
4565 // rX, rY = VMOVRRD dZ
4567 // rX = EXTRACT_SUBREG dZ, ssub_0
4568 // rY = EXTRACT_SUBREG dZ, ssub_1
4569 const MachineOperand &MOReg = MI.getOperand(2);
4570 InputReg.Reg = MOReg.getReg();
4571 InputReg.SubReg = MOReg.getSubReg();
4572 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4575 llvm_unreachable("Target dependent opcode missing");
4578 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4579 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4580 RegSubRegPairAndIdx &InsertedReg) const {
4581 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4582 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4584 switch (MI.getOpcode()) {
4585 case ARM::VSETLNi32:
4586 // dX = VSETLNi32 dY, rZ, imm
4587 const MachineOperand &MOBaseReg = MI.getOperand(1);
4588 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4589 const MachineOperand &MOIndex = MI.getOperand(3);
4590 BaseReg.Reg = MOBaseReg.getReg();
4591 BaseReg.SubReg = MOBaseReg.getSubReg();
4593 InsertedReg.Reg = MOInsertedReg.getReg();
4594 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4595 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4598 llvm_unreachable("Target dependent opcode missing");