1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMGenInstrInfo.inc"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalValue.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
41 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
42 cl::desc("Enable ARM 2-addr to 3-addr conv"));
44 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
46 unsigned MLxOpc; // MLA / MLS opcode
47 unsigned MulOpc; // Expanded multiplication opcode
48 unsigned AddSubOpc; // Expanded add / sub opcode
49 bool NegAcc; // True if the acc is negated before the add / sub.
50 bool HasLane; // True if instruction has an extra "lane" operand.
53 static const ARM_MLxEntry ARM_MLxTable[] = {
54 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
56 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
57 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
58 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
59 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
60 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
61 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
62 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
63 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
66 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
67 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
68 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
69 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
70 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
71 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
72 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
73 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
76 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
77 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
79 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
80 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
81 assert(false && "Duplicated entries?");
82 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
83 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
87 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
88 // currently defaults to no prepass hazard recognizer.
89 ScheduleHazardRecognizer *ARMBaseInstrInfo::
90 CreateTargetHazardRecognizer(const TargetMachine *TM,
91 const ScheduleDAG *DAG) const {
92 if (usePreRAHazardRecognizer()) {
93 const InstrItineraryData *II = TM->getInstrItineraryData();
94 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
96 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
99 ScheduleHazardRecognizer *ARMBaseInstrInfo::
100 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
101 const ScheduleDAG *DAG) const {
102 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
103 return (ScheduleHazardRecognizer *)
104 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
105 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
109 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
110 MachineBasicBlock::iterator &MBBI,
111 LiveVariables *LV) const {
112 // FIXME: Thumb2 support.
117 MachineInstr *MI = MBBI;
118 MachineFunction &MF = *MI->getParent()->getParent();
119 uint64_t TSFlags = MI->getDesc().TSFlags;
121 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
122 default: return NULL;
123 case ARMII::IndexModePre:
126 case ARMII::IndexModePost:
130 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
132 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
136 MachineInstr *UpdateMI = NULL;
137 MachineInstr *MemMI = NULL;
138 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
139 const TargetInstrDesc &TID = MI->getDesc();
140 unsigned NumOps = TID.getNumOperands();
141 bool isLoad = !TID.mayStore();
142 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
143 const MachineOperand &Base = MI->getOperand(2);
144 const MachineOperand &Offset = MI->getOperand(NumOps-3);
145 unsigned WBReg = WB.getReg();
146 unsigned BaseReg = Base.getReg();
147 unsigned OffReg = Offset.getReg();
148 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
149 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
152 assert(false && "Unknown indexed op!");
154 case ARMII::AddrMode2: {
155 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
156 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
158 if (ARM_AM::getSOImmVal(Amt) == -1)
159 // Can't encode it in a so_imm operand. This transformation will
160 // add more than 1 instruction. Abandon!
162 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
163 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
164 .addReg(BaseReg).addImm(Amt)
165 .addImm(Pred).addReg(0).addReg(0);
166 } else if (Amt != 0) {
167 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
168 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
169 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
170 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
171 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
172 .addImm(Pred).addReg(0).addReg(0);
174 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
176 .addReg(BaseReg).addReg(OffReg)
177 .addImm(Pred).addReg(0).addReg(0);
180 case ARMII::AddrMode3 : {
181 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
182 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
184 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
187 .addReg(BaseReg).addImm(Amt)
188 .addImm(Pred).addReg(0).addReg(0);
190 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
192 .addReg(BaseReg).addReg(OffReg)
193 .addImm(Pred).addReg(0).addReg(0);
198 std::vector<MachineInstr*> NewMIs;
201 MemMI = BuildMI(MF, MI->getDebugLoc(),
202 get(MemOpc), MI->getOperand(0).getReg())
203 .addReg(WBReg).addImm(0).addImm(Pred);
205 MemMI = BuildMI(MF, MI->getDebugLoc(),
206 get(MemOpc)).addReg(MI->getOperand(1).getReg())
207 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
208 NewMIs.push_back(MemMI);
209 NewMIs.push_back(UpdateMI);
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(BaseReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
220 UpdateMI->getOperand(0).setIsDead();
221 NewMIs.push_back(UpdateMI);
222 NewMIs.push_back(MemMI);
225 // Transfer LiveVariables states, kill / dead info.
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
229 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
230 unsigned Reg = MO.getReg();
232 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
234 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
236 LV->addVirtualRegisterDead(Reg, NewMI);
238 if (MO.isUse() && MO.isKill()) {
239 for (unsigned j = 0; j < 2; ++j) {
240 // Look at the two new MI's in reverse order.
241 MachineInstr *NewMI = NewMIs[j];
242 if (!NewMI->readsRegister(Reg))
244 LV->addVirtualRegisterKilled(Reg, NewMI);
245 if (VI.removeKill(MI))
246 VI.Kills.push_back(NewMI);
254 MFI->insert(MBBI, NewMIs[1]);
255 MFI->insert(MBBI, NewMIs[0]);
261 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
262 MachineBasicBlock *&FBB,
263 SmallVectorImpl<MachineOperand> &Cond,
264 bool AllowModify) const {
265 // If the block has no terminators, it just falls into the block after it.
266 MachineBasicBlock::iterator I = MBB.end();
267 if (I == MBB.begin())
270 while (I->isDebugValue()) {
271 if (I == MBB.begin())
275 if (!isUnpredicatedTerminator(I))
278 // Get the last instruction in the block.
279 MachineInstr *LastInst = I;
281 // If there is only one terminator instruction, process it.
282 unsigned LastOpc = LastInst->getOpcode();
283 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
284 if (isUncondBranchOpcode(LastOpc)) {
285 TBB = LastInst->getOperand(0).getMBB();
288 if (isCondBranchOpcode(LastOpc)) {
289 // Block ends with fall-through condbranch.
290 TBB = LastInst->getOperand(0).getMBB();
291 Cond.push_back(LastInst->getOperand(1));
292 Cond.push_back(LastInst->getOperand(2));
295 return true; // Can't handle indirect branch.
298 // Get the instruction before it if it is a terminator.
299 MachineInstr *SecondLastInst = I;
300 unsigned SecondLastOpc = SecondLastInst->getOpcode();
302 // If AllowModify is true and the block ends with two or more unconditional
303 // branches, delete all but the first unconditional branch.
304 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
305 while (isUncondBranchOpcode(SecondLastOpc)) {
306 LastInst->eraseFromParent();
307 LastInst = SecondLastInst;
308 LastOpc = LastInst->getOpcode();
309 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
310 // Return now the only terminator is an unconditional branch.
311 TBB = LastInst->getOperand(0).getMBB();
315 SecondLastOpc = SecondLastInst->getOpcode();
320 // If there are three terminators, we don't know what sort of block this is.
321 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
324 // If the block ends with a B and a Bcc, handle it.
325 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
326 TBB = SecondLastInst->getOperand(0).getMBB();
327 Cond.push_back(SecondLastInst->getOperand(1));
328 Cond.push_back(SecondLastInst->getOperand(2));
329 FBB = LastInst->getOperand(0).getMBB();
333 // If the block ends with two unconditional branches, handle it. The second
334 // one is not executed, so remove it.
335 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
336 TBB = SecondLastInst->getOperand(0).getMBB();
339 I->eraseFromParent();
343 // ...likewise if it ends with a branch table followed by an unconditional
344 // branch. The branch folder can create these, and we must get rid of them for
345 // correctness of Thumb constant islands.
346 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
347 isIndirectBranchOpcode(SecondLastOpc)) &&
348 isUncondBranchOpcode(LastOpc)) {
351 I->eraseFromParent();
355 // Otherwise, can't handle this.
360 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
361 MachineBasicBlock::iterator I = MBB.end();
362 if (I == MBB.begin()) return 0;
364 while (I->isDebugValue()) {
365 if (I == MBB.begin())
369 if (!isUncondBranchOpcode(I->getOpcode()) &&
370 !isCondBranchOpcode(I->getOpcode()))
373 // Remove the branch.
374 I->eraseFromParent();
378 if (I == MBB.begin()) return 1;
380 if (!isCondBranchOpcode(I->getOpcode()))
383 // Remove the branch.
384 I->eraseFromParent();
389 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
390 MachineBasicBlock *FBB,
391 const SmallVectorImpl<MachineOperand> &Cond,
393 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
394 int BOpc = !AFI->isThumbFunction()
395 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
396 int BccOpc = !AFI->isThumbFunction()
397 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
399 // Shouldn't be a fall through.
400 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
401 assert((Cond.size() == 2 || Cond.size() == 0) &&
402 "ARM branch conditions have two components!");
405 if (Cond.empty()) // Unconditional branch?
406 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
408 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
409 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
413 // Two-way conditional branch.
414 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
415 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
420 bool ARMBaseInstrInfo::
421 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
422 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
423 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
427 bool ARMBaseInstrInfo::
428 PredicateInstruction(MachineInstr *MI,
429 const SmallVectorImpl<MachineOperand> &Pred) const {
430 unsigned Opc = MI->getOpcode();
431 if (isUncondBranchOpcode(Opc)) {
432 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
433 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
434 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
438 int PIdx = MI->findFirstPredOperandIdx();
440 MachineOperand &PMO = MI->getOperand(PIdx);
441 PMO.setImm(Pred[0].getImm());
442 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
448 bool ARMBaseInstrInfo::
449 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
450 const SmallVectorImpl<MachineOperand> &Pred2) const {
451 if (Pred1.size() > 2 || Pred2.size() > 2)
454 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
455 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
465 return CC2 == ARMCC::HI;
467 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
469 return CC2 == ARMCC::GT;
471 return CC2 == ARMCC::LT;
475 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
476 std::vector<MachineOperand> &Pred) const {
477 // FIXME: This confuses implicit_def with optional CPSR def.
478 const TargetInstrDesc &TID = MI->getDesc();
479 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
483 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
484 const MachineOperand &MO = MI->getOperand(i);
485 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
494 /// isPredicable - Return true if the specified instruction can be predicated.
495 /// By default, this returns true for every instruction with a
496 /// PredicateOperand.
497 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
498 const TargetInstrDesc &TID = MI->getDesc();
499 if (!TID.isPredicable())
502 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
503 ARMFunctionInfo *AFI =
504 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
505 return AFI->isThumb2Function();
510 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
511 LLVM_ATTRIBUTE_NOINLINE
512 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
514 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
516 assert(JTI < JT.size());
517 return JT[JTI].MBBs.size();
520 /// GetInstSize - Return the size of the specified MachineInstr.
522 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
523 const MachineBasicBlock &MBB = *MI->getParent();
524 const MachineFunction *MF = MBB.getParent();
525 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
527 // Basic size info comes from the TSFlags field.
528 const TargetInstrDesc &TID = MI->getDesc();
529 uint64_t TSFlags = TID.TSFlags;
531 unsigned Opc = MI->getOpcode();
532 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
534 // If this machine instr is an inline asm, measure it.
535 if (MI->getOpcode() == ARM::INLINEASM)
536 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
541 llvm_unreachable("Unknown or unset size field for instr!");
542 case TargetOpcode::IMPLICIT_DEF:
543 case TargetOpcode::KILL:
544 case TargetOpcode::PROLOG_LABEL:
545 case TargetOpcode::EH_LABEL:
546 case TargetOpcode::DBG_VALUE:
551 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
552 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
553 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
554 case ARMII::SizeSpecial: {
556 case ARM::MOVi16_ga_pcrel:
557 case ARM::MOVTi16_ga_pcrel:
558 case ARM::t2MOVi16_ga_pcrel:
559 case ARM::t2MOVTi16_ga_pcrel:
562 case ARM::t2MOVi32imm:
564 case ARM::CONSTPOOL_ENTRY:
565 // If this machine instr is a constant pool entry, its size is recorded as
567 return MI->getOperand(2).getImm();
568 case ARM::Int_eh_sjlj_longjmp:
570 case ARM::tInt_eh_sjlj_longjmp:
572 case ARM::Int_eh_sjlj_setjmp:
573 case ARM::Int_eh_sjlj_setjmp_nofp:
575 case ARM::tInt_eh_sjlj_setjmp:
576 case ARM::t2Int_eh_sjlj_setjmp:
577 case ARM::t2Int_eh_sjlj_setjmp_nofp:
585 case ARM::t2TBH_JT: {
586 // These are jumptable branches, i.e. a branch followed by an inlined
587 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
588 // entry is one byte; TBH two byte each.
589 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
590 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
591 unsigned NumOps = TID.getNumOperands();
592 MachineOperand JTOP =
593 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
594 unsigned JTI = JTOP.getIndex();
595 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
597 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
598 assert(JTI < JT.size());
599 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
600 // 4 aligned. The assembler / linker may add 2 byte padding just before
601 // the JT entries. The size does not include this padding; the
602 // constant islands pass does separate bookkeeping for it.
603 // FIXME: If we know the size of the function is less than (1 << 16) *2
604 // bytes, we can use 16-bit entries instead. Then there won't be an
606 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
607 unsigned NumEntries = getNumJTEntries(JT, JTI);
608 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
609 // Make sure the instruction that follows TBB is 2-byte aligned.
610 // FIXME: Constant island pass should insert an "ALIGN" instruction
613 return NumEntries * EntrySize + InstSize;
616 // Otherwise, pseudo-instruction sizes are zero.
621 return 0; // Not reached
624 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
625 MachineBasicBlock::iterator I, DebugLoc DL,
626 unsigned DestReg, unsigned SrcReg,
627 bool KillSrc) const {
628 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
629 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
631 if (GPRDest && GPRSrc) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
633 .addReg(SrcReg, getKillRegState(KillSrc))));
637 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
638 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
641 if (SPRDest && SPRSrc)
643 else if (GPRDest && SPRSrc)
645 else if (SPRDest && GPRSrc)
647 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
649 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
651 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
653 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
656 llvm_unreachable("Impossible reg-to-reg copy");
658 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
659 MIB.addReg(SrcReg, getKillRegState(KillSrc));
660 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
665 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
666 unsigned Reg, unsigned SubIdx, unsigned State,
667 const TargetRegisterInfo *TRI) {
669 return MIB.addReg(Reg, State);
671 if (TargetRegisterInfo::isPhysicalRegister(Reg))
672 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
673 return MIB.addReg(Reg, State, SubIdx);
676 void ARMBaseInstrInfo::
677 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
678 unsigned SrcReg, bool isKill, int FI,
679 const TargetRegisterClass *RC,
680 const TargetRegisterInfo *TRI) const {
682 if (I != MBB.end()) DL = I->getDebugLoc();
683 MachineFunction &MF = *MBB.getParent();
684 MachineFrameInfo &MFI = *MF.getFrameInfo();
685 unsigned Align = MFI.getObjectAlignment(FI);
687 MachineMemOperand *MMO =
688 MF.getMachineMemOperand(MachinePointerInfo(
689 PseudoSourceValue::getFixedStack(FI)),
690 MachineMemOperand::MOStore,
691 MFI.getObjectSize(FI),
694 // tGPR is used sometimes in ARM instructions that need to avoid using
695 // certain registers. Just treat it as GPR here. Likewise, rGPR.
696 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
697 || RC == ARM::rGPRRegisterClass)
698 RC = ARM::GPRRegisterClass;
700 switch (RC->getID()) {
701 case ARM::GPRRegClassID:
702 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
703 .addReg(SrcReg, getKillRegState(isKill))
704 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
706 case ARM::SPRRegClassID:
707 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
708 .addReg(SrcReg, getKillRegState(isKill))
709 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
711 case ARM::DPRRegClassID:
712 case ARM::DPR_VFP2RegClassID:
713 case ARM::DPR_8RegClassID:
714 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
715 .addReg(SrcReg, getKillRegState(isKill))
716 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
718 case ARM::QPRRegClassID:
719 case ARM::QPR_VFP2RegClassID:
720 case ARM::QPR_8RegClassID:
721 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
722 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
723 .addFrameIndex(FI).addImm(16)
724 .addReg(SrcReg, getKillRegState(isKill))
725 .addMemOperand(MMO));
727 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
728 .addReg(SrcReg, getKillRegState(isKill))
730 .addMemOperand(MMO));
733 case ARM::QQPRRegClassID:
734 case ARM::QQPR_VFP2RegClassID:
735 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
736 // FIXME: It's possible to only store part of the QQ register if the
737 // spilled def has a sub-register index.
738 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
739 .addFrameIndex(FI).addImm(16)
740 .addReg(SrcReg, getKillRegState(isKill))
741 .addMemOperand(MMO));
743 MachineInstrBuilder MIB =
744 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
747 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
748 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
749 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
750 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
753 case ARM::QQQQPRRegClassID: {
754 MachineInstrBuilder MIB =
755 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
758 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
759 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
760 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
761 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
762 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
763 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
764 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
765 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
769 llvm_unreachable("Unknown regclass!");
774 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
775 int &FrameIndex) const {
776 switch (MI->getOpcode()) {
779 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
780 if (MI->getOperand(1).isFI() &&
781 MI->getOperand(2).isReg() &&
782 MI->getOperand(3).isImm() &&
783 MI->getOperand(2).getReg() == 0 &&
784 MI->getOperand(3).getImm() == 0) {
785 FrameIndex = MI->getOperand(1).getIndex();
786 return MI->getOperand(0).getReg();
794 if (MI->getOperand(1).isFI() &&
795 MI->getOperand(2).isImm() &&
796 MI->getOperand(2).getImm() == 0) {
797 FrameIndex = MI->getOperand(1).getIndex();
798 return MI->getOperand(0).getReg();
801 case ARM::VST1q64Pseudo:
802 if (MI->getOperand(0).isFI() &&
803 MI->getOperand(2).getSubReg() == 0) {
804 FrameIndex = MI->getOperand(0).getIndex();
805 return MI->getOperand(2).getReg();
809 if (MI->getOperand(1).isFI() &&
810 MI->getOperand(0).getSubReg() == 0) {
811 FrameIndex = MI->getOperand(1).getIndex();
812 return MI->getOperand(0).getReg();
820 void ARMBaseInstrInfo::
821 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
822 unsigned DestReg, int FI,
823 const TargetRegisterClass *RC,
824 const TargetRegisterInfo *TRI) const {
826 if (I != MBB.end()) DL = I->getDebugLoc();
827 MachineFunction &MF = *MBB.getParent();
828 MachineFrameInfo &MFI = *MF.getFrameInfo();
829 unsigned Align = MFI.getObjectAlignment(FI);
830 MachineMemOperand *MMO =
831 MF.getMachineMemOperand(
832 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
833 MachineMemOperand::MOLoad,
834 MFI.getObjectSize(FI),
837 // tGPR is used sometimes in ARM instructions that need to avoid using
838 // certain registers. Just treat it as GPR here.
839 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
840 || RC == ARM::rGPRRegisterClass)
841 RC = ARM::GPRRegisterClass;
843 switch (RC->getID()) {
844 case ARM::GPRRegClassID:
845 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
846 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
848 case ARM::SPRRegClassID:
849 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
850 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
852 case ARM::DPRRegClassID:
853 case ARM::DPR_VFP2RegClassID:
854 case ARM::DPR_8RegClassID:
855 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
856 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
858 case ARM::QPRRegClassID:
859 case ARM::QPR_VFP2RegClassID:
860 case ARM::QPR_8RegClassID:
861 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
862 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
863 .addFrameIndex(FI).addImm(16)
864 .addMemOperand(MMO));
866 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
868 .addMemOperand(MMO));
871 case ARM::QQPRRegClassID:
872 case ARM::QQPR_VFP2RegClassID:
873 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
874 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
875 .addFrameIndex(FI).addImm(16)
876 .addMemOperand(MMO));
878 MachineInstrBuilder MIB =
879 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
882 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
883 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
884 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
885 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
888 case ARM::QQQQPRRegClassID: {
889 MachineInstrBuilder MIB =
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
893 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
894 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
895 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
896 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
897 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
898 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
899 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
900 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
904 llvm_unreachable("Unknown regclass!");
909 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
910 int &FrameIndex) const {
911 switch (MI->getOpcode()) {
914 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
915 if (MI->getOperand(1).isFI() &&
916 MI->getOperand(2).isReg() &&
917 MI->getOperand(3).isImm() &&
918 MI->getOperand(2).getReg() == 0 &&
919 MI->getOperand(3).getImm() == 0) {
920 FrameIndex = MI->getOperand(1).getIndex();
921 return MI->getOperand(0).getReg();
929 if (MI->getOperand(1).isFI() &&
930 MI->getOperand(2).isImm() &&
931 MI->getOperand(2).getImm() == 0) {
932 FrameIndex = MI->getOperand(1).getIndex();
933 return MI->getOperand(0).getReg();
936 case ARM::VLD1q64Pseudo:
937 if (MI->getOperand(1).isFI() &&
938 MI->getOperand(0).getSubReg() == 0) {
939 FrameIndex = MI->getOperand(1).getIndex();
940 return MI->getOperand(0).getReg();
944 if (MI->getOperand(1).isFI() &&
945 MI->getOperand(0).getSubReg() == 0) {
946 FrameIndex = MI->getOperand(1).getIndex();
947 return MI->getOperand(0).getReg();
956 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
957 int FrameIx, uint64_t Offset,
960 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
961 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
965 /// Create a copy of a const pool value. Update CPI to the new index and return
967 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
968 MachineConstantPool *MCP = MF.getConstantPool();
969 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
971 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
972 assert(MCPE.isMachineConstantPoolEntry() &&
973 "Expecting a machine constantpool entry!");
974 ARMConstantPoolValue *ACPV =
975 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
977 unsigned PCLabelId = AFI->createPICLabelUId();
978 ARMConstantPoolValue *NewCPV = 0;
979 // FIXME: The below assumes PIC relocation model and that the function
980 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
981 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
982 // instructions, so that's probably OK, but is PIC always correct when
984 if (ACPV->isGlobalValue())
985 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
987 else if (ACPV->isExtSymbol())
988 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
989 ACPV->getSymbol(), PCLabelId, 4);
990 else if (ACPV->isBlockAddress())
991 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
992 ARMCP::CPBlockAddress, 4);
993 else if (ACPV->isLSDA())
994 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
997 llvm_unreachable("Unexpected ARM constantpool value type!!");
998 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1002 void ARMBaseInstrInfo::
1003 reMaterialize(MachineBasicBlock &MBB,
1004 MachineBasicBlock::iterator I,
1005 unsigned DestReg, unsigned SubIdx,
1006 const MachineInstr *Orig,
1007 const TargetRegisterInfo &TRI) const {
1008 unsigned Opcode = Orig->getOpcode();
1011 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1012 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1016 case ARM::tLDRpci_pic:
1017 case ARM::t2LDRpci_pic: {
1018 MachineFunction &MF = *MBB.getParent();
1019 unsigned CPI = Orig->getOperand(1).getIndex();
1020 unsigned PCLabelId = duplicateCPV(MF, CPI);
1021 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1023 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1024 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1031 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1032 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1033 switch(Orig->getOpcode()) {
1034 case ARM::tLDRpci_pic:
1035 case ARM::t2LDRpci_pic: {
1036 unsigned CPI = Orig->getOperand(1).getIndex();
1037 unsigned PCLabelId = duplicateCPV(MF, CPI);
1038 Orig->getOperand(1).setIndex(CPI);
1039 Orig->getOperand(2).setImm(PCLabelId);
1046 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1047 const MachineInstr *MI1,
1048 const MachineRegisterInfo *MRI) const {
1049 int Opcode = MI0->getOpcode();
1050 if (Opcode == ARM::t2LDRpci ||
1051 Opcode == ARM::t2LDRpci_pic ||
1052 Opcode == ARM::tLDRpci ||
1053 Opcode == ARM::tLDRpci_pic ||
1054 Opcode == ARM::MOV_ga_dyn ||
1055 Opcode == ARM::MOV_ga_pcrel ||
1056 Opcode == ARM::MOV_ga_pcrel_ldr ||
1057 Opcode == ARM::t2MOV_ga_dyn ||
1058 Opcode == ARM::t2MOV_ga_pcrel) {
1059 if (MI1->getOpcode() != Opcode)
1061 if (MI0->getNumOperands() != MI1->getNumOperands())
1064 const MachineOperand &MO0 = MI0->getOperand(1);
1065 const MachineOperand &MO1 = MI1->getOperand(1);
1066 if (MO0.getOffset() != MO1.getOffset())
1069 if (Opcode == ARM::MOV_ga_dyn ||
1070 Opcode == ARM::MOV_ga_pcrel ||
1071 Opcode == ARM::MOV_ga_pcrel_ldr ||
1072 Opcode == ARM::t2MOV_ga_dyn ||
1073 Opcode == ARM::t2MOV_ga_pcrel)
1074 // Ignore the PC labels.
1075 return MO0.getGlobal() == MO1.getGlobal();
1077 const MachineFunction *MF = MI0->getParent()->getParent();
1078 const MachineConstantPool *MCP = MF->getConstantPool();
1079 int CPI0 = MO0.getIndex();
1080 int CPI1 = MO1.getIndex();
1081 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1082 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1083 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1084 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1085 if (isARMCP0 && isARMCP1) {
1086 ARMConstantPoolValue *ACPV0 =
1087 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1088 ARMConstantPoolValue *ACPV1 =
1089 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1090 return ACPV0->hasSameValue(ACPV1);
1091 } else if (!isARMCP0 && !isARMCP1) {
1092 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1095 } else if (Opcode == ARM::PICLDR) {
1096 if (MI1->getOpcode() != Opcode)
1098 if (MI0->getNumOperands() != MI1->getNumOperands())
1101 unsigned Addr0 = MI0->getOperand(1).getReg();
1102 unsigned Addr1 = MI1->getOperand(1).getReg();
1103 if (Addr0 != Addr1) {
1105 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1106 !TargetRegisterInfo::isVirtualRegister(Addr1))
1109 // This assumes SSA form.
1110 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1111 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1112 // Check if the loaded value, e.g. a constantpool of a global address, are
1114 if (!produceSameValue(Def0, Def1, MRI))
1118 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1119 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1120 const MachineOperand &MO0 = MI0->getOperand(i);
1121 const MachineOperand &MO1 = MI1->getOperand(i);
1122 if (!MO0.isIdenticalTo(MO1))
1128 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1131 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1132 /// determine if two loads are loading from the same base address. It should
1133 /// only return true if the base pointers are the same and the only differences
1134 /// between the two addresses is the offset. It also returns the offsets by
1136 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1138 int64_t &Offset2) const {
1139 // Don't worry about Thumb: just ARM and Thumb2.
1140 if (Subtarget.isThumb1Only()) return false;
1142 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1145 switch (Load1->getMachineOpcode()) {
1158 case ARM::t2LDRSHi8:
1160 case ARM::t2LDRSHi12:
1164 switch (Load2->getMachineOpcode()) {
1177 case ARM::t2LDRSHi8:
1179 case ARM::t2LDRSHi12:
1183 // Check if base addresses and chain operands match.
1184 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1185 Load1->getOperand(4) != Load2->getOperand(4))
1188 // Index should be Reg0.
1189 if (Load1->getOperand(3) != Load2->getOperand(3))
1192 // Determine the offsets.
1193 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1194 isa<ConstantSDNode>(Load2->getOperand(1))) {
1195 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1196 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1203 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1204 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1205 /// be scheduled togther. On some targets if two loads are loading from
1206 /// addresses in the same cache line, it's better if they are scheduled
1207 /// together. This function takes two integers that represent the load offsets
1208 /// from the common base address. It returns true if it decides it's desirable
1209 /// to schedule the two loads together. "NumLoads" is the number of loads that
1210 /// have already been scheduled after Load1.
1211 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1212 int64_t Offset1, int64_t Offset2,
1213 unsigned NumLoads) const {
1214 // Don't worry about Thumb: just ARM and Thumb2.
1215 if (Subtarget.isThumb1Only()) return false;
1217 assert(Offset2 > Offset1);
1219 if ((Offset2 - Offset1) / 8 > 64)
1222 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1223 return false; // FIXME: overly conservative?
1225 // Four loads in a row should be sufficient.
1232 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1233 const MachineBasicBlock *MBB,
1234 const MachineFunction &MF) const {
1235 // Debug info is never a scheduling boundary. It's necessary to be explicit
1236 // due to the special treatment of IT instructions below, otherwise a
1237 // dbg_value followed by an IT will result in the IT instruction being
1238 // considered a scheduling hazard, which is wrong. It should be the actual
1239 // instruction preceding the dbg_value instruction(s), just like it is
1240 // when debug info is not present.
1241 if (MI->isDebugValue())
1244 // Terminators and labels can't be scheduled around.
1245 if (MI->getDesc().isTerminator() || MI->isLabel())
1248 // Treat the start of the IT block as a scheduling boundary, but schedule
1249 // t2IT along with all instructions following it.
1250 // FIXME: This is a big hammer. But the alternative is to add all potential
1251 // true and anti dependencies to IT block instructions as implicit operands
1252 // to the t2IT instruction. The added compile time and complexity does not
1254 MachineBasicBlock::const_iterator I = MI;
1255 // Make sure to skip any dbg_value instructions
1256 while (++I != MBB->end() && I->isDebugValue())
1258 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1261 // Don't attempt to schedule around any instruction that defines
1262 // a stack-oriented pointer, as it's unlikely to be profitable. This
1263 // saves compile time, because it doesn't require every single
1264 // stack slot reference to depend on the instruction that does the
1266 if (MI->definesRegister(ARM::SP))
1272 bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1274 unsigned ExtraPredCycles,
1276 float Confidence) const {
1280 // Attempt to estimate the relative costs of predication versus branching.
1281 float UnpredCost = Probability * NumCycles;
1282 UnpredCost += 1.0; // The branch itself
1283 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1285 return (float)(NumCycles + ExtraPredCycles) < UnpredCost;
1288 bool ARMBaseInstrInfo::
1289 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1290 unsigned TCycles, unsigned TExtra,
1291 MachineBasicBlock &FMBB,
1292 unsigned FCycles, unsigned FExtra,
1293 float Probability, float Confidence) const {
1294 if (!TCycles || !FCycles)
1297 // Attempt to estimate the relative costs of predication versus branching.
1298 float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles;
1299 UnpredCost += 1.0; // The branch itself
1300 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1302 return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost;
1305 /// getInstrPredicate - If instruction is predicated, returns its predicate
1306 /// condition, otherwise returns AL. It also returns the condition code
1307 /// register by reference.
1309 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1310 int PIdx = MI->findFirstPredOperandIdx();
1316 PredReg = MI->getOperand(PIdx+1).getReg();
1317 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1321 int llvm::getMatchingCondBranchOpcode(int Opc) {
1324 else if (Opc == ARM::tB)
1326 else if (Opc == ARM::t2B)
1329 llvm_unreachable("Unknown unconditional branch opcode!");
1334 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1335 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1336 unsigned DestReg, unsigned BaseReg, int NumBytes,
1337 ARMCC::CondCodes Pred, unsigned PredReg,
1338 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1339 bool isSub = NumBytes < 0;
1340 if (isSub) NumBytes = -NumBytes;
1343 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1344 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1345 assert(ThisVal && "Didn't extract field correctly");
1347 // We will handle these bits from offset, clear them.
1348 NumBytes &= ~ThisVal;
1350 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1352 // Build the new ADD / SUB.
1353 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1354 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1355 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1356 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1357 .setMIFlags(MIFlags);
1362 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1363 unsigned FrameReg, int &Offset,
1364 const ARMBaseInstrInfo &TII) {
1365 unsigned Opcode = MI.getOpcode();
1366 const TargetInstrDesc &Desc = MI.getDesc();
1367 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1370 // Memory operands in inline assembly always use AddrMode2.
1371 if (Opcode == ARM::INLINEASM)
1372 AddrMode = ARMII::AddrMode2;
1374 if (Opcode == ARM::ADDri) {
1375 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1377 // Turn it into a move.
1378 MI.setDesc(TII.get(ARM::MOVr));
1379 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1380 MI.RemoveOperand(FrameRegIdx+1);
1383 } else if (Offset < 0) {
1386 MI.setDesc(TII.get(ARM::SUBri));
1389 // Common case: small offset, fits into instruction.
1390 if (ARM_AM::getSOImmVal(Offset) != -1) {
1391 // Replace the FrameIndex with sp / fp
1392 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1393 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1398 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1400 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1401 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1403 // We will handle these bits from offset, clear them.
1404 Offset &= ~ThisImmVal;
1406 // Get the properly encoded SOImmVal field.
1407 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1408 "Bit extraction didn't work?");
1409 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1411 unsigned ImmIdx = 0;
1413 unsigned NumBits = 0;
1416 case ARMII::AddrMode_i12: {
1417 ImmIdx = FrameRegIdx + 1;
1418 InstrOffs = MI.getOperand(ImmIdx).getImm();
1422 case ARMII::AddrMode2: {
1423 ImmIdx = FrameRegIdx+2;
1424 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1425 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1430 case ARMII::AddrMode3: {
1431 ImmIdx = FrameRegIdx+2;
1432 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1433 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1438 case ARMII::AddrMode4:
1439 case ARMII::AddrMode6:
1440 // Can't fold any offset even if it's zero.
1442 case ARMII::AddrMode5: {
1443 ImmIdx = FrameRegIdx+1;
1444 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1445 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1452 llvm_unreachable("Unsupported addressing mode!");
1456 Offset += InstrOffs * Scale;
1457 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1463 // Attempt to fold address comp. if opcode has offset bits
1465 // Common case: small offset, fits into instruction.
1466 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1467 int ImmedOffset = Offset / Scale;
1468 unsigned Mask = (1 << NumBits) - 1;
1469 if ((unsigned)Offset <= Mask * Scale) {
1470 // Replace the FrameIndex with sp
1471 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1472 // FIXME: When addrmode2 goes away, this will simplify (like the
1473 // T2 version), as the LDR.i12 versions don't need the encoding
1474 // tricks for the offset value.
1476 if (AddrMode == ARMII::AddrMode_i12)
1477 ImmedOffset = -ImmedOffset;
1479 ImmedOffset |= 1 << NumBits;
1481 ImmOp.ChangeToImmediate(ImmedOffset);
1486 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1487 ImmedOffset = ImmedOffset & Mask;
1489 if (AddrMode == ARMII::AddrMode_i12)
1490 ImmedOffset = -ImmedOffset;
1492 ImmedOffset |= 1 << NumBits;
1494 ImmOp.ChangeToImmediate(ImmedOffset);
1495 Offset &= ~(Mask*Scale);
1499 Offset = (isSub) ? -Offset : Offset;
1503 bool ARMBaseInstrInfo::
1504 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1505 int &CmpValue) const {
1506 switch (MI->getOpcode()) {
1510 SrcReg = MI->getOperand(0).getReg();
1512 CmpValue = MI->getOperand(1).getImm();
1516 SrcReg = MI->getOperand(0).getReg();
1517 CmpMask = MI->getOperand(1).getImm();
1525 /// isSuitableForMask - Identify a suitable 'and' instruction that
1526 /// operates on the given source register and applies the same mask
1527 /// as a 'tst' instruction. Provide a limited look-through for copies.
1528 /// When successful, MI will hold the found instruction.
1529 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1530 int CmpMask, bool CommonUse) {
1531 switch (MI->getOpcode()) {
1534 if (CmpMask != MI->getOperand(2).getImm())
1536 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1540 // Walk down one instruction which is potentially an 'and'.
1541 const MachineInstr &Copy = *MI;
1542 MachineBasicBlock::iterator AND(
1543 llvm::next(MachineBasicBlock::iterator(MI)));
1544 if (AND == MI->getParent()->end()) return false;
1546 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1554 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1555 /// comparison into one that sets the zero bit in the flags register.
1556 bool ARMBaseInstrInfo::
1557 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1558 int CmpValue, const MachineRegisterInfo *MRI) const {
1562 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1563 if (llvm::next(DI) != MRI->def_end())
1564 // Only support one definition.
1567 MachineInstr *MI = &*DI;
1569 // Masked compares sometimes use the same register as the corresponding 'and'.
1570 if (CmpMask != ~0) {
1571 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1573 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1574 UE = MRI->use_end(); UI != UE; ++UI) {
1575 if (UI->getParent() != CmpInstr->getParent()) continue;
1576 MachineInstr *PotentialAND = &*UI;
1577 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1582 if (!MI) return false;
1586 // Conservatively refuse to convert an instruction which isn't in the same BB
1587 // as the comparison.
1588 if (MI->getParent() != CmpInstr->getParent())
1591 // Check that CPSR isn't set between the comparison instruction and the one we
1593 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1594 B = MI->getParent()->begin();
1596 // Early exit if CmpInstr is at the beginning of the BB.
1597 if (I == B) return false;
1600 for (; I != E; --I) {
1601 const MachineInstr &Instr = *I;
1603 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1604 const MachineOperand &MO = Instr.getOperand(IO);
1605 if (!MO.isReg()) continue;
1607 // This instruction modifies or uses CPSR after the one we want to
1608 // change. We can't do this transformation.
1609 if (MO.getReg() == ARM::CPSR)
1614 // The 'and' is below the comparison instruction.
1618 // Set the "zero" bit in CPSR.
1619 switch (MI->getOpcode()) {
1631 case ARM::t2SBCri: {
1632 // Scan forward for the use of CPSR, if it's a conditional code requires
1633 // checking of V bit, then this is not safe to do. If we can't find the
1634 // CPSR use (i.e. used in another block), then it's not safe to perform
1635 // the optimization.
1636 bool isSafe = false;
1638 E = MI->getParent()->end();
1639 while (!isSafe && ++I != E) {
1640 const MachineInstr &Instr = *I;
1641 for (unsigned IO = 0, EO = Instr.getNumOperands();
1642 !isSafe && IO != EO; ++IO) {
1643 const MachineOperand &MO = Instr.getOperand(IO);
1644 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1650 // Condition code is after the operand before CPSR.
1651 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1674 // Toggle the optional operand to CPSR.
1675 MI->getOperand(5).setReg(ARM::CPSR);
1676 MI->getOperand(5).setIsDef(true);
1677 CmpInstr->eraseFromParent();
1684 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1685 MachineInstr *DefMI, unsigned Reg,
1686 MachineRegisterInfo *MRI) const {
1687 // Fold large immediates into add, sub, or, xor.
1688 unsigned DefOpc = DefMI->getOpcode();
1689 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1691 if (!DefMI->getOperand(1).isImm())
1692 // Could be t2MOVi32imm <ga:xx>
1695 if (!MRI->hasOneNonDBGUse(Reg))
1698 unsigned UseOpc = UseMI->getOpcode();
1699 unsigned NewUseOpc = 0;
1700 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1701 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1702 bool Commute = false;
1704 default: return false;
1712 case ARM::t2EORrr: {
1713 Commute = UseMI->getOperand(2).getReg() != Reg;
1720 NewUseOpc = ARM::SUBri;
1726 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1728 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1729 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1732 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1733 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1734 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1738 case ARM::t2SUBrr: {
1742 NewUseOpc = ARM::t2SUBri;
1747 case ARM::t2EORrr: {
1748 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1750 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1751 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1754 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1755 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1756 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1764 unsigned OpIdx = Commute ? 2 : 1;
1765 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1766 bool isKill = UseMI->getOperand(OpIdx).isKill();
1767 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1768 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1769 *UseMI, UseMI->getDebugLoc(),
1770 get(NewUseOpc), NewReg)
1771 .addReg(Reg1, getKillRegState(isKill))
1772 .addImm(SOImmValV1)));
1773 UseMI->setDesc(get(NewUseOpc));
1774 UseMI->getOperand(1).setReg(NewReg);
1775 UseMI->getOperand(1).setIsKill();
1776 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1777 DefMI->eraseFromParent();
1782 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1783 const MachineInstr *MI) const {
1784 if (!ItinData || ItinData->isEmpty())
1787 const TargetInstrDesc &Desc = MI->getDesc();
1788 unsigned Class = Desc.getSchedClass();
1789 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1793 unsigned Opc = MI->getOpcode();
1796 llvm_unreachable("Unexpected multi-uops instruction!");
1802 // The number of uOps for load / store multiple are determined by the number
1805 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1806 // same cycle. The scheduling for the first load / store must be done
1807 // separately by assuming the the address is not 64-bit aligned.
1809 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1810 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1811 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1813 case ARM::VLDMDIA_UPD:
1814 case ARM::VLDMDDB_UPD:
1816 case ARM::VLDMSIA_UPD:
1817 case ARM::VLDMSDB_UPD:
1819 case ARM::VSTMDIA_UPD:
1820 case ARM::VSTMDDB_UPD:
1822 case ARM::VSTMSIA_UPD:
1823 case ARM::VSTMSDB_UPD: {
1824 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1825 return (NumRegs / 2) + (NumRegs % 2) + 1;
1828 case ARM::LDMIA_RET:
1833 case ARM::LDMIA_UPD:
1834 case ARM::LDMDA_UPD:
1835 case ARM::LDMDB_UPD:
1836 case ARM::LDMIB_UPD:
1841 case ARM::STMIA_UPD:
1842 case ARM::STMDA_UPD:
1843 case ARM::STMDB_UPD:
1844 case ARM::STMIB_UPD:
1846 case ARM::tLDMIA_UPD:
1848 case ARM::tSTMIA_UPD:
1852 case ARM::t2LDMIA_RET:
1855 case ARM::t2LDMIA_UPD:
1856 case ARM::t2LDMDB_UPD:
1859 case ARM::t2STMIA_UPD:
1860 case ARM::t2STMDB_UPD: {
1861 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1862 if (Subtarget.isCortexA8()) {
1865 // 4 registers would be issued: 2, 2.
1866 // 5 registers would be issued: 2, 2, 1.
1867 UOps = (NumRegs / 2);
1871 } else if (Subtarget.isCortexA9()) {
1872 UOps = (NumRegs / 2);
1873 // If there are odd number of registers or if it's not 64-bit aligned,
1874 // then it takes an extra AGU (Address Generation Unit) cycle.
1875 if ((NumRegs % 2) ||
1876 !MI->hasOneMemOperand() ||
1877 (*MI->memoperands_begin())->getAlignment() < 8)
1881 // Assume the worst.
1889 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1890 const TargetInstrDesc &DefTID,
1892 unsigned DefIdx, unsigned DefAlign) const {
1893 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1895 // Def is the address writeback.
1896 return ItinData->getOperandCycle(DefClass, DefIdx);
1899 if (Subtarget.isCortexA8()) {
1900 // (regno / 2) + (regno % 2) + 1
1901 DefCycle = RegNo / 2 + 1;
1904 } else if (Subtarget.isCortexA9()) {
1906 bool isSLoad = false;
1908 switch (DefTID.getOpcode()) {
1911 case ARM::VLDMSIA_UPD:
1912 case ARM::VLDMSDB_UPD:
1917 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1918 // then it takes an extra cycle.
1919 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1922 // Assume the worst.
1923 DefCycle = RegNo + 2;
1930 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1931 const TargetInstrDesc &DefTID,
1933 unsigned DefIdx, unsigned DefAlign) const {
1934 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1936 // Def is the address writeback.
1937 return ItinData->getOperandCycle(DefClass, DefIdx);
1940 if (Subtarget.isCortexA8()) {
1941 // 4 registers would be issued: 1, 2, 1.
1942 // 5 registers would be issued: 1, 2, 2.
1943 DefCycle = RegNo / 2;
1946 // Result latency is issue cycle + 2: E2.
1948 } else if (Subtarget.isCortexA9()) {
1949 DefCycle = (RegNo / 2);
1950 // If there are odd number of registers or if it's not 64-bit aligned,
1951 // then it takes an extra AGU (Address Generation Unit) cycle.
1952 if ((RegNo % 2) || DefAlign < 8)
1954 // Result latency is AGU cycles + 2.
1957 // Assume the worst.
1958 DefCycle = RegNo + 2;
1965 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1966 const TargetInstrDesc &UseTID,
1968 unsigned UseIdx, unsigned UseAlign) const {
1969 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1971 return ItinData->getOperandCycle(UseClass, UseIdx);
1974 if (Subtarget.isCortexA8()) {
1975 // (regno / 2) + (regno % 2) + 1
1976 UseCycle = RegNo / 2 + 1;
1979 } else if (Subtarget.isCortexA9()) {
1981 bool isSStore = false;
1983 switch (UseTID.getOpcode()) {
1986 case ARM::VSTMSIA_UPD:
1987 case ARM::VSTMSDB_UPD:
1992 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1993 // then it takes an extra cycle.
1994 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
1997 // Assume the worst.
1998 UseCycle = RegNo + 2;
2005 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2006 const TargetInstrDesc &UseTID,
2008 unsigned UseIdx, unsigned UseAlign) const {
2009 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
2011 return ItinData->getOperandCycle(UseClass, UseIdx);
2014 if (Subtarget.isCortexA8()) {
2015 UseCycle = RegNo / 2;
2020 } else if (Subtarget.isCortexA9()) {
2021 UseCycle = (RegNo / 2);
2022 // If there are odd number of registers or if it's not 64-bit aligned,
2023 // then it takes an extra AGU (Address Generation Unit) cycle.
2024 if ((RegNo % 2) || UseAlign < 8)
2027 // Assume the worst.
2034 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2035 const TargetInstrDesc &DefTID,
2036 unsigned DefIdx, unsigned DefAlign,
2037 const TargetInstrDesc &UseTID,
2038 unsigned UseIdx, unsigned UseAlign) const {
2039 unsigned DefClass = DefTID.getSchedClass();
2040 unsigned UseClass = UseTID.getSchedClass();
2042 if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
2043 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2045 // This may be a def / use of a variable_ops instruction, the operand
2046 // latency might be determinable dynamically. Let the target try to
2049 bool LdmBypass = false;
2050 switch (DefTID.getOpcode()) {
2052 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2056 case ARM::VLDMDIA_UPD:
2057 case ARM::VLDMDDB_UPD:
2059 case ARM::VLDMSIA_UPD:
2060 case ARM::VLDMSDB_UPD:
2061 DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2064 case ARM::LDMIA_RET:
2069 case ARM::LDMIA_UPD:
2070 case ARM::LDMDA_UPD:
2071 case ARM::LDMDB_UPD:
2072 case ARM::LDMIB_UPD:
2074 case ARM::tLDMIA_UPD:
2076 case ARM::t2LDMIA_RET:
2079 case ARM::t2LDMIA_UPD:
2080 case ARM::t2LDMDB_UPD:
2082 DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2087 // We can't seem to determine the result latency of the def, assume it's 2.
2091 switch (UseTID.getOpcode()) {
2093 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2097 case ARM::VSTMDIA_UPD:
2098 case ARM::VSTMDDB_UPD:
2100 case ARM::VSTMSIA_UPD:
2101 case ARM::VSTMSDB_UPD:
2102 UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2109 case ARM::STMIA_UPD:
2110 case ARM::STMDA_UPD:
2111 case ARM::STMDB_UPD:
2112 case ARM::STMIB_UPD:
2114 case ARM::tSTMIA_UPD:
2119 case ARM::t2STMIA_UPD:
2120 case ARM::t2STMDB_UPD:
2121 UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2126 // Assume it's read in the first stage.
2129 UseCycle = DefCycle - UseCycle + 1;
2132 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2133 // first def operand.
2134 if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
2137 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2138 UseClass, UseIdx)) {
2147 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2148 const MachineInstr *DefMI, unsigned DefIdx,
2149 const MachineInstr *UseMI, unsigned UseIdx) const {
2150 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2151 DefMI->isRegSequence() || DefMI->isImplicitDef())
2154 const TargetInstrDesc &DefTID = DefMI->getDesc();
2155 if (!ItinData || ItinData->isEmpty())
2156 return DefTID.mayLoad() ? 3 : 1;
2158 const TargetInstrDesc &UseTID = UseMI->getDesc();
2159 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2160 if (DefMO.getReg() == ARM::CPSR) {
2161 if (DefMI->getOpcode() == ARM::FMSTAT) {
2162 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2163 return Subtarget.isCortexA9() ? 1 : 20;
2166 // CPSR set and branch can be paired in the same cycle.
2167 if (UseTID.isBranch())
2171 unsigned DefAlign = DefMI->hasOneMemOperand()
2172 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2173 unsigned UseAlign = UseMI->hasOneMemOperand()
2174 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2175 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2176 UseTID, UseIdx, UseAlign);
2179 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2180 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2181 // variants are one cycle cheaper.
2182 switch (DefTID.getOpcode()) {
2186 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2187 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2189 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2196 case ARM::t2LDRSHs: {
2197 // Thumb2 mode: lsl only.
2198 unsigned ShAmt = DefMI->getOperand(3).getImm();
2199 if (ShAmt == 0 || ShAmt == 2)
2210 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2211 SDNode *DefNode, unsigned DefIdx,
2212 SDNode *UseNode, unsigned UseIdx) const {
2213 if (!DefNode->isMachineOpcode())
2216 const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
2218 if (isZeroCost(DefTID.Opcode))
2221 if (!ItinData || ItinData->isEmpty())
2222 return DefTID.mayLoad() ? 3 : 1;
2224 if (!UseNode->isMachineOpcode()) {
2225 int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
2226 if (Subtarget.isCortexA9())
2227 return Latency <= 2 ? 1 : Latency - 1;
2229 return Latency <= 3 ? 1 : Latency - 2;
2232 const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
2233 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2234 unsigned DefAlign = !DefMN->memoperands_empty()
2235 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2236 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2237 unsigned UseAlign = !UseMN->memoperands_empty()
2238 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2239 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2240 UseTID, UseIdx, UseAlign);
2243 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2244 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2245 // variants are one cycle cheaper.
2246 switch (DefTID.getOpcode()) {
2251 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2252 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2254 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2261 case ARM::t2LDRSHs: {
2262 // Thumb2 mode: lsl only.
2264 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2265 if (ShAmt == 0 || ShAmt == 2)
2275 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2276 const MachineInstr *MI,
2277 unsigned *PredCost) const {
2278 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2279 MI->isRegSequence() || MI->isImplicitDef())
2282 if (!ItinData || ItinData->isEmpty())
2285 const TargetInstrDesc &TID = MI->getDesc();
2286 unsigned Class = TID.getSchedClass();
2287 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2288 if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR))
2289 // When predicated, CPSR is an additional source operand for CPSR updating
2290 // instructions, this apparently increases their latencies.
2293 return ItinData->getStageLatency(Class);
2294 return getNumMicroOps(ItinData, MI);
2297 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2298 SDNode *Node) const {
2299 if (!Node->isMachineOpcode())
2302 if (!ItinData || ItinData->isEmpty())
2305 unsigned Opcode = Node->getMachineOpcode();
2308 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2315 bool ARMBaseInstrInfo::
2316 hasHighOperandLatency(const InstrItineraryData *ItinData,
2317 const MachineRegisterInfo *MRI,
2318 const MachineInstr *DefMI, unsigned DefIdx,
2319 const MachineInstr *UseMI, unsigned UseIdx) const {
2320 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2321 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2322 if (Subtarget.isCortexA8() &&
2323 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2324 // CortexA8 VFP instructions are not pipelined.
2327 // Hoist VFP / NEON instructions with 4 or higher latency.
2328 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2331 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2332 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2335 bool ARMBaseInstrInfo::
2336 hasLowDefLatency(const InstrItineraryData *ItinData,
2337 const MachineInstr *DefMI, unsigned DefIdx) const {
2338 if (!ItinData || ItinData->isEmpty())
2341 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2342 if (DDomain == ARMII::DomainGeneral) {
2343 unsigned DefClass = DefMI->getDesc().getSchedClass();
2344 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2345 return (DefCycle != -1 && DefCycle <= 2);
2351 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2352 unsigned &AddSubOpc,
2353 bool &NegAcc, bool &HasLane) const {
2354 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2355 if (I == MLxEntryMap.end())
2358 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2359 MulOpc = Entry.MulOpc;
2360 AddSubOpc = Entry.AddSubOpc;
2361 NegAcc = Entry.NegAcc;
2362 HasLane = Entry.HasLane;