1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231 storeRegToStackSlot(MBB, MI, Reg, isKill,
232 CSI[i].getFrameIdx(), RC, TRI);
239 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240 MachineBasicBlock *&FBB,
241 SmallVectorImpl<MachineOperand> &Cond,
242 bool AllowModify) const {
243 // If the block has no terminators, it just falls into the block after it.
244 MachineBasicBlock::iterator I = MBB.end();
245 if (I == MBB.begin())
248 while (I->isDebugValue()) {
249 if (I == MBB.begin())
253 if (!isUnpredicatedTerminator(I))
256 // Get the last instruction in the block.
257 MachineInstr *LastInst = I;
259 // If there is only one terminator instruction, process it.
260 unsigned LastOpc = LastInst->getOpcode();
261 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262 if (isUncondBranchOpcode(LastOpc)) {
263 TBB = LastInst->getOperand(0).getMBB();
266 if (isCondBranchOpcode(LastOpc)) {
267 // Block ends with fall-through condbranch.
268 TBB = LastInst->getOperand(0).getMBB();
269 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(LastInst->getOperand(2));
273 return true; // Can't handle indirect branch.
276 // Get the instruction before it if it is a terminator.
277 MachineInstr *SecondLastInst = I;
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
283 // If the block ends with a B and a Bcc, handle it.
284 unsigned SecondLastOpc = SecondLastInst->getOpcode();
285 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286 TBB = SecondLastInst->getOperand(0).getMBB();
287 Cond.push_back(SecondLastInst->getOperand(1));
288 Cond.push_back(SecondLastInst->getOperand(2));
289 FBB = LastInst->getOperand(0).getMBB();
293 // If the block ends with two unconditional branches, handle it. The second
294 // one is not executed, so remove it.
295 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296 TBB = SecondLastInst->getOperand(0).getMBB();
299 I->eraseFromParent();
303 // ...likewise if it ends with a branch table followed by an unconditional
304 // branch. The branch folder can create these, and we must get rid of them for
305 // correctness of Thumb constant islands.
306 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307 isIndirectBranchOpcode(SecondLastOpc)) &&
308 isUncondBranchOpcode(LastOpc)) {
311 I->eraseFromParent();
315 // Otherwise, can't handle this.
320 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 while (I->isDebugValue()) {
325 if (I == MBB.begin())
329 if (!isUncondBranchOpcode(I->getOpcode()) &&
330 !isCondBranchOpcode(I->getOpcode()))
333 // Remove the branch.
334 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 if (!isCondBranchOpcode(I->getOpcode()))
343 // Remove the branch.
344 I->eraseFromParent();
349 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350 MachineBasicBlock *FBB,
351 const SmallVectorImpl<MachineOperand> &Cond,
353 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354 int BOpc = !AFI->isThumbFunction()
355 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356 int BccOpc = !AFI->isThumbFunction()
357 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
359 // Shouldn't be a fall through.
360 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361 assert((Cond.size() == 2 || Cond.size() == 0) &&
362 "ARM branch conditions have two components!");
365 if (Cond.empty()) // Unconditional branch?
366 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
368 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
373 // Two-way conditional branch.
374 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
380 bool ARMBaseInstrInfo::
381 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
387 bool ARMBaseInstrInfo::
388 PredicateInstruction(MachineInstr *MI,
389 const SmallVectorImpl<MachineOperand> &Pred) const {
390 unsigned Opc = MI->getOpcode();
391 if (isUncondBranchOpcode(Opc)) {
392 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
398 int PIdx = MI->findFirstPredOperandIdx();
400 MachineOperand &PMO = MI->getOperand(PIdx);
401 PMO.setImm(Pred[0].getImm());
402 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
408 bool ARMBaseInstrInfo::
409 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410 const SmallVectorImpl<MachineOperand> &Pred2) const {
411 if (Pred1.size() > 2 || Pred2.size() > 2)
414 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
425 return CC2 == ARMCC::HI;
427 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
429 return CC2 == ARMCC::GT;
431 return CC2 == ARMCC::LT;
435 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436 std::vector<MachineOperand> &Pred) const {
437 // FIXME: This confuses implicit_def with optional CPSR def.
438 const TargetInstrDesc &TID = MI->getDesc();
439 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
443 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444 const MachineOperand &MO = MI->getOperand(i);
445 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
454 /// isPredicable - Return true if the specified instruction can be predicated.
455 /// By default, this returns true for every instruction with a
456 /// PredicateOperand.
457 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458 const TargetInstrDesc &TID = MI->getDesc();
459 if (!TID.isPredicable())
462 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463 ARMFunctionInfo *AFI =
464 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465 return AFI->isThumb2Function();
470 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
472 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
474 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
476 assert(JTI < JT.size());
477 return JT[JTI].MBBs.size();
480 /// GetInstSize - Return the size of the specified MachineInstr.
482 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483 const MachineBasicBlock &MBB = *MI->getParent();
484 const MachineFunction *MF = MBB.getParent();
485 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
487 // Basic size info comes from the TSFlags field.
488 const TargetInstrDesc &TID = MI->getDesc();
489 uint64_t TSFlags = TID.TSFlags;
491 unsigned Opc = MI->getOpcode();
492 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
494 // If this machine instr is an inline asm, measure it.
495 if (MI->getOpcode() == ARM::INLINEASM)
496 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
501 llvm_unreachable("Unknown or unset size field for instr!");
502 case TargetOpcode::IMPLICIT_DEF:
503 case TargetOpcode::KILL:
504 case TargetOpcode::DBG_LABEL:
505 case TargetOpcode::EH_LABEL:
506 case TargetOpcode::DBG_VALUE:
511 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
512 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
513 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
514 case ARMII::SizeSpecial: {
516 case ARM::CONSTPOOL_ENTRY:
517 // If this machine instr is a constant pool entry, its size is recorded as
519 return MI->getOperand(2).getImm();
520 case ARM::Int_eh_sjlj_longjmp:
522 case ARM::tInt_eh_sjlj_longjmp:
524 case ARM::Int_eh_sjlj_setjmp:
525 case ARM::Int_eh_sjlj_setjmp_nofp:
527 case ARM::tInt_eh_sjlj_setjmp:
528 case ARM::t2Int_eh_sjlj_setjmp:
529 case ARM::t2Int_eh_sjlj_setjmp_nofp:
538 // These are jumptable branches, i.e. a branch followed by an inlined
539 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540 // entry is one byte; TBH two byte each.
541 unsigned EntrySize = (Opc == ARM::t2TBB)
542 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543 unsigned NumOps = TID.getNumOperands();
544 MachineOperand JTOP =
545 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546 unsigned JTI = JTOP.getIndex();
547 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
549 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550 assert(JTI < JT.size());
551 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552 // 4 aligned. The assembler / linker may add 2 byte padding just before
553 // the JT entries. The size does not include this padding; the
554 // constant islands pass does separate bookkeeping for it.
555 // FIXME: If we know the size of the function is less than (1 << 16) *2
556 // bytes, we can use 16-bit entries instead. Then there won't be an
558 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559 unsigned NumEntries = getNumJTEntries(JT, JTI);
560 if (Opc == ARM::t2TBB && (NumEntries & 1))
561 // Make sure the instruction that follows TBB is 2-byte aligned.
562 // FIXME: Constant island pass should insert an "ALIGN" instruction
565 return NumEntries * EntrySize + InstSize;
568 // Otherwise, pseudo-instruction sizes are zero.
573 return 0; // Not reached
576 /// Return true if the instruction is a register to register move and
577 /// leave the source and dest operands in the passed parameters.
580 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
581 unsigned &SrcReg, unsigned &DstReg,
582 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
583 switch (MI.getOpcode()) {
590 SrcReg = MI.getOperand(1).getReg();
591 DstReg = MI.getOperand(0).getReg();
592 SrcSubIdx = MI.getOperand(1).getSubReg();
593 DstSubIdx = MI.getOperand(0).getSubReg();
599 case ARM::tMOVgpr2tgpr:
600 case ARM::tMOVtgpr2gpr:
601 case ARM::tMOVgpr2gpr:
603 assert(MI.getDesc().getNumOperands() >= 2 &&
604 MI.getOperand(0).isReg() &&
605 MI.getOperand(1).isReg() &&
606 "Invalid ARM MOV instruction");
607 SrcReg = MI.getOperand(1).getReg();
608 DstReg = MI.getOperand(0).getReg();
609 SrcSubIdx = MI.getOperand(1).getSubReg();
610 DstSubIdx = MI.getOperand(0).getSubReg();
619 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
620 int &FrameIndex) const {
621 switch (MI->getOpcode()) {
624 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
625 if (MI->getOperand(1).isFI() &&
626 MI->getOperand(2).isReg() &&
627 MI->getOperand(3).isImm() &&
628 MI->getOperand(2).getReg() == 0 &&
629 MI->getOperand(3).getImm() == 0) {
630 FrameIndex = MI->getOperand(1).getIndex();
631 return MI->getOperand(0).getReg();
636 if (MI->getOperand(1).isFI() &&
637 MI->getOperand(2).isImm() &&
638 MI->getOperand(2).getImm() == 0) {
639 FrameIndex = MI->getOperand(1).getIndex();
640 return MI->getOperand(0).getReg();
645 if (MI->getOperand(1).isFI() &&
646 MI->getOperand(2).isImm() &&
647 MI->getOperand(2).getImm() == 0) {
648 FrameIndex = MI->getOperand(1).getIndex();
649 return MI->getOperand(0).getReg();
658 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
659 int &FrameIndex) const {
660 switch (MI->getOpcode()) {
663 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
664 if (MI->getOperand(1).isFI() &&
665 MI->getOperand(2).isReg() &&
666 MI->getOperand(3).isImm() &&
667 MI->getOperand(2).getReg() == 0 &&
668 MI->getOperand(3).getImm() == 0) {
669 FrameIndex = MI->getOperand(1).getIndex();
670 return MI->getOperand(0).getReg();
675 if (MI->getOperand(1).isFI() &&
676 MI->getOperand(2).isImm() &&
677 MI->getOperand(2).getImm() == 0) {
678 FrameIndex = MI->getOperand(1).getIndex();
679 return MI->getOperand(0).getReg();
684 if (MI->getOperand(1).isFI() &&
685 MI->getOperand(2).isImm() &&
686 MI->getOperand(2).getImm() == 0) {
687 FrameIndex = MI->getOperand(1).getIndex();
688 return MI->getOperand(0).getReg();
697 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
698 MachineBasicBlock::iterator I,
699 unsigned DestReg, unsigned SrcReg,
700 const TargetRegisterClass *DestRC,
701 const TargetRegisterClass *SrcRC,
703 // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid
704 // using certain registers. Just treat them as GPR here.
705 if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass)
706 DestRC = ARM::GPRRegisterClass;
707 if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
708 SrcRC = ARM::GPRRegisterClass;
710 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
711 if (DestRC == ARM::DPR_8RegisterClass)
712 DestRC = ARM::DPR_VFP2RegisterClass;
713 if (SrcRC == ARM::DPR_8RegisterClass)
714 SrcRC = ARM::DPR_VFP2RegisterClass;
716 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
717 if (DestRC == ARM::QPR_VFP2RegisterClass ||
718 DestRC == ARM::QPR_8RegisterClass)
719 DestRC = ARM::QPRRegisterClass;
720 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
721 SrcRC == ARM::QPR_8RegisterClass)
722 SrcRC = ARM::QPRRegisterClass;
724 // Allow QQPR / QQPR_VFP2 cross-class copies.
725 if (DestRC == ARM::QQPR_VFP2RegisterClass)
726 DestRC = ARM::QQPRRegisterClass;
727 if (SrcRC == ARM::QQPR_VFP2RegisterClass)
728 SrcRC = ARM::QQPRRegisterClass;
730 // Disallow copies of unequal sizes.
731 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
734 if (DestRC == ARM::GPRRegisterClass) {
735 if (SrcRC == ARM::SPRRegisterClass)
736 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
739 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
740 DestReg).addReg(SrcReg)));
744 if (DestRC == ARM::SPRRegisterClass)
745 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
746 else if (DestRC == ARM::DPRRegisterClass)
748 else if (DestRC == ARM::DPR_VFP2RegisterClass ||
749 SrcRC == ARM::DPR_VFP2RegisterClass)
750 // Always use neon reg-reg move if source or dest is NEON-only regclass.
751 Opc = ARM::VMOVDneon;
752 else if (DestRC == ARM::QPRRegisterClass)
754 else if (DestRC == ARM::QQPRRegisterClass)
756 else if (DestRC == ARM::QQQQPRRegisterClass)
761 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
763 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
771 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
772 unsigned Reg, unsigned SubIdx, unsigned State,
773 const TargetRegisterInfo *TRI) {
775 return MIB.addReg(Reg, State);
777 if (TargetRegisterInfo::isPhysicalRegister(Reg))
778 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
779 return MIB.addReg(Reg, State, SubIdx);
782 void ARMBaseInstrInfo::
783 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
784 unsigned SrcReg, bool isKill, int FI,
785 const TargetRegisterClass *RC,
786 const TargetRegisterInfo *TRI) const {
788 if (I != MBB.end()) DL = I->getDebugLoc();
789 MachineFunction &MF = *MBB.getParent();
790 MachineFrameInfo &MFI = *MF.getFrameInfo();
791 unsigned Align = MFI.getObjectAlignment(FI);
793 MachineMemOperand *MMO =
794 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
795 MachineMemOperand::MOStore, 0,
796 MFI.getObjectSize(FI),
799 // tGPR is used sometimes in ARM instructions that need to avoid using
800 // certain registers. Just treat it as GPR here.
801 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
802 RC = ARM::GPRRegisterClass;
804 switch (RC->getID()) {
805 case ARM::GPRRegClassID:
806 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
807 .addReg(SrcReg, getKillRegState(isKill))
808 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
810 case ARM::SPRRegClassID:
811 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
812 .addReg(SrcReg, getKillRegState(isKill))
813 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
815 case ARM::DPRRegClassID:
816 case ARM::DPR_VFP2RegClassID:
817 case ARM::DPR_8RegClassID:
818 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
819 .addReg(SrcReg, getKillRegState(isKill))
820 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
822 case ARM::QPRRegClassID:
823 case ARM::QPR_VFP2RegClassID:
824 case ARM::QPR_8RegClassID:
825 // FIXME: Neon instructions should support predicates
826 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
827 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
828 .addFrameIndex(FI).addImm(128)
829 .addReg(SrcReg, getKillRegState(isKill))
830 .addMemOperand(MMO));
832 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
833 .addReg(SrcReg, getKillRegState(isKill))
835 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
836 .addMemOperand(MMO));
839 case ARM::QQPRRegClassID:
840 case ARM::QQPR_VFP2RegClassID:
841 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
842 // FIXME: It's possible to only store part of the QQ register if the
843 // spilled def has a sub-register index.
844 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
845 .addFrameIndex(FI).addImm(128);
846 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
850 AddDefaultPred(MIB.addMemOperand(MMO));
852 MachineInstrBuilder MIB =
853 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
855 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
857 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
858 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
859 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
860 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
863 case ARM::QQQQPRRegClassID: {
864 MachineInstrBuilder MIB =
865 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
867 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
869 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
870 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
871 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
872 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
873 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
874 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
875 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
876 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
880 llvm_unreachable("Unknown regclass!");
884 void ARMBaseInstrInfo::
885 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
886 unsigned DestReg, int FI,
887 const TargetRegisterClass *RC,
888 const TargetRegisterInfo *TRI) const {
890 if (I != MBB.end()) DL = I->getDebugLoc();
891 MachineFunction &MF = *MBB.getParent();
892 MachineFrameInfo &MFI = *MF.getFrameInfo();
893 unsigned Align = MFI.getObjectAlignment(FI);
894 MachineMemOperand *MMO =
895 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
896 MachineMemOperand::MOLoad, 0,
897 MFI.getObjectSize(FI),
900 // tGPR is used sometimes in ARM instructions that need to avoid using
901 // certain registers. Just treat it as GPR here.
902 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
903 RC = ARM::GPRRegisterClass;
905 switch (RC->getID()) {
906 case ARM::GPRRegClassID:
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
908 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
910 case ARM::SPRRegClassID:
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
912 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
914 case ARM::DPRRegClassID:
915 case ARM::DPR_VFP2RegClassID:
916 case ARM::DPR_8RegClassID:
917 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
918 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
920 case ARM::QPRRegClassID:
921 case ARM::QPR_VFP2RegClassID:
922 case ARM::QPR_8RegClassID:
923 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
925 .addFrameIndex(FI).addImm(128)
926 .addMemOperand(MMO));
928 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
930 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
931 .addMemOperand(MMO));
934 case ARM::QQPRRegClassID:
935 case ARM::QQPR_VFP2RegClassID:
936 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
937 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
938 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
939 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
940 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
941 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
942 AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
944 MachineInstrBuilder MIB =
945 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
947 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
949 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
950 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
951 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
952 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
955 case ARM::QQQQPRRegClassID: {
956 MachineInstrBuilder MIB =
957 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
959 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
961 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
962 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
963 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
964 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
965 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
966 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
967 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
968 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
972 llvm_unreachable("Unknown regclass!");
977 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
978 int FrameIx, uint64_t Offset,
981 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
982 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
986 MachineInstr *ARMBaseInstrInfo::
987 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
988 const SmallVectorImpl<unsigned> &Ops, int FI) const {
989 if (Ops.size() != 1) return NULL;
991 unsigned OpNum = Ops[0];
992 unsigned Opc = MI->getOpcode();
993 MachineInstr *NewMI = NULL;
994 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
995 // If it is updating CPSR, then it cannot be folded.
996 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
998 unsigned Pred = MI->getOperand(2).getImm();
999 unsigned PredReg = MI->getOperand(3).getReg();
1000 if (OpNum == 0) { // move -> store
1001 unsigned SrcReg = MI->getOperand(1).getReg();
1002 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1003 bool isKill = MI->getOperand(1).isKill();
1004 bool isUndef = MI->getOperand(1).isUndef();
1005 if (Opc == ARM::MOVr)
1006 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
1008 getKillRegState(isKill) | getUndefRegState(isUndef),
1010 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1012 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1014 getKillRegState(isKill) | getUndefRegState(isUndef),
1016 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1017 } else { // move -> load
1018 unsigned DstReg = MI->getOperand(0).getReg();
1019 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1020 bool isDead = MI->getOperand(0).isDead();
1021 bool isUndef = MI->getOperand(0).isUndef();
1022 if (Opc == ARM::MOVr)
1023 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1026 getDeadRegState(isDead) |
1027 getUndefRegState(isUndef), DstSubReg)
1028 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1030 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1033 getDeadRegState(isDead) |
1034 getUndefRegState(isUndef), DstSubReg)
1035 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1037 } else if (Opc == ARM::tMOVgpr2gpr ||
1038 Opc == ARM::tMOVtgpr2gpr ||
1039 Opc == ARM::tMOVgpr2tgpr) {
1040 if (OpNum == 0) { // move -> store
1041 unsigned SrcReg = MI->getOperand(1).getReg();
1042 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1043 bool isKill = MI->getOperand(1).isKill();
1044 bool isUndef = MI->getOperand(1).isUndef();
1045 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1047 getKillRegState(isKill) | getUndefRegState(isUndef),
1049 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1050 } else { // move -> load
1051 unsigned DstReg = MI->getOperand(0).getReg();
1052 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1053 bool isDead = MI->getOperand(0).isDead();
1054 bool isUndef = MI->getOperand(0).isUndef();
1055 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1058 getDeadRegState(isDead) |
1059 getUndefRegState(isUndef),
1061 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1063 } else if (Opc == ARM::VMOVS) {
1064 unsigned Pred = MI->getOperand(2).getImm();
1065 unsigned PredReg = MI->getOperand(3).getReg();
1066 if (OpNum == 0) { // move -> store
1067 unsigned SrcReg = MI->getOperand(1).getReg();
1068 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1069 bool isKill = MI->getOperand(1).isKill();
1070 bool isUndef = MI->getOperand(1).isUndef();
1071 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1072 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1075 .addImm(0).addImm(Pred).addReg(PredReg);
1076 } else { // move -> load
1077 unsigned DstReg = MI->getOperand(0).getReg();
1078 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1079 bool isDead = MI->getOperand(0).isDead();
1080 bool isUndef = MI->getOperand(0).isUndef();
1081 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1084 getDeadRegState(isDead) |
1085 getUndefRegState(isUndef),
1087 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1089 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1090 unsigned Pred = MI->getOperand(2).getImm();
1091 unsigned PredReg = MI->getOperand(3).getReg();
1092 if (OpNum == 0) { // move -> store
1093 unsigned SrcReg = MI->getOperand(1).getReg();
1094 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1095 bool isKill = MI->getOperand(1).isKill();
1096 bool isUndef = MI->getOperand(1).isUndef();
1097 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1099 getKillRegState(isKill) | getUndefRegState(isUndef),
1101 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1102 } else { // move -> load
1103 unsigned DstReg = MI->getOperand(0).getReg();
1104 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1105 bool isDead = MI->getOperand(0).isDead();
1106 bool isUndef = MI->getOperand(0).isUndef();
1107 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1110 getDeadRegState(isDead) |
1111 getUndefRegState(isUndef),
1113 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1115 } else if (Opc == ARM::VMOVQ) {
1116 MachineFrameInfo &MFI = *MF.getFrameInfo();
1117 unsigned Pred = MI->getOperand(2).getImm();
1118 unsigned PredReg = MI->getOperand(3).getReg();
1119 if (OpNum == 0) { // move -> store
1120 unsigned SrcReg = MI->getOperand(1).getReg();
1121 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1122 bool isKill = MI->getOperand(1).isKill();
1123 bool isUndef = MI->getOperand(1).isUndef();
1124 if (MFI.getObjectAlignment(FI) >= 16 &&
1125 getRegisterInfo().canRealignStack(MF)) {
1126 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1127 .addFrameIndex(FI).addImm(128)
1129 getKillRegState(isKill) | getUndefRegState(isUndef),
1131 .addImm(Pred).addReg(PredReg);
1133 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1135 getKillRegState(isKill) | getUndefRegState(isUndef),
1137 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1138 .addImm(Pred).addReg(PredReg);
1140 } else { // move -> load
1141 unsigned DstReg = MI->getOperand(0).getReg();
1142 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1143 bool isDead = MI->getOperand(0).isDead();
1144 bool isUndef = MI->getOperand(0).isUndef();
1145 if (MFI.getObjectAlignment(FI) >= 16 &&
1146 getRegisterInfo().canRealignStack(MF)) {
1147 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1150 getDeadRegState(isDead) |
1151 getUndefRegState(isUndef),
1153 .addFrameIndex(FI).addImm(128).addImm(Pred).addReg(PredReg);
1155 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1158 getDeadRegState(isDead) |
1159 getUndefRegState(isUndef),
1161 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1162 .addImm(Pred).addReg(PredReg);
1171 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1173 const SmallVectorImpl<unsigned> &Ops,
1174 MachineInstr* LoadMI) const {
1180 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1181 const SmallVectorImpl<unsigned> &Ops) const {
1182 if (Ops.size() != 1) return false;
1184 unsigned Opc = MI->getOpcode();
1185 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1186 // If it is updating CPSR, then it cannot be folded.
1187 return MI->getOperand(4).getReg() != ARM::CPSR ||
1188 MI->getOperand(4).isDead();
1189 } else if (Opc == ARM::tMOVgpr2gpr ||
1190 Opc == ARM::tMOVtgpr2gpr ||
1191 Opc == ARM::tMOVgpr2tgpr) {
1193 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1194 Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1198 // FIXME: VMOVQQ and VMOVQQQQ?
1203 /// Create a copy of a const pool value. Update CPI to the new index and return
1205 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1206 MachineConstantPool *MCP = MF.getConstantPool();
1207 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1209 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1210 assert(MCPE.isMachineConstantPoolEntry() &&
1211 "Expecting a machine constantpool entry!");
1212 ARMConstantPoolValue *ACPV =
1213 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1215 unsigned PCLabelId = AFI->createConstPoolEntryUId();
1216 ARMConstantPoolValue *NewCPV = 0;
1217 if (ACPV->isGlobalValue())
1218 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1220 else if (ACPV->isExtSymbol())
1221 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1222 ACPV->getSymbol(), PCLabelId, 4);
1223 else if (ACPV->isBlockAddress())
1224 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1225 ARMCP::CPBlockAddress, 4);
1227 llvm_unreachable("Unexpected ARM constantpool value type!!");
1228 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1232 void ARMBaseInstrInfo::
1233 reMaterialize(MachineBasicBlock &MBB,
1234 MachineBasicBlock::iterator I,
1235 unsigned DestReg, unsigned SubIdx,
1236 const MachineInstr *Orig,
1237 const TargetRegisterInfo &TRI) const {
1238 unsigned Opcode = Orig->getOpcode();
1241 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1242 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1246 case ARM::tLDRpci_pic:
1247 case ARM::t2LDRpci_pic: {
1248 MachineFunction &MF = *MBB.getParent();
1249 unsigned CPI = Orig->getOperand(1).getIndex();
1250 unsigned PCLabelId = duplicateCPV(MF, CPI);
1251 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1253 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1254 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1261 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1262 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1263 switch(Orig->getOpcode()) {
1264 case ARM::tLDRpci_pic:
1265 case ARM::t2LDRpci_pic: {
1266 unsigned CPI = Orig->getOperand(1).getIndex();
1267 unsigned PCLabelId = duplicateCPV(MF, CPI);
1268 Orig->getOperand(1).setIndex(CPI);
1269 Orig->getOperand(2).setImm(PCLabelId);
1276 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1277 const MachineInstr *MI1) const {
1278 int Opcode = MI0->getOpcode();
1279 if (Opcode == ARM::t2LDRpci ||
1280 Opcode == ARM::t2LDRpci_pic ||
1281 Opcode == ARM::tLDRpci ||
1282 Opcode == ARM::tLDRpci_pic) {
1283 if (MI1->getOpcode() != Opcode)
1285 if (MI0->getNumOperands() != MI1->getNumOperands())
1288 const MachineOperand &MO0 = MI0->getOperand(1);
1289 const MachineOperand &MO1 = MI1->getOperand(1);
1290 if (MO0.getOffset() != MO1.getOffset())
1293 const MachineFunction *MF = MI0->getParent()->getParent();
1294 const MachineConstantPool *MCP = MF->getConstantPool();
1295 int CPI0 = MO0.getIndex();
1296 int CPI1 = MO1.getIndex();
1297 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1298 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1299 ARMConstantPoolValue *ACPV0 =
1300 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1301 ARMConstantPoolValue *ACPV1 =
1302 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1303 return ACPV0->hasSameValue(ACPV1);
1306 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1309 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1310 /// determine if two loads are loading from the same base address. It should
1311 /// only return true if the base pointers are the same and the only differences
1312 /// between the two addresses is the offset. It also returns the offsets by
1314 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1316 int64_t &Offset2) const {
1317 // Don't worry about Thumb: just ARM and Thumb2.
1318 if (Subtarget.isThumb1Only()) return false;
1320 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1323 switch (Load1->getMachineOpcode()) {
1336 case ARM::t2LDRSHi8:
1338 case ARM::t2LDRSHi12:
1342 switch (Load2->getMachineOpcode()) {
1355 case ARM::t2LDRSHi8:
1357 case ARM::t2LDRSHi12:
1361 // Check if base addresses and chain operands match.
1362 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1363 Load1->getOperand(4) != Load2->getOperand(4))
1366 // Index should be Reg0.
1367 if (Load1->getOperand(3) != Load2->getOperand(3))
1370 // Determine the offsets.
1371 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1372 isa<ConstantSDNode>(Load2->getOperand(1))) {
1373 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1374 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1381 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1382 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1383 /// be scheduled togther. On some targets if two loads are loading from
1384 /// addresses in the same cache line, it's better if they are scheduled
1385 /// together. This function takes two integers that represent the load offsets
1386 /// from the common base address. It returns true if it decides it's desirable
1387 /// to schedule the two loads together. "NumLoads" is the number of loads that
1388 /// have already been scheduled after Load1.
1389 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1390 int64_t Offset1, int64_t Offset2,
1391 unsigned NumLoads) const {
1392 // Don't worry about Thumb: just ARM and Thumb2.
1393 if (Subtarget.isThumb1Only()) return false;
1395 assert(Offset2 > Offset1);
1397 if ((Offset2 - Offset1) / 8 > 64)
1400 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1401 return false; // FIXME: overly conservative?
1403 // Four loads in a row should be sufficient.
1410 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1411 const MachineBasicBlock *MBB,
1412 const MachineFunction &MF) const {
1413 // Debug info is never a scheduling boundary. It's necessary to be explicit
1414 // due to the special treatment of IT instructions below, otherwise a
1415 // dbg_value followed by an IT will result in the IT instruction being
1416 // considered a scheduling hazard, which is wrong. It should be the actual
1417 // instruction preceding the dbg_value instruction(s), just like it is
1418 // when debug info is not present.
1419 if (MI->isDebugValue())
1422 // Terminators and labels can't be scheduled around.
1423 if (MI->getDesc().isTerminator() || MI->isLabel())
1426 // Treat the start of the IT block as a scheduling boundary, but schedule
1427 // t2IT along with all instructions following it.
1428 // FIXME: This is a big hammer. But the alternative is to add all potential
1429 // true and anti dependencies to IT block instructions as implicit operands
1430 // to the t2IT instruction. The added compile time and complexity does not
1432 MachineBasicBlock::const_iterator I = MI;
1433 // Make sure to skip any dbg_value instructions
1434 while (++I != MBB->end() && I->isDebugValue())
1436 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1439 // Don't attempt to schedule around any instruction that defines
1440 // a stack-oriented pointer, as it's unlikely to be profitable. This
1441 // saves compile time, because it doesn't require every single
1442 // stack slot reference to depend on the instruction that does the
1444 if (MI->definesRegister(ARM::SP))
1450 bool ARMBaseInstrInfo::
1451 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
1454 if (Subtarget.getCPUString() == "generic")
1455 // Generic (and overly aggressive) if-conversion limits for testing.
1456 return NumInstrs <= 10;
1457 else if (Subtarget.hasV7Ops())
1458 return NumInstrs <= 3;
1459 return NumInstrs <= 2;
1462 bool ARMBaseInstrInfo::
1463 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1464 MachineBasicBlock &FMBB, unsigned NumF) const {
1465 return NumT && NumF && NumT <= 2 && NumF <= 2;
1468 /// getInstrPredicate - If instruction is predicated, returns its predicate
1469 /// condition, otherwise returns AL. It also returns the condition code
1470 /// register by reference.
1472 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1473 int PIdx = MI->findFirstPredOperandIdx();
1479 PredReg = MI->getOperand(PIdx+1).getReg();
1480 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1484 int llvm::getMatchingCondBranchOpcode(int Opc) {
1487 else if (Opc == ARM::tB)
1489 else if (Opc == ARM::t2B)
1492 llvm_unreachable("Unknown unconditional branch opcode!");
1497 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1498 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1499 unsigned DestReg, unsigned BaseReg, int NumBytes,
1500 ARMCC::CondCodes Pred, unsigned PredReg,
1501 const ARMBaseInstrInfo &TII) {
1502 bool isSub = NumBytes < 0;
1503 if (isSub) NumBytes = -NumBytes;
1506 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1507 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1508 assert(ThisVal && "Didn't extract field correctly");
1510 // We will handle these bits from offset, clear them.
1511 NumBytes &= ~ThisVal;
1513 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1515 // Build the new ADD / SUB.
1516 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1517 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1518 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1519 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1524 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1525 unsigned FrameReg, int &Offset,
1526 const ARMBaseInstrInfo &TII) {
1527 unsigned Opcode = MI.getOpcode();
1528 const TargetInstrDesc &Desc = MI.getDesc();
1529 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1532 // Memory operands in inline assembly always use AddrMode2.
1533 if (Opcode == ARM::INLINEASM)
1534 AddrMode = ARMII::AddrMode2;
1536 if (Opcode == ARM::ADDri) {
1537 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1539 // Turn it into a move.
1540 MI.setDesc(TII.get(ARM::MOVr));
1541 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1542 MI.RemoveOperand(FrameRegIdx+1);
1545 } else if (Offset < 0) {
1548 MI.setDesc(TII.get(ARM::SUBri));
1551 // Common case: small offset, fits into instruction.
1552 if (ARM_AM::getSOImmVal(Offset) != -1) {
1553 // Replace the FrameIndex with sp / fp
1554 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1555 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1560 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1562 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1563 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1565 // We will handle these bits from offset, clear them.
1566 Offset &= ~ThisImmVal;
1568 // Get the properly encoded SOImmVal field.
1569 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1570 "Bit extraction didn't work?");
1571 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1573 unsigned ImmIdx = 0;
1575 unsigned NumBits = 0;
1578 case ARMII::AddrMode2: {
1579 ImmIdx = FrameRegIdx+2;
1580 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1581 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1586 case ARMII::AddrMode3: {
1587 ImmIdx = FrameRegIdx+2;
1588 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1589 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1594 case ARMII::AddrMode4:
1595 case ARMII::AddrMode6:
1596 // Can't fold any offset even if it's zero.
1598 case ARMII::AddrMode5: {
1599 ImmIdx = FrameRegIdx+1;
1600 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1601 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1608 llvm_unreachable("Unsupported addressing mode!");
1612 Offset += InstrOffs * Scale;
1613 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1619 // Attempt to fold address comp. if opcode has offset bits
1621 // Common case: small offset, fits into instruction.
1622 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1623 int ImmedOffset = Offset / Scale;
1624 unsigned Mask = (1 << NumBits) - 1;
1625 if ((unsigned)Offset <= Mask * Scale) {
1626 // Replace the FrameIndex with sp
1627 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1629 ImmedOffset |= 1 << NumBits;
1630 ImmOp.ChangeToImmediate(ImmedOffset);
1635 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1636 ImmedOffset = ImmedOffset & Mask;
1638 ImmedOffset |= 1 << NumBits;
1639 ImmOp.ChangeToImmediate(ImmedOffset);
1640 Offset &= ~(Mask*Scale);
1644 Offset = (isSub) ? -Offset : Offset;