1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
30 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
31 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 ARMBaseInstrInfo::ARMBaseInstrInfo()
34 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
38 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
39 MachineBasicBlock::iterator &MBBI,
40 LiveVariables *LV) const {
41 // FIXME: Thumb2 support.
46 MachineInstr *MI = MBBI;
47 MachineFunction &MF = *MI->getParent()->getParent();
48 unsigned TSFlags = MI->getDesc().TSFlags;
50 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
52 case ARMII::IndexModePre:
55 case ARMII::IndexModePost:
59 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
61 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
65 MachineInstr *UpdateMI = NULL;
66 MachineInstr *MemMI = NULL;
67 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
68 const TargetInstrDesc &TID = MI->getDesc();
69 unsigned NumOps = TID.getNumOperands();
70 bool isLoad = !TID.mayStore();
71 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
72 const MachineOperand &Base = MI->getOperand(2);
73 const MachineOperand &Offset = MI->getOperand(NumOps-3);
74 unsigned WBReg = WB.getReg();
75 unsigned BaseReg = Base.getReg();
76 unsigned OffReg = Offset.getReg();
77 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
78 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
81 assert(false && "Unknown indexed op!");
83 case ARMII::AddrMode2: {
84 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
85 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
87 if (ARM_AM::getSOImmVal(Amt) == -1)
88 // Can't encode it in a so_imm operand. This transformation will
89 // add more than 1 instruction. Abandon!
91 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
92 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
93 .addReg(BaseReg).addImm(Amt)
94 .addImm(Pred).addReg(0).addReg(0);
95 } else if (Amt != 0) {
96 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
97 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
98 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
99 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
100 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
101 .addImm(Pred).addReg(0).addReg(0);
103 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
104 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
105 .addReg(BaseReg).addReg(OffReg)
106 .addImm(Pred).addReg(0).addReg(0);
109 case ARMII::AddrMode3 : {
110 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
111 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
113 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
116 .addReg(BaseReg).addImm(Amt)
117 .addImm(Pred).addReg(0).addReg(0);
119 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
120 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
121 .addReg(BaseReg).addReg(OffReg)
122 .addImm(Pred).addReg(0).addReg(0);
127 std::vector<MachineInstr*> NewMIs;
130 MemMI = BuildMI(MF, MI->getDebugLoc(),
131 get(MemOpc), MI->getOperand(0).getReg())
132 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
134 MemMI = BuildMI(MF, MI->getDebugLoc(),
135 get(MemOpc)).addReg(MI->getOperand(1).getReg())
136 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
137 NewMIs.push_back(MemMI);
138 NewMIs.push_back(UpdateMI);
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
149 UpdateMI->getOperand(0).setIsDead();
150 NewMIs.push_back(UpdateMI);
151 NewMIs.push_back(MemMI);
154 // Transfer LiveVariables states, kill / dead info.
156 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
157 MachineOperand &MO = MI->getOperand(i);
158 if (MO.isReg() && MO.getReg() &&
159 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
160 unsigned Reg = MO.getReg();
162 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
164 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
166 LV->addVirtualRegisterDead(Reg, NewMI);
168 if (MO.isUse() && MO.isKill()) {
169 for (unsigned j = 0; j < 2; ++j) {
170 // Look at the two new MI's in reverse order.
171 MachineInstr *NewMI = NewMIs[j];
172 if (!NewMI->readsRegister(Reg))
174 LV->addVirtualRegisterKilled(Reg, NewMI);
175 if (VI.removeKill(MI))
176 VI.Kills.push_back(NewMI);
184 MFI->insert(MBBI, NewMIs[1]);
185 MFI->insert(MBBI, NewMIs[0]);
191 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
192 MachineBasicBlock *&FBB,
193 SmallVectorImpl<MachineOperand> &Cond,
194 bool AllowModify) const {
195 // If the block has no terminators, it just falls into the block after it.
196 MachineBasicBlock::iterator I = MBB.end();
197 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
200 // Get the last instruction in the block.
201 MachineInstr *LastInst = I;
203 // If there is only one terminator instruction, process it.
204 unsigned LastOpc = LastInst->getOpcode();
205 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
206 if (isUncondBranchOpcode(LastOpc)) {
207 TBB = LastInst->getOperand(0).getMBB();
210 if (isCondBranchOpcode(LastOpc)) {
211 // Block ends with fall-through condbranch.
212 TBB = LastInst->getOperand(0).getMBB();
213 Cond.push_back(LastInst->getOperand(1));
214 Cond.push_back(LastInst->getOperand(2));
217 return true; // Can't handle indirect branch.
220 // Get the instruction before it if it is a terminator.
221 MachineInstr *SecondLastInst = I;
223 // If there are three terminators, we don't know what sort of block this is.
224 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
227 // If the block ends with a B and a Bcc, handle it.
228 unsigned SecondLastOpc = SecondLastInst->getOpcode();
229 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
230 TBB = SecondLastInst->getOperand(0).getMBB();
231 Cond.push_back(SecondLastInst->getOperand(1));
232 Cond.push_back(SecondLastInst->getOperand(2));
233 FBB = LastInst->getOperand(0).getMBB();
237 // If the block ends with two unconditional branches, handle it. The second
238 // one is not executed, so remove it.
239 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240 TBB = SecondLastInst->getOperand(0).getMBB();
243 I->eraseFromParent();
247 // ...likewise if it ends with a branch table followed by an unconditional
248 // branch. The branch folder can create these, and we must get rid of them for
249 // correctness of Thumb constant islands.
250 if (isJumpTableBranchOpcode(SecondLastOpc) &&
251 isUncondBranchOpcode(LastOpc)) {
254 I->eraseFromParent();
258 // Otherwise, can't handle this.
263 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
264 MachineBasicBlock::iterator I = MBB.end();
265 if (I == MBB.begin()) return 0;
267 if (!isUncondBranchOpcode(I->getOpcode()) &&
268 !isCondBranchOpcode(I->getOpcode()))
271 // Remove the branch.
272 I->eraseFromParent();
276 if (I == MBB.begin()) return 1;
278 if (!isCondBranchOpcode(I->getOpcode()))
281 // Remove the branch.
282 I->eraseFromParent();
287 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
288 MachineBasicBlock *FBB,
289 const SmallVectorImpl<MachineOperand> &Cond) const {
290 // FIXME this should probably have a DebugLoc argument
291 DebugLoc dl = DebugLoc::getUnknownLoc();
293 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
294 int BOpc = !AFI->isThumbFunction()
295 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
296 int BccOpc = !AFI->isThumbFunction()
297 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
299 // Shouldn't be a fall through.
300 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
301 assert((Cond.size() == 2 || Cond.size() == 0) &&
302 "ARM branch conditions have two components!");
305 if (Cond.empty()) // Unconditional branch?
306 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
308 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
309 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
313 // Two-way conditional branch.
314 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
315 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
316 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
320 bool ARMBaseInstrInfo::
321 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
322 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
323 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
327 bool ARMBaseInstrInfo::
328 PredicateInstruction(MachineInstr *MI,
329 const SmallVectorImpl<MachineOperand> &Pred) const {
330 unsigned Opc = MI->getOpcode();
331 if (isUncondBranchOpcode(Opc)) {
332 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
333 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
334 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
338 int PIdx = MI->findFirstPredOperandIdx();
340 MachineOperand &PMO = MI->getOperand(PIdx);
341 PMO.setImm(Pred[0].getImm());
342 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
348 bool ARMBaseInstrInfo::
349 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
350 const SmallVectorImpl<MachineOperand> &Pred2) const {
351 if (Pred1.size() > 2 || Pred2.size() > 2)
354 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
355 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
365 return CC2 == ARMCC::HI;
367 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
369 return CC2 == ARMCC::GT;
371 return CC2 == ARMCC::LT;
375 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
376 std::vector<MachineOperand> &Pred) const {
377 // FIXME: This confuses implicit_def with optional CPSR def.
378 const TargetInstrDesc &TID = MI->getDesc();
379 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
383 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
384 const MachineOperand &MO = MI->getOperand(i);
385 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
395 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
396 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
397 unsigned JTI) DISABLE_INLINE;
398 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
400 return JT[JTI].MBBs.size();
403 /// GetInstSize - Return the size of the specified MachineInstr.
405 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
406 const MachineBasicBlock &MBB = *MI->getParent();
407 const MachineFunction *MF = MBB.getParent();
408 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
410 // Basic size info comes from the TSFlags field.
411 const TargetInstrDesc &TID = MI->getDesc();
412 unsigned TSFlags = TID.TSFlags;
414 unsigned Opc = MI->getOpcode();
415 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
417 // If this machine instr is an inline asm, measure it.
418 if (MI->getOpcode() == ARM::INLINEASM)
419 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
424 llvm_unreachable("Unknown or unset size field for instr!");
425 case TargetInstrInfo::IMPLICIT_DEF:
426 case TargetInstrInfo::KILL:
427 case TargetInstrInfo::DBG_LABEL:
428 case TargetInstrInfo::EH_LABEL:
433 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
434 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
435 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
436 case ARMII::SizeSpecial: {
438 case ARM::CONSTPOOL_ENTRY:
439 // If this machine instr is a constant pool entry, its size is recorded as
441 return MI->getOperand(2).getImm();
442 case ARM::Int_eh_sjlj_setjmp:
444 case ARM::t2Int_eh_sjlj_setjmp:
453 // These are jumptable branches, i.e. a branch followed by an inlined
454 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
455 // entry is one byte; TBH two byte each.
456 unsigned EntrySize = (Opc == ARM::t2TBB)
457 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
458 unsigned NumOps = TID.getNumOperands();
459 MachineOperand JTOP =
460 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
461 unsigned JTI = JTOP.getIndex();
462 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
463 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
464 assert(JTI < JT.size());
465 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
466 // 4 aligned. The assembler / linker may add 2 byte padding just before
467 // the JT entries. The size does not include this padding; the
468 // constant islands pass does separate bookkeeping for it.
469 // FIXME: If we know the size of the function is less than (1 << 16) *2
470 // bytes, we can use 16-bit entries instead. Then there won't be an
472 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
473 unsigned NumEntries = getNumJTEntries(JT, JTI);
474 if (Opc == ARM::t2TBB && (NumEntries & 1))
475 // Make sure the instruction that follows TBB is 2-byte aligned.
476 // FIXME: Constant island pass should insert an "ALIGN" instruction
479 return NumEntries * EntrySize + InstSize;
482 // Otherwise, pseudo-instruction sizes are zero.
487 return 0; // Not reached
490 /// Return true if the instruction is a register to register move and
491 /// leave the source and dest operands in the passed parameters.
494 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
495 unsigned &SrcReg, unsigned &DstReg,
496 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
497 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
499 switch (MI.getOpcode()) {
505 SrcReg = MI.getOperand(1).getReg();
506 DstReg = MI.getOperand(0).getReg();
511 case ARM::tMOVgpr2tgpr:
512 case ARM::tMOVtgpr2gpr:
513 case ARM::tMOVgpr2gpr:
515 assert(MI.getDesc().getNumOperands() >= 2 &&
516 MI.getOperand(0).isReg() &&
517 MI.getOperand(1).isReg() &&
518 "Invalid ARM MOV instruction");
519 SrcReg = MI.getOperand(1).getReg();
520 DstReg = MI.getOperand(0).getReg();
529 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
530 int &FrameIndex) const {
531 switch (MI->getOpcode()) {
534 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
535 if (MI->getOperand(1).isFI() &&
536 MI->getOperand(2).isReg() &&
537 MI->getOperand(3).isImm() &&
538 MI->getOperand(2).getReg() == 0 &&
539 MI->getOperand(3).getImm() == 0) {
540 FrameIndex = MI->getOperand(1).getIndex();
541 return MI->getOperand(0).getReg();
546 if (MI->getOperand(1).isFI() &&
547 MI->getOperand(2).isImm() &&
548 MI->getOperand(2).getImm() == 0) {
549 FrameIndex = MI->getOperand(1).getIndex();
550 return MI->getOperand(0).getReg();
555 if (MI->getOperand(1).isFI() &&
556 MI->getOperand(2).isImm() &&
557 MI->getOperand(2).getImm() == 0) {
558 FrameIndex = MI->getOperand(1).getIndex();
559 return MI->getOperand(0).getReg();
568 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
569 int &FrameIndex) const {
570 switch (MI->getOpcode()) {
573 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
574 if (MI->getOperand(1).isFI() &&
575 MI->getOperand(2).isReg() &&
576 MI->getOperand(3).isImm() &&
577 MI->getOperand(2).getReg() == 0 &&
578 MI->getOperand(3).getImm() == 0) {
579 FrameIndex = MI->getOperand(1).getIndex();
580 return MI->getOperand(0).getReg();
585 if (MI->getOperand(1).isFI() &&
586 MI->getOperand(2).isImm() &&
587 MI->getOperand(2).getImm() == 0) {
588 FrameIndex = MI->getOperand(1).getIndex();
589 return MI->getOperand(0).getReg();
594 if (MI->getOperand(1).isFI() &&
595 MI->getOperand(2).isImm() &&
596 MI->getOperand(2).getImm() == 0) {
597 FrameIndex = MI->getOperand(1).getIndex();
598 return MI->getOperand(0).getReg();
607 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
608 MachineBasicBlock::iterator I,
609 unsigned DestReg, unsigned SrcReg,
610 const TargetRegisterClass *DestRC,
611 const TargetRegisterClass *SrcRC) const {
612 DebugLoc DL = DebugLoc::getUnknownLoc();
613 if (I != MBB.end()) DL = I->getDebugLoc();
615 if (DestRC != SrcRC) {
616 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
617 // Allow QPR / QPR_VFP2 cross-class copies
618 if (DestRC == ARM::DPRRegisterClass) {
619 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
620 SrcRC == ARM::DPR_8RegisterClass) {
623 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
624 if (SrcRC == ARM::DPRRegisterClass ||
625 SrcRC == ARM::DPR_8RegisterClass) {
628 } else if (DestRC == ARM::DPR_8RegisterClass) {
629 if (SrcRC == ARM::DPRRegisterClass ||
630 SrcRC == ARM::DPR_VFP2RegisterClass) {
633 } else if ((DestRC == ARM::QPRRegisterClass &&
634 SrcRC == ARM::QPR_VFP2RegisterClass) ||
635 (DestRC == ARM::QPR_VFP2RegisterClass &&
636 SrcRC == ARM::QPRRegisterClass)) {
641 if (DestRC == ARM::GPRRegisterClass) {
642 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
643 DestReg).addReg(SrcReg)));
644 } else if (DestRC == ARM::SPRRegisterClass) {
645 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
647 } else if ((DestRC == ARM::DPRRegisterClass) ||
648 (DestRC == ARM::DPR_VFP2RegisterClass) ||
649 (DestRC == ARM::DPR_8RegisterClass)) {
650 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
652 } else if (DestRC == ARM::QPRRegisterClass ||
653 DestRC == ARM::QPR_VFP2RegisterClass) {
654 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
662 void ARMBaseInstrInfo::
663 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
664 unsigned SrcReg, bool isKill, int FI,
665 const TargetRegisterClass *RC) const {
666 DebugLoc DL = DebugLoc::getUnknownLoc();
667 if (I != MBB.end()) DL = I->getDebugLoc();
669 if (RC == ARM::GPRRegisterClass) {
670 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
671 .addReg(SrcReg, getKillRegState(isKill))
672 .addFrameIndex(FI).addReg(0).addImm(0));
673 } else if (RC == ARM::DPRRegisterClass ||
674 RC == ARM::DPR_VFP2RegisterClass ||
675 RC == ARM::DPR_8RegisterClass) {
676 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
677 .addReg(SrcReg, getKillRegState(isKill))
678 .addFrameIndex(FI).addImm(0));
679 } else if (RC == ARM::SPRRegisterClass) {
680 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
681 .addReg(SrcReg, getKillRegState(isKill))
682 .addFrameIndex(FI).addImm(0));
684 assert((RC == ARM::QPRRegisterClass ||
685 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
686 // FIXME: Neon instructions should support predicates
687 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
688 .addFrameIndex(FI).addImm(0);
692 void ARMBaseInstrInfo::
693 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
694 unsigned DestReg, int FI,
695 const TargetRegisterClass *RC) const {
696 DebugLoc DL = DebugLoc::getUnknownLoc();
697 if (I != MBB.end()) DL = I->getDebugLoc();
699 if (RC == ARM::GPRRegisterClass) {
700 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
701 .addFrameIndex(FI).addReg(0).addImm(0));
702 } else if (RC == ARM::DPRRegisterClass ||
703 RC == ARM::DPR_VFP2RegisterClass ||
704 RC == ARM::DPR_8RegisterClass) {
705 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
706 .addFrameIndex(FI).addImm(0));
707 } else if (RC == ARM::SPRRegisterClass) {
708 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
709 .addFrameIndex(FI).addImm(0));
711 assert((RC == ARM::QPRRegisterClass ||
712 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
713 // FIXME: Neon instructions should support predicates
714 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0);
718 MachineInstr *ARMBaseInstrInfo::
719 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
720 const SmallVectorImpl<unsigned> &Ops, int FI) const {
721 if (Ops.size() != 1) return NULL;
723 unsigned OpNum = Ops[0];
724 unsigned Opc = MI->getOpcode();
725 MachineInstr *NewMI = NULL;
726 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
727 // If it is updating CPSR, then it cannot be folded.
728 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
730 unsigned Pred = MI->getOperand(2).getImm();
731 unsigned PredReg = MI->getOperand(3).getReg();
732 if (OpNum == 0) { // move -> store
733 unsigned SrcReg = MI->getOperand(1).getReg();
734 bool isKill = MI->getOperand(1).isKill();
735 bool isUndef = MI->getOperand(1).isUndef();
736 if (Opc == ARM::MOVr)
737 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
738 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
739 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
741 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
742 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
743 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
744 } else { // move -> load
745 unsigned DstReg = MI->getOperand(0).getReg();
746 bool isDead = MI->getOperand(0).isDead();
747 bool isUndef = MI->getOperand(0).isUndef();
748 if (Opc == ARM::MOVr)
749 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
752 getDeadRegState(isDead) |
753 getUndefRegState(isUndef))
754 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
756 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
759 getDeadRegState(isDead) |
760 getUndefRegState(isUndef))
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
763 } else if (Opc == ARM::tMOVgpr2gpr ||
764 Opc == ARM::tMOVtgpr2gpr ||
765 Opc == ARM::tMOVgpr2tgpr) {
766 if (OpNum == 0) { // move -> store
767 unsigned SrcReg = MI->getOperand(1).getReg();
768 bool isKill = MI->getOperand(1).isKill();
769 bool isUndef = MI->getOperand(1).isUndef();
770 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
771 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
772 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
773 } else { // move -> load
774 unsigned DstReg = MI->getOperand(0).getReg();
775 bool isDead = MI->getOperand(0).isDead();
776 bool isUndef = MI->getOperand(0).isUndef();
777 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
780 getDeadRegState(isDead) |
781 getUndefRegState(isUndef))
782 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
784 } else if (Opc == ARM::FCPYS) {
785 unsigned Pred = MI->getOperand(2).getImm();
786 unsigned PredReg = MI->getOperand(3).getReg();
787 if (OpNum == 0) { // move -> store
788 unsigned SrcReg = MI->getOperand(1).getReg();
789 bool isKill = MI->getOperand(1).isKill();
790 bool isUndef = MI->getOperand(1).isUndef();
791 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
792 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
794 .addImm(0).addImm(Pred).addReg(PredReg);
795 } else { // move -> load
796 unsigned DstReg = MI->getOperand(0).getReg();
797 bool isDead = MI->getOperand(0).isDead();
798 bool isUndef = MI->getOperand(0).isUndef();
799 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
802 getDeadRegState(isDead) |
803 getUndefRegState(isUndef))
804 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
807 else if (Opc == ARM::FCPYD) {
808 unsigned Pred = MI->getOperand(2).getImm();
809 unsigned PredReg = MI->getOperand(3).getReg();
810 if (OpNum == 0) { // move -> store
811 unsigned SrcReg = MI->getOperand(1).getReg();
812 bool isKill = MI->getOperand(1).isKill();
813 bool isUndef = MI->getOperand(1).isUndef();
814 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
815 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
816 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
817 } else { // move -> load
818 unsigned DstReg = MI->getOperand(0).getReg();
819 bool isDead = MI->getOperand(0).isDead();
820 bool isUndef = MI->getOperand(0).isUndef();
821 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
824 getDeadRegState(isDead) |
825 getUndefRegState(isUndef))
826 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
834 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
836 const SmallVectorImpl<unsigned> &Ops,
837 MachineInstr* LoadMI) const {
843 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
844 const SmallVectorImpl<unsigned> &Ops) const {
845 if (Ops.size() != 1) return false;
847 unsigned Opc = MI->getOpcode();
848 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
849 // If it is updating CPSR, then it cannot be folded.
850 return MI->getOperand(4).getReg() != ARM::CPSR ||
851 MI->getOperand(4).isDead();
852 } else if (Opc == ARM::tMOVgpr2gpr ||
853 Opc == ARM::tMOVtgpr2gpr ||
854 Opc == ARM::tMOVgpr2tgpr) {
856 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
858 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
859 return false; // FIXME
865 /// getInstrPredicate - If instruction is predicated, returns its predicate
866 /// condition, otherwise returns AL. It also returns the condition code
867 /// register by reference.
869 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
870 int PIdx = MI->findFirstPredOperandIdx();
876 PredReg = MI->getOperand(PIdx+1).getReg();
877 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
881 int llvm::getMatchingCondBranchOpcode(int Opc) {
884 else if (Opc == ARM::tB)
886 else if (Opc == ARM::t2B)
889 llvm_unreachable("Unknown unconditional branch opcode!");
894 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
895 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
896 unsigned DestReg, unsigned BaseReg, int NumBytes,
897 ARMCC::CondCodes Pred, unsigned PredReg,
898 const ARMBaseInstrInfo &TII) {
899 bool isSub = NumBytes < 0;
900 if (isSub) NumBytes = -NumBytes;
903 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
904 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
905 assert(ThisVal && "Didn't extract field correctly");
907 // We will handle these bits from offset, clear them.
908 NumBytes &= ~ThisVal;
910 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
912 // Build the new ADD / SUB.
913 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
914 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
915 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
916 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
921 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
922 unsigned FrameReg, int &Offset,
923 const ARMBaseInstrInfo &TII) {
924 unsigned Opcode = MI.getOpcode();
925 const TargetInstrDesc &Desc = MI.getDesc();
926 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
929 // Memory operands in inline assembly always use AddrMode2.
930 if (Opcode == ARM::INLINEASM)
931 AddrMode = ARMII::AddrMode2;
933 if (Opcode == ARM::ADDri) {
934 Offset += MI.getOperand(FrameRegIdx+1).getImm();
936 // Turn it into a move.
937 MI.setDesc(TII.get(ARM::MOVr));
938 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
939 MI.RemoveOperand(FrameRegIdx+1);
942 } else if (Offset < 0) {
945 MI.setDesc(TII.get(ARM::SUBri));
948 // Common case: small offset, fits into instruction.
949 if (ARM_AM::getSOImmVal(Offset) != -1) {
950 // Replace the FrameIndex with sp / fp
951 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
952 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
957 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
959 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
960 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
962 // We will handle these bits from offset, clear them.
963 Offset &= ~ThisImmVal;
965 // Get the properly encoded SOImmVal field.
966 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
967 "Bit extraction didn't work?");
968 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
972 unsigned NumBits = 0;
975 case ARMII::AddrMode2: {
976 ImmIdx = FrameRegIdx+2;
977 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
978 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
983 case ARMII::AddrMode3: {
984 ImmIdx = FrameRegIdx+2;
985 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
986 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
991 case ARMII::AddrMode4:
992 // Can't fold any offset even if it's zero.
994 case ARMII::AddrMode5: {
995 ImmIdx = FrameRegIdx+1;
996 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
997 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1004 llvm_unreachable("Unsupported addressing mode!");
1008 Offset += InstrOffs * Scale;
1009 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1015 // Attempt to fold address comp. if opcode has offset bits
1017 // Common case: small offset, fits into instruction.
1018 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1019 int ImmedOffset = Offset / Scale;
1020 unsigned Mask = (1 << NumBits) - 1;
1021 if ((unsigned)Offset <= Mask * Scale) {
1022 // Replace the FrameIndex with sp
1023 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1025 ImmedOffset |= 1 << NumBits;
1026 ImmOp.ChangeToImmediate(ImmedOffset);
1031 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1032 ImmedOffset = ImmedOffset & Mask;
1034 ImmedOffset |= 1 << NumBits;
1035 ImmOp.ChangeToImmediate(ImmedOffset);
1036 Offset &= ~(Mask*Scale);
1040 Offset = (isSub) ? -Offset : Offset;