1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineMemOperand.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
34 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
35 cl::desc("Enable ARM 2-addr to 3-addr conv"));
37 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
38 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
43 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
44 MachineBasicBlock::iterator &MBBI,
45 LiveVariables *LV) const {
46 // FIXME: Thumb2 support.
51 MachineInstr *MI = MBBI;
52 MachineFunction &MF = *MI->getParent()->getParent();
53 unsigned TSFlags = MI->getDesc().TSFlags;
55 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
57 case ARMII::IndexModePre:
60 case ARMII::IndexModePost:
64 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
66 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
70 MachineInstr *UpdateMI = NULL;
71 MachineInstr *MemMI = NULL;
72 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
73 const TargetInstrDesc &TID = MI->getDesc();
74 unsigned NumOps = TID.getNumOperands();
75 bool isLoad = !TID.mayStore();
76 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
77 const MachineOperand &Base = MI->getOperand(2);
78 const MachineOperand &Offset = MI->getOperand(NumOps-3);
79 unsigned WBReg = WB.getReg();
80 unsigned BaseReg = Base.getReg();
81 unsigned OffReg = Offset.getReg();
82 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
83 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
86 assert(false && "Unknown indexed op!");
88 case ARMII::AddrMode2: {
89 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
90 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
92 if (ARM_AM::getSOImmVal(Amt) == -1)
93 // Can't encode it in a so_imm operand. This transformation will
94 // add more than 1 instruction. Abandon!
96 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
97 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
98 .addReg(BaseReg).addImm(Amt)
99 .addImm(Pred).addReg(0).addReg(0);
100 } else if (Amt != 0) {
101 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
102 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
103 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
104 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
105 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
106 .addImm(Pred).addReg(0).addReg(0);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
110 .addReg(BaseReg).addReg(OffReg)
111 .addImm(Pred).addReg(0).addReg(0);
114 case ARMII::AddrMode3 : {
115 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
116 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
118 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
119 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
120 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
121 .addReg(BaseReg).addImm(Amt)
122 .addImm(Pred).addReg(0).addReg(0);
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
126 .addReg(BaseReg).addReg(OffReg)
127 .addImm(Pred).addReg(0).addReg(0);
132 std::vector<MachineInstr*> NewMIs;
135 MemMI = BuildMI(MF, MI->getDebugLoc(),
136 get(MemOpc), MI->getOperand(0).getReg())
137 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
139 MemMI = BuildMI(MF, MI->getDebugLoc(),
140 get(MemOpc)).addReg(MI->getOperand(1).getReg())
141 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
142 NewMIs.push_back(MemMI);
143 NewMIs.push_back(UpdateMI);
146 MemMI = BuildMI(MF, MI->getDebugLoc(),
147 get(MemOpc), MI->getOperand(0).getReg())
148 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
150 MemMI = BuildMI(MF, MI->getDebugLoc(),
151 get(MemOpc)).addReg(MI->getOperand(1).getReg())
152 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
154 UpdateMI->getOperand(0).setIsDead();
155 NewMIs.push_back(UpdateMI);
156 NewMIs.push_back(MemMI);
159 // Transfer LiveVariables states, kill / dead info.
161 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
162 MachineOperand &MO = MI->getOperand(i);
163 if (MO.isReg() && MO.getReg() &&
164 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
165 unsigned Reg = MO.getReg();
167 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
169 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
171 LV->addVirtualRegisterDead(Reg, NewMI);
173 if (MO.isUse() && MO.isKill()) {
174 for (unsigned j = 0; j < 2; ++j) {
175 // Look at the two new MI's in reverse order.
176 MachineInstr *NewMI = NewMIs[j];
177 if (!NewMI->readsRegister(Reg))
179 LV->addVirtualRegisterKilled(Reg, NewMI);
180 if (VI.removeKill(MI))
181 VI.Kills.push_back(NewMI);
189 MFI->insert(MBBI, NewMIs[1]);
190 MFI->insert(MBBI, NewMIs[0]);
196 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
197 MachineBasicBlock *&FBB,
198 SmallVectorImpl<MachineOperand> &Cond,
199 bool AllowModify) const {
200 // If the block has no terminators, it just falls into the block after it.
201 MachineBasicBlock::iterator I = MBB.end();
202 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
205 // Get the last instruction in the block.
206 MachineInstr *LastInst = I;
208 // If there is only one terminator instruction, process it.
209 unsigned LastOpc = LastInst->getOpcode();
210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
211 if (isUncondBranchOpcode(LastOpc)) {
212 TBB = LastInst->getOperand(0).getMBB();
215 if (isCondBranchOpcode(LastOpc)) {
216 // Block ends with fall-through condbranch.
217 TBB = LastInst->getOperand(0).getMBB();
218 Cond.push_back(LastInst->getOperand(1));
219 Cond.push_back(LastInst->getOperand(2));
222 return true; // Can't handle indirect branch.
225 // Get the instruction before it if it is a terminator.
226 MachineInstr *SecondLastInst = I;
228 // If there are three terminators, we don't know what sort of block this is.
229 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
232 // If the block ends with a B and a Bcc, handle it.
233 unsigned SecondLastOpc = SecondLastInst->getOpcode();
234 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
235 TBB = SecondLastInst->getOperand(0).getMBB();
236 Cond.push_back(SecondLastInst->getOperand(1));
237 Cond.push_back(SecondLastInst->getOperand(2));
238 FBB = LastInst->getOperand(0).getMBB();
242 // If the block ends with two unconditional branches, handle it. The second
243 // one is not executed, so remove it.
244 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
245 TBB = SecondLastInst->getOperand(0).getMBB();
248 I->eraseFromParent();
252 // ...likewise if it ends with a branch table followed by an unconditional
253 // branch. The branch folder can create these, and we must get rid of them for
254 // correctness of Thumb constant islands.
255 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
256 isIndirectBranchOpcode(SecondLastOpc)) &&
257 isUncondBranchOpcode(LastOpc)) {
260 I->eraseFromParent();
264 // Otherwise, can't handle this.
269 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
270 MachineBasicBlock::iterator I = MBB.end();
271 if (I == MBB.begin()) return 0;
273 if (!isUncondBranchOpcode(I->getOpcode()) &&
274 !isCondBranchOpcode(I->getOpcode()))
277 // Remove the branch.
278 I->eraseFromParent();
282 if (I == MBB.begin()) return 1;
284 if (!isCondBranchOpcode(I->getOpcode()))
287 // Remove the branch.
288 I->eraseFromParent();
293 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
294 MachineBasicBlock *FBB,
295 const SmallVectorImpl<MachineOperand> &Cond) const {
296 // FIXME this should probably have a DebugLoc argument
297 DebugLoc dl = DebugLoc::getUnknownLoc();
299 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
300 int BOpc = !AFI->isThumbFunction()
301 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
302 int BccOpc = !AFI->isThumbFunction()
303 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
305 // Shouldn't be a fall through.
306 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
307 assert((Cond.size() == 2 || Cond.size() == 0) &&
308 "ARM branch conditions have two components!");
311 if (Cond.empty()) // Unconditional branch?
312 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
314 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
315 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
319 // Two-way conditional branch.
320 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
321 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
322 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
326 bool ARMBaseInstrInfo::
327 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
328 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
329 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
333 bool ARMBaseInstrInfo::
334 PredicateInstruction(MachineInstr *MI,
335 const SmallVectorImpl<MachineOperand> &Pred) const {
336 unsigned Opc = MI->getOpcode();
337 if (isUncondBranchOpcode(Opc)) {
338 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
339 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
340 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
344 int PIdx = MI->findFirstPredOperandIdx();
346 MachineOperand &PMO = MI->getOperand(PIdx);
347 PMO.setImm(Pred[0].getImm());
348 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
354 bool ARMBaseInstrInfo::
355 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
356 const SmallVectorImpl<MachineOperand> &Pred2) const {
357 if (Pred1.size() > 2 || Pred2.size() > 2)
360 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
361 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
371 return CC2 == ARMCC::HI;
373 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
375 return CC2 == ARMCC::GT;
377 return CC2 == ARMCC::LT;
381 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
382 std::vector<MachineOperand> &Pred) const {
383 // FIXME: This confuses implicit_def with optional CPSR def.
384 const TargetInstrDesc &TID = MI->getDesc();
385 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
389 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
390 const MachineOperand &MO = MI->getOperand(i);
391 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
401 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
402 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
403 unsigned JTI) DISABLE_INLINE;
404 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
406 return JT[JTI].MBBs.size();
409 /// GetInstSize - Return the size of the specified MachineInstr.
411 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
412 const MachineBasicBlock &MBB = *MI->getParent();
413 const MachineFunction *MF = MBB.getParent();
414 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
416 // Basic size info comes from the TSFlags field.
417 const TargetInstrDesc &TID = MI->getDesc();
418 unsigned TSFlags = TID.TSFlags;
420 unsigned Opc = MI->getOpcode();
421 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
423 // If this machine instr is an inline asm, measure it.
424 if (MI->getOpcode() == ARM::INLINEASM)
425 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
430 llvm_unreachable("Unknown or unset size field for instr!");
431 case TargetInstrInfo::IMPLICIT_DEF:
432 case TargetInstrInfo::KILL:
433 case TargetInstrInfo::DBG_LABEL:
434 case TargetInstrInfo::EH_LABEL:
439 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
440 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
441 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
442 case ARMII::SizeSpecial: {
444 case ARM::CONSTPOOL_ENTRY:
445 // If this machine instr is a constant pool entry, its size is recorded as
447 return MI->getOperand(2).getImm();
448 case ARM::Int_eh_sjlj_setjmp:
450 case ARM::t2Int_eh_sjlj_setjmp:
459 // These are jumptable branches, i.e. a branch followed by an inlined
460 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
461 // entry is one byte; TBH two byte each.
462 unsigned EntrySize = (Opc == ARM::t2TBB)
463 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
464 unsigned NumOps = TID.getNumOperands();
465 MachineOperand JTOP =
466 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
467 unsigned JTI = JTOP.getIndex();
468 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
469 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
470 assert(JTI < JT.size());
471 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
472 // 4 aligned. The assembler / linker may add 2 byte padding just before
473 // the JT entries. The size does not include this padding; the
474 // constant islands pass does separate bookkeeping for it.
475 // FIXME: If we know the size of the function is less than (1 << 16) *2
476 // bytes, we can use 16-bit entries instead. Then there won't be an
478 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
479 unsigned NumEntries = getNumJTEntries(JT, JTI);
480 if (Opc == ARM::t2TBB && (NumEntries & 1))
481 // Make sure the instruction that follows TBB is 2-byte aligned.
482 // FIXME: Constant island pass should insert an "ALIGN" instruction
485 return NumEntries * EntrySize + InstSize;
488 // Otherwise, pseudo-instruction sizes are zero.
493 return 0; // Not reached
496 /// Return true if the instruction is a register to register move and
497 /// leave the source and dest operands in the passed parameters.
500 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
501 unsigned &SrcReg, unsigned &DstReg,
502 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
503 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
505 switch (MI.getOpcode()) {
511 SrcReg = MI.getOperand(1).getReg();
512 DstReg = MI.getOperand(0).getReg();
517 case ARM::tMOVgpr2tgpr:
518 case ARM::tMOVtgpr2gpr:
519 case ARM::tMOVgpr2gpr:
521 assert(MI.getDesc().getNumOperands() >= 2 &&
522 MI.getOperand(0).isReg() &&
523 MI.getOperand(1).isReg() &&
524 "Invalid ARM MOV instruction");
525 SrcReg = MI.getOperand(1).getReg();
526 DstReg = MI.getOperand(0).getReg();
535 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
536 int &FrameIndex) const {
537 switch (MI->getOpcode()) {
540 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
541 if (MI->getOperand(1).isFI() &&
542 MI->getOperand(2).isReg() &&
543 MI->getOperand(3).isImm() &&
544 MI->getOperand(2).getReg() == 0 &&
545 MI->getOperand(3).getImm() == 0) {
546 FrameIndex = MI->getOperand(1).getIndex();
547 return MI->getOperand(0).getReg();
552 if (MI->getOperand(1).isFI() &&
553 MI->getOperand(2).isImm() &&
554 MI->getOperand(2).getImm() == 0) {
555 FrameIndex = MI->getOperand(1).getIndex();
556 return MI->getOperand(0).getReg();
561 if (MI->getOperand(1).isFI() &&
562 MI->getOperand(2).isImm() &&
563 MI->getOperand(2).getImm() == 0) {
564 FrameIndex = MI->getOperand(1).getIndex();
565 return MI->getOperand(0).getReg();
574 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
575 int &FrameIndex) const {
576 switch (MI->getOpcode()) {
579 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
580 if (MI->getOperand(1).isFI() &&
581 MI->getOperand(2).isReg() &&
582 MI->getOperand(3).isImm() &&
583 MI->getOperand(2).getReg() == 0 &&
584 MI->getOperand(3).getImm() == 0) {
585 FrameIndex = MI->getOperand(1).getIndex();
586 return MI->getOperand(0).getReg();
591 if (MI->getOperand(1).isFI() &&
592 MI->getOperand(2).isImm() &&
593 MI->getOperand(2).getImm() == 0) {
594 FrameIndex = MI->getOperand(1).getIndex();
595 return MI->getOperand(0).getReg();
600 if (MI->getOperand(1).isFI() &&
601 MI->getOperand(2).isImm() &&
602 MI->getOperand(2).getImm() == 0) {
603 FrameIndex = MI->getOperand(1).getIndex();
604 return MI->getOperand(0).getReg();
613 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
614 MachineBasicBlock::iterator I,
615 unsigned DestReg, unsigned SrcReg,
616 const TargetRegisterClass *DestRC,
617 const TargetRegisterClass *SrcRC) const {
618 DebugLoc DL = DebugLoc::getUnknownLoc();
619 if (I != MBB.end()) DL = I->getDebugLoc();
621 if (DestRC != SrcRC) {
622 if (DestRC->getSize() != SrcRC->getSize())
625 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
626 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
627 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
631 if (DestRC == ARM::GPRRegisterClass) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
633 DestReg).addReg(SrcReg)));
634 } else if (DestRC == ARM::SPRRegisterClass) {
635 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
637 } else if (DestRC == ARM::DPRRegisterClass) {
638 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
640 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
641 DestRC == ARM::DPR_8RegisterClass ||
642 SrcRC == ARM::DPR_VFP2RegisterClass ||
643 SrcRC == ARM::DPR_8RegisterClass) {
644 // Always use neon reg-reg move if source or dest is NEON-only regclass.
645 BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg).addReg(SrcReg);
646 } else if (DestRC == ARM::QPRRegisterClass ||
647 DestRC == ARM::QPR_VFP2RegisterClass ||
648 DestRC == ARM::QPR_8RegisterClass) {
649 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
657 void ARMBaseInstrInfo::
658 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
659 unsigned SrcReg, bool isKill, int FI,
660 const TargetRegisterClass *RC) const {
661 DebugLoc DL = DebugLoc::getUnknownLoc();
662 if (I != MBB.end()) DL = I->getDebugLoc();
663 MachineFunction &MF = *MBB.getParent();
664 MachineFrameInfo &MFI = *MF.getFrameInfo();
666 MachineMemOperand *MMO =
667 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
668 MachineMemOperand::MOStore, 0,
669 MFI.getObjectSize(FI),
670 MFI.getObjectAlignment(FI));
672 if (RC == ARM::GPRRegisterClass) {
673 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
674 .addReg(SrcReg, getKillRegState(isKill))
675 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
676 } else if (RC == ARM::DPRRegisterClass ||
677 RC == ARM::DPR_VFP2RegisterClass ||
678 RC == ARM::DPR_8RegisterClass) {
679 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
680 .addReg(SrcReg, getKillRegState(isKill))
681 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
682 } else if (RC == ARM::SPRRegisterClass) {
683 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
684 .addReg(SrcReg, getKillRegState(isKill))
685 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
687 assert((RC == ARM::QPRRegisterClass ||
688 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
689 // FIXME: Neon instructions should support predicates
690 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
691 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
695 void ARMBaseInstrInfo::
696 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
697 unsigned DestReg, int FI,
698 const TargetRegisterClass *RC) const {
699 DebugLoc DL = DebugLoc::getUnknownLoc();
700 if (I != MBB.end()) DL = I->getDebugLoc();
701 MachineFunction &MF = *MBB.getParent();
702 MachineFrameInfo &MFI = *MF.getFrameInfo();
704 MachineMemOperand *MMO =
705 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
706 MachineMemOperand::MOLoad, 0,
707 MFI.getObjectSize(FI),
708 MFI.getObjectAlignment(FI));
710 if (RC == ARM::GPRRegisterClass) {
711 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
712 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
713 } else if (RC == ARM::DPRRegisterClass ||
714 RC == ARM::DPR_VFP2RegisterClass ||
715 RC == ARM::DPR_8RegisterClass) {
716 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
717 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
718 } else if (RC == ARM::SPRRegisterClass) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
720 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
722 assert((RC == ARM::QPRRegisterClass ||
723 RC == ARM::QPR_VFP2RegisterClass ||
724 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
725 // FIXME: Neon instructions should support predicates
726 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
731 MachineInstr *ARMBaseInstrInfo::
732 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
733 const SmallVectorImpl<unsigned> &Ops, int FI) const {
734 if (Ops.size() != 1) return NULL;
736 unsigned OpNum = Ops[0];
737 unsigned Opc = MI->getOpcode();
738 MachineInstr *NewMI = NULL;
739 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
740 // If it is updating CPSR, then it cannot be folded.
741 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
743 unsigned Pred = MI->getOperand(2).getImm();
744 unsigned PredReg = MI->getOperand(3).getReg();
745 if (OpNum == 0) { // move -> store
746 unsigned SrcReg = MI->getOperand(1).getReg();
747 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
748 bool isKill = MI->getOperand(1).isKill();
749 bool isUndef = MI->getOperand(1).isUndef();
750 if (Opc == ARM::MOVr)
751 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
753 getKillRegState(isKill) | getUndefRegState(isUndef),
755 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
759 getKillRegState(isKill) | getUndefRegState(isUndef),
761 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
762 } else { // move -> load
763 unsigned DstReg = MI->getOperand(0).getReg();
764 unsigned DstSubReg = MI->getOperand(0).getSubReg();
765 bool isDead = MI->getOperand(0).isDead();
766 bool isUndef = MI->getOperand(0).isUndef();
767 if (Opc == ARM::MOVr)
768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
771 getDeadRegState(isDead) |
772 getUndefRegState(isUndef), DstSubReg)
773 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
775 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
778 getDeadRegState(isDead) |
779 getUndefRegState(isUndef), DstSubReg)
780 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
782 } else if (Opc == ARM::tMOVgpr2gpr ||
783 Opc == ARM::tMOVtgpr2gpr ||
784 Opc == ARM::tMOVgpr2tgpr) {
785 if (OpNum == 0) { // move -> store
786 unsigned SrcReg = MI->getOperand(1).getReg();
787 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
788 bool isKill = MI->getOperand(1).isKill();
789 bool isUndef = MI->getOperand(1).isUndef();
790 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
792 getKillRegState(isKill) | getUndefRegState(isUndef),
794 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
795 } else { // move -> load
796 unsigned DstReg = MI->getOperand(0).getReg();
797 unsigned DstSubReg = MI->getOperand(0).getSubReg();
798 bool isDead = MI->getOperand(0).isDead();
799 bool isUndef = MI->getOperand(0).isUndef();
800 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
803 getDeadRegState(isDead) |
804 getUndefRegState(isUndef),
806 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
808 } else if (Opc == ARM::FCPYS) {
809 unsigned Pred = MI->getOperand(2).getImm();
810 unsigned PredReg = MI->getOperand(3).getReg();
811 if (OpNum == 0) { // move -> store
812 unsigned SrcReg = MI->getOperand(1).getReg();
813 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
814 bool isKill = MI->getOperand(1).isKill();
815 bool isUndef = MI->getOperand(1).isUndef();
816 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
817 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
820 .addImm(0).addImm(Pred).addReg(PredReg);
821 } else { // move -> load
822 unsigned DstReg = MI->getOperand(0).getReg();
823 unsigned DstSubReg = MI->getOperand(0).getSubReg();
824 bool isDead = MI->getOperand(0).isDead();
825 bool isUndef = MI->getOperand(0).isUndef();
826 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
829 getDeadRegState(isDead) |
830 getUndefRegState(isUndef),
832 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
835 else if (Opc == ARM::FCPYD) {
836 unsigned Pred = MI->getOperand(2).getImm();
837 unsigned PredReg = MI->getOperand(3).getReg();
838 if (OpNum == 0) { // move -> store
839 unsigned SrcReg = MI->getOperand(1).getReg();
840 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
841 bool isKill = MI->getOperand(1).isKill();
842 bool isUndef = MI->getOperand(1).isUndef();
843 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
845 getKillRegState(isKill) | getUndefRegState(isUndef),
847 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
848 } else { // move -> load
849 unsigned DstReg = MI->getOperand(0).getReg();
850 unsigned DstSubReg = MI->getOperand(0).getSubReg();
851 bool isDead = MI->getOperand(0).isDead();
852 bool isUndef = MI->getOperand(0).isUndef();
853 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
856 getDeadRegState(isDead) |
857 getUndefRegState(isUndef),
859 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
867 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
869 const SmallVectorImpl<unsigned> &Ops,
870 MachineInstr* LoadMI) const {
876 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
877 const SmallVectorImpl<unsigned> &Ops) const {
878 if (Ops.size() != 1) return false;
880 unsigned Opc = MI->getOpcode();
881 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
882 // If it is updating CPSR, then it cannot be folded.
883 return MI->getOperand(4).getReg() != ARM::CPSR ||
884 MI->getOperand(4).isDead();
885 } else if (Opc == ARM::tMOVgpr2gpr ||
886 Opc == ARM::tMOVtgpr2gpr ||
887 Opc == ARM::tMOVgpr2tgpr) {
889 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
891 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
892 return false; // FIXME
898 /// getInstrPredicate - If instruction is predicated, returns its predicate
899 /// condition, otherwise returns AL. It also returns the condition code
900 /// register by reference.
902 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
903 int PIdx = MI->findFirstPredOperandIdx();
909 PredReg = MI->getOperand(PIdx+1).getReg();
910 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
914 int llvm::getMatchingCondBranchOpcode(int Opc) {
917 else if (Opc == ARM::tB)
919 else if (Opc == ARM::t2B)
922 llvm_unreachable("Unknown unconditional branch opcode!");
927 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
928 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
929 unsigned DestReg, unsigned BaseReg, int NumBytes,
930 ARMCC::CondCodes Pred, unsigned PredReg,
931 const ARMBaseInstrInfo &TII) {
932 bool isSub = NumBytes < 0;
933 if (isSub) NumBytes = -NumBytes;
936 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
937 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
938 assert(ThisVal && "Didn't extract field correctly");
940 // We will handle these bits from offset, clear them.
941 NumBytes &= ~ThisVal;
943 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
945 // Build the new ADD / SUB.
946 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
947 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
948 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
949 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
954 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
955 unsigned FrameReg, int &Offset,
956 const ARMBaseInstrInfo &TII) {
957 unsigned Opcode = MI.getOpcode();
958 const TargetInstrDesc &Desc = MI.getDesc();
959 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
962 // Memory operands in inline assembly always use AddrMode2.
963 if (Opcode == ARM::INLINEASM)
964 AddrMode = ARMII::AddrMode2;
966 if (Opcode == ARM::ADDri) {
967 Offset += MI.getOperand(FrameRegIdx+1).getImm();
969 // Turn it into a move.
970 MI.setDesc(TII.get(ARM::MOVr));
971 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
972 MI.RemoveOperand(FrameRegIdx+1);
975 } else if (Offset < 0) {
978 MI.setDesc(TII.get(ARM::SUBri));
981 // Common case: small offset, fits into instruction.
982 if (ARM_AM::getSOImmVal(Offset) != -1) {
983 // Replace the FrameIndex with sp / fp
984 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
985 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
990 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
992 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
993 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
995 // We will handle these bits from offset, clear them.
996 Offset &= ~ThisImmVal;
998 // Get the properly encoded SOImmVal field.
999 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1000 "Bit extraction didn't work?");
1001 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1003 unsigned ImmIdx = 0;
1005 unsigned NumBits = 0;
1008 case ARMII::AddrMode2: {
1009 ImmIdx = FrameRegIdx+2;
1010 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1011 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1016 case ARMII::AddrMode3: {
1017 ImmIdx = FrameRegIdx+2;
1018 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1019 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1024 case ARMII::AddrMode4:
1025 // Can't fold any offset even if it's zero.
1027 case ARMII::AddrMode5: {
1028 ImmIdx = FrameRegIdx+1;
1029 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1030 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1037 llvm_unreachable("Unsupported addressing mode!");
1041 Offset += InstrOffs * Scale;
1042 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1048 // Attempt to fold address comp. if opcode has offset bits
1050 // Common case: small offset, fits into instruction.
1051 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1052 int ImmedOffset = Offset / Scale;
1053 unsigned Mask = (1 << NumBits) - 1;
1054 if ((unsigned)Offset <= Mask * Scale) {
1055 // Replace the FrameIndex with sp
1056 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1058 ImmedOffset |= 1 << NumBits;
1059 ImmOp.ChangeToImmediate(ImmedOffset);
1064 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1065 ImmedOffset = ImmedOffset & Mask;
1067 ImmedOffset |= 1 << NumBits;
1068 ImmOp.ChangeToImmediate(ImmedOffset);
1069 Offset &= ~(Mask*Scale);
1073 Offset = (isSub) ? -Offset : Offset;