1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
39 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
40 cl::desc("Enable ARM 2-addr to 3-addr conv"));
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
49 MachineBasicBlock::iterator &MBBI,
50 LiveVariables *LV) const {
51 // FIXME: Thumb2 support.
56 MachineInstr *MI = MBBI;
57 MachineFunction &MF = *MI->getParent()->getParent();
58 unsigned TSFlags = MI->getDesc().TSFlags;
60 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
62 case ARMII::IndexModePre:
65 case ARMII::IndexModePost:
69 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
71 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
75 MachineInstr *UpdateMI = NULL;
76 MachineInstr *MemMI = NULL;
77 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
78 const TargetInstrDesc &TID = MI->getDesc();
79 unsigned NumOps = TID.getNumOperands();
80 bool isLoad = !TID.mayStore();
81 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
82 const MachineOperand &Base = MI->getOperand(2);
83 const MachineOperand &Offset = MI->getOperand(NumOps-3);
84 unsigned WBReg = WB.getReg();
85 unsigned BaseReg = Base.getReg();
86 unsigned OffReg = Offset.getReg();
87 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
88 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
91 assert(false && "Unknown indexed op!");
93 case ARMII::AddrMode2: {
94 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
95 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
97 if (ARM_AM::getSOImmVal(Amt) == -1)
98 // Can't encode it in a so_imm operand. This transformation will
99 // add more than 1 instruction. Abandon!
101 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
102 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
103 .addReg(BaseReg).addImm(Amt)
104 .addImm(Pred).addReg(0).addReg(0);
105 } else if (Amt != 0) {
106 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
107 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
108 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
109 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
110 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
111 .addImm(Pred).addReg(0).addReg(0);
113 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
114 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
115 .addReg(BaseReg).addReg(OffReg)
116 .addImm(Pred).addReg(0).addReg(0);
119 case ARMII::AddrMode3 : {
120 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
121 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
123 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
124 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
125 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
126 .addReg(BaseReg).addImm(Amt)
127 .addImm(Pred).addReg(0).addReg(0);
129 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
130 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
131 .addReg(BaseReg).addReg(OffReg)
132 .addImm(Pred).addReg(0).addReg(0);
137 std::vector<MachineInstr*> NewMIs;
140 MemMI = BuildMI(MF, MI->getDebugLoc(),
141 get(MemOpc), MI->getOperand(0).getReg())
142 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
144 MemMI = BuildMI(MF, MI->getDebugLoc(),
145 get(MemOpc)).addReg(MI->getOperand(1).getReg())
146 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
147 NewMIs.push_back(MemMI);
148 NewMIs.push_back(UpdateMI);
151 MemMI = BuildMI(MF, MI->getDebugLoc(),
152 get(MemOpc), MI->getOperand(0).getReg())
153 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
155 MemMI = BuildMI(MF, MI->getDebugLoc(),
156 get(MemOpc)).addReg(MI->getOperand(1).getReg())
157 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
159 UpdateMI->getOperand(0).setIsDead();
160 NewMIs.push_back(UpdateMI);
161 NewMIs.push_back(MemMI);
164 // Transfer LiveVariables states, kill / dead info.
166 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 MachineOperand &MO = MI->getOperand(i);
168 if (MO.isReg() && MO.getReg() &&
169 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
170 unsigned Reg = MO.getReg();
172 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
174 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
176 LV->addVirtualRegisterDead(Reg, NewMI);
178 if (MO.isUse() && MO.isKill()) {
179 for (unsigned j = 0; j < 2; ++j) {
180 // Look at the two new MI's in reverse order.
181 MachineInstr *NewMI = NewMIs[j];
182 if (!NewMI->readsRegister(Reg))
184 LV->addVirtualRegisterKilled(Reg, NewMI);
185 if (VI.removeKill(MI))
186 VI.Kills.push_back(NewMI);
194 MFI->insert(MBBI, NewMIs[1]);
195 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const {
205 // If the block has no terminators, it just falls into the block after it.
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
210 // Get the last instruction in the block.
211 MachineInstr *LastInst = I;
213 // If there is only one terminator instruction, process it.
214 unsigned LastOpc = LastInst->getOpcode();
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216 if (isUncondBranchOpcode(LastOpc)) {
217 TBB = LastInst->getOperand(0).getMBB();
220 if (isCondBranchOpcode(LastOpc)) {
221 // Block ends with fall-through condbranch.
222 TBB = LastInst->getOperand(0).getMBB();
223 Cond.push_back(LastInst->getOperand(1));
224 Cond.push_back(LastInst->getOperand(2));
227 return true; // Can't handle indirect branch.
230 // Get the instruction before it if it is a terminator.
231 MachineInstr *SecondLastInst = I;
233 // If there are three terminators, we don't know what sort of block this is.
234 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
237 // If the block ends with a B and a Bcc, handle it.
238 unsigned SecondLastOpc = SecondLastInst->getOpcode();
239 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
240 TBB = SecondLastInst->getOperand(0).getMBB();
241 Cond.push_back(SecondLastInst->getOperand(1));
242 Cond.push_back(SecondLastInst->getOperand(2));
243 FBB = LastInst->getOperand(0).getMBB();
247 // If the block ends with two unconditional branches, handle it. The second
248 // one is not executed, so remove it.
249 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
250 TBB = SecondLastInst->getOperand(0).getMBB();
253 I->eraseFromParent();
257 // ...likewise if it ends with a branch table followed by an unconditional
258 // branch. The branch folder can create these, and we must get rid of them for
259 // correctness of Thumb constant islands.
260 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
261 isIndirectBranchOpcode(SecondLastOpc)) &&
262 isUncondBranchOpcode(LastOpc)) {
265 I->eraseFromParent();
269 // Otherwise, can't handle this.
274 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
275 MachineBasicBlock::iterator I = MBB.end();
276 if (I == MBB.begin()) return 0;
278 if (!isUncondBranchOpcode(I->getOpcode()) &&
279 !isCondBranchOpcode(I->getOpcode()))
282 // Remove the branch.
283 I->eraseFromParent();
287 if (I == MBB.begin()) return 1;
289 if (!isCondBranchOpcode(I->getOpcode()))
292 // Remove the branch.
293 I->eraseFromParent();
298 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
299 MachineBasicBlock *FBB,
300 const SmallVectorImpl<MachineOperand> &Cond) const {
301 // FIXME this should probably have a DebugLoc argument
302 DebugLoc dl = DebugLoc::getUnknownLoc();
304 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
305 int BOpc = !AFI->isThumbFunction()
306 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
307 int BccOpc = !AFI->isThumbFunction()
308 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
310 // Shouldn't be a fall through.
311 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
312 assert((Cond.size() == 2 || Cond.size() == 0) &&
313 "ARM branch conditions have two components!");
316 if (Cond.empty()) // Unconditional branch?
317 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
319 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
320 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
324 // Two-way conditional branch.
325 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
326 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
327 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
331 bool ARMBaseInstrInfo::
332 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
333 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
334 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
338 bool ARMBaseInstrInfo::
339 PredicateInstruction(MachineInstr *MI,
340 const SmallVectorImpl<MachineOperand> &Pred) const {
341 unsigned Opc = MI->getOpcode();
342 if (isUncondBranchOpcode(Opc)) {
343 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
344 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
345 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
349 int PIdx = MI->findFirstPredOperandIdx();
351 MachineOperand &PMO = MI->getOperand(PIdx);
352 PMO.setImm(Pred[0].getImm());
353 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
359 bool ARMBaseInstrInfo::
360 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
361 const SmallVectorImpl<MachineOperand> &Pred2) const {
362 if (Pred1.size() > 2 || Pred2.size() > 2)
365 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
366 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
376 return CC2 == ARMCC::HI;
378 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
380 return CC2 == ARMCC::GT;
382 return CC2 == ARMCC::LT;
386 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
387 std::vector<MachineOperand> &Pred) const {
388 // FIXME: This confuses implicit_def with optional CPSR def.
389 const TargetInstrDesc &TID = MI->getDesc();
390 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
394 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
395 const MachineOperand &MO = MI->getOperand(i);
396 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
405 /// isPredicable - Return true if the specified instruction can be predicated.
406 /// By default, this returns true for every instruction with a
407 /// PredicateOperand.
408 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
409 const TargetInstrDesc &TID = MI->getDesc();
410 if (!TID.isPredicable())
413 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
414 ARMFunctionInfo *AFI =
415 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
416 return AFI->isThumb2Function();
421 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
423 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
425 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
427 assert(JTI < JT.size());
428 return JT[JTI].MBBs.size();
431 /// GetInstSize - Return the size of the specified MachineInstr.
433 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
434 const MachineBasicBlock &MBB = *MI->getParent();
435 const MachineFunction *MF = MBB.getParent();
436 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
438 // Basic size info comes from the TSFlags field.
439 const TargetInstrDesc &TID = MI->getDesc();
440 unsigned TSFlags = TID.TSFlags;
442 unsigned Opc = MI->getOpcode();
443 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
445 // If this machine instr is an inline asm, measure it.
446 if (MI->getOpcode() == ARM::INLINEASM)
447 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
452 llvm_unreachable("Unknown or unset size field for instr!");
453 case TargetInstrInfo::IMPLICIT_DEF:
454 case TargetInstrInfo::KILL:
455 case TargetInstrInfo::DBG_LABEL:
456 case TargetInstrInfo::EH_LABEL:
461 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
462 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
463 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
464 case ARMII::SizeSpecial: {
466 case ARM::CONSTPOOL_ENTRY:
467 // If this machine instr is a constant pool entry, its size is recorded as
469 return MI->getOperand(2).getImm();
470 case ARM::Int_eh_sjlj_setjmp:
472 case ARM::tInt_eh_sjlj_setjmp:
474 case ARM::t2Int_eh_sjlj_setjmp:
483 // These are jumptable branches, i.e. a branch followed by an inlined
484 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
485 // entry is one byte; TBH two byte each.
486 unsigned EntrySize = (Opc == ARM::t2TBB)
487 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
488 unsigned NumOps = TID.getNumOperands();
489 MachineOperand JTOP =
490 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
491 unsigned JTI = JTOP.getIndex();
492 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
493 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
494 assert(JTI < JT.size());
495 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
496 // 4 aligned. The assembler / linker may add 2 byte padding just before
497 // the JT entries. The size does not include this padding; the
498 // constant islands pass does separate bookkeeping for it.
499 // FIXME: If we know the size of the function is less than (1 << 16) *2
500 // bytes, we can use 16-bit entries instead. Then there won't be an
502 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
503 unsigned NumEntries = getNumJTEntries(JT, JTI);
504 if (Opc == ARM::t2TBB && (NumEntries & 1))
505 // Make sure the instruction that follows TBB is 2-byte aligned.
506 // FIXME: Constant island pass should insert an "ALIGN" instruction
509 return NumEntries * EntrySize + InstSize;
512 // Otherwise, pseudo-instruction sizes are zero.
517 return 0; // Not reached
520 /// Return true if the instruction is a register to register move and
521 /// leave the source and dest operands in the passed parameters.
524 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
525 unsigned &SrcReg, unsigned &DstReg,
526 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
527 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
529 switch (MI.getOpcode()) {
535 SrcReg = MI.getOperand(1).getReg();
536 DstReg = MI.getOperand(0).getReg();
541 case ARM::tMOVgpr2tgpr:
542 case ARM::tMOVtgpr2gpr:
543 case ARM::tMOVgpr2gpr:
545 assert(MI.getDesc().getNumOperands() >= 2 &&
546 MI.getOperand(0).isReg() &&
547 MI.getOperand(1).isReg() &&
548 "Invalid ARM MOV instruction");
549 SrcReg = MI.getOperand(1).getReg();
550 DstReg = MI.getOperand(0).getReg();
559 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
560 int &FrameIndex) const {
561 switch (MI->getOpcode()) {
564 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
565 if (MI->getOperand(1).isFI() &&
566 MI->getOperand(2).isReg() &&
567 MI->getOperand(3).isImm() &&
568 MI->getOperand(2).getReg() == 0 &&
569 MI->getOperand(3).getImm() == 0) {
570 FrameIndex = MI->getOperand(1).getIndex();
571 return MI->getOperand(0).getReg();
576 if (MI->getOperand(1).isFI() &&
577 MI->getOperand(2).isImm() &&
578 MI->getOperand(2).getImm() == 0) {
579 FrameIndex = MI->getOperand(1).getIndex();
580 return MI->getOperand(0).getReg();
585 if (MI->getOperand(1).isFI() &&
586 MI->getOperand(2).isImm() &&
587 MI->getOperand(2).getImm() == 0) {
588 FrameIndex = MI->getOperand(1).getIndex();
589 return MI->getOperand(0).getReg();
598 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
599 int &FrameIndex) const {
600 switch (MI->getOpcode()) {
603 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
604 if (MI->getOperand(1).isFI() &&
605 MI->getOperand(2).isReg() &&
606 MI->getOperand(3).isImm() &&
607 MI->getOperand(2).getReg() == 0 &&
608 MI->getOperand(3).getImm() == 0) {
609 FrameIndex = MI->getOperand(1).getIndex();
610 return MI->getOperand(0).getReg();
615 if (MI->getOperand(1).isFI() &&
616 MI->getOperand(2).isImm() &&
617 MI->getOperand(2).getImm() == 0) {
618 FrameIndex = MI->getOperand(1).getIndex();
619 return MI->getOperand(0).getReg();
624 if (MI->getOperand(1).isFI() &&
625 MI->getOperand(2).isImm() &&
626 MI->getOperand(2).getImm() == 0) {
627 FrameIndex = MI->getOperand(1).getIndex();
628 return MI->getOperand(0).getReg();
637 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
638 MachineBasicBlock::iterator I,
639 unsigned DestReg, unsigned SrcReg,
640 const TargetRegisterClass *DestRC,
641 const TargetRegisterClass *SrcRC) const {
642 DebugLoc DL = DebugLoc::getUnknownLoc();
643 if (I != MBB.end()) DL = I->getDebugLoc();
645 if (DestRC != SrcRC) {
646 if (DestRC->getSize() != SrcRC->getSize())
649 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
650 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
651 if (DestRC->getSize() != 8 && DestRC->getSize() != 16)
655 if (DestRC == ARM::GPRRegisterClass) {
656 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
657 DestReg).addReg(SrcReg)));
658 } else if (DestRC == ARM::SPRRegisterClass) {
659 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVS), DestReg)
661 } else if (DestRC == ARM::DPRRegisterClass) {
662 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVD), DestReg)
664 } else if (DestRC == ARM::DPR_VFP2RegisterClass ||
665 DestRC == ARM::DPR_8RegisterClass ||
666 SrcRC == ARM::DPR_VFP2RegisterClass ||
667 SrcRC == ARM::DPR_8RegisterClass) {
668 // Always use neon reg-reg move if source or dest is NEON-only regclass.
669 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon),
670 DestReg).addReg(SrcReg));
671 } else if (DestRC == ARM::QPRRegisterClass ||
672 DestRC == ARM::QPR_VFP2RegisterClass ||
673 DestRC == ARM::QPR_8RegisterClass) {
674 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ),
675 DestReg).addReg(SrcReg));
683 void ARMBaseInstrInfo::
684 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
685 unsigned SrcReg, bool isKill, int FI,
686 const TargetRegisterClass *RC) const {
687 DebugLoc DL = DebugLoc::getUnknownLoc();
688 if (I != MBB.end()) DL = I->getDebugLoc();
689 MachineFunction &MF = *MBB.getParent();
690 MachineFrameInfo &MFI = *MF.getFrameInfo();
691 unsigned Align = MFI.getObjectAlignment(FI);
693 MachineMemOperand *MMO =
694 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
695 MachineMemOperand::MOStore, 0,
696 MFI.getObjectSize(FI),
699 if (RC == ARM::GPRRegisterClass) {
700 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
701 .addReg(SrcReg, getKillRegState(isKill))
702 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
703 } else if (RC == ARM::DPRRegisterClass ||
704 RC == ARM::DPR_VFP2RegisterClass ||
705 RC == ARM::DPR_8RegisterClass) {
706 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
707 .addReg(SrcReg, getKillRegState(isKill))
708 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
709 } else if (RC == ARM::SPRRegisterClass) {
710 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
711 .addReg(SrcReg, getKillRegState(isKill))
712 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
714 assert((RC == ARM::QPRRegisterClass ||
715 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
716 // FIXME: Neon instructions should support predicates
718 && (getRegisterInfo().needsStackRealignment(MF))) {
719 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
720 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
722 .addReg(SrcReg, getKillRegState(isKill)));
724 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
725 addReg(SrcReg, getKillRegState(isKill))
726 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
731 void ARMBaseInstrInfo::
732 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
733 unsigned DestReg, int FI,
734 const TargetRegisterClass *RC) const {
735 DebugLoc DL = DebugLoc::getUnknownLoc();
736 if (I != MBB.end()) DL = I->getDebugLoc();
737 MachineFunction &MF = *MBB.getParent();
738 MachineFrameInfo &MFI = *MF.getFrameInfo();
739 unsigned Align = MFI.getObjectAlignment(FI);
741 MachineMemOperand *MMO =
742 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
743 MachineMemOperand::MOLoad, 0,
744 MFI.getObjectSize(FI),
747 if (RC == ARM::GPRRegisterClass) {
748 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
749 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
750 } else if (RC == ARM::DPRRegisterClass ||
751 RC == ARM::DPR_VFP2RegisterClass ||
752 RC == ARM::DPR_8RegisterClass) {
753 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
754 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
755 } else if (RC == ARM::SPRRegisterClass) {
756 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
757 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
759 assert((RC == ARM::QPRRegisterClass ||
760 RC == ARM::QPR_VFP2RegisterClass ||
761 RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
763 && (getRegisterInfo().needsStackRealignment(MF))) {
764 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
765 .addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
766 .addMemOperand(MMO));
768 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg)
769 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
774 MachineInstr *ARMBaseInstrInfo::
775 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
776 const SmallVectorImpl<unsigned> &Ops, int FI) const {
777 if (Ops.size() != 1) return NULL;
779 unsigned OpNum = Ops[0];
780 unsigned Opc = MI->getOpcode();
781 MachineInstr *NewMI = NULL;
782 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
783 // If it is updating CPSR, then it cannot be folded.
784 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
786 unsigned Pred = MI->getOperand(2).getImm();
787 unsigned PredReg = MI->getOperand(3).getReg();
788 if (OpNum == 0) { // move -> store
789 unsigned SrcReg = MI->getOperand(1).getReg();
790 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
791 bool isKill = MI->getOperand(1).isKill();
792 bool isUndef = MI->getOperand(1).isUndef();
793 if (Opc == ARM::MOVr)
794 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
796 getKillRegState(isKill) | getUndefRegState(isUndef),
798 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
800 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
802 getKillRegState(isKill) | getUndefRegState(isUndef),
804 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
805 } else { // move -> load
806 unsigned DstReg = MI->getOperand(0).getReg();
807 unsigned DstSubReg = MI->getOperand(0).getSubReg();
808 bool isDead = MI->getOperand(0).isDead();
809 bool isUndef = MI->getOperand(0).isUndef();
810 if (Opc == ARM::MOVr)
811 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
814 getDeadRegState(isDead) |
815 getUndefRegState(isUndef), DstSubReg)
816 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
818 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
821 getDeadRegState(isDead) |
822 getUndefRegState(isUndef), DstSubReg)
823 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
825 } else if (Opc == ARM::tMOVgpr2gpr ||
826 Opc == ARM::tMOVtgpr2gpr ||
827 Opc == ARM::tMOVgpr2tgpr) {
828 if (OpNum == 0) { // move -> store
829 unsigned SrcReg = MI->getOperand(1).getReg();
830 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
831 bool isKill = MI->getOperand(1).isKill();
832 bool isUndef = MI->getOperand(1).isUndef();
833 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
835 getKillRegState(isKill) | getUndefRegState(isUndef),
837 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
838 } else { // move -> load
839 unsigned DstReg = MI->getOperand(0).getReg();
840 unsigned DstSubReg = MI->getOperand(0).getSubReg();
841 bool isDead = MI->getOperand(0).isDead();
842 bool isUndef = MI->getOperand(0).isUndef();
843 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
846 getDeadRegState(isDead) |
847 getUndefRegState(isUndef),
849 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
851 } else if (Opc == ARM::VMOVS) {
852 unsigned Pred = MI->getOperand(2).getImm();
853 unsigned PredReg = MI->getOperand(3).getReg();
854 if (OpNum == 0) { // move -> store
855 unsigned SrcReg = MI->getOperand(1).getReg();
856 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
857 bool isKill = MI->getOperand(1).isKill();
858 bool isUndef = MI->getOperand(1).isUndef();
859 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
860 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
863 .addImm(0).addImm(Pred).addReg(PredReg);
864 } else { // move -> load
865 unsigned DstReg = MI->getOperand(0).getReg();
866 unsigned DstSubReg = MI->getOperand(0).getSubReg();
867 bool isDead = MI->getOperand(0).isDead();
868 bool isUndef = MI->getOperand(0).isUndef();
869 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
872 getDeadRegState(isDead) |
873 getUndefRegState(isUndef),
875 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
878 else if (Opc == ARM::VMOVD) {
879 unsigned Pred = MI->getOperand(2).getImm();
880 unsigned PredReg = MI->getOperand(3).getReg();
881 if (OpNum == 0) { // move -> store
882 unsigned SrcReg = MI->getOperand(1).getReg();
883 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
884 bool isKill = MI->getOperand(1).isKill();
885 bool isUndef = MI->getOperand(1).isUndef();
886 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
888 getKillRegState(isKill) | getUndefRegState(isUndef),
890 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
891 } else { // move -> load
892 unsigned DstReg = MI->getOperand(0).getReg();
893 unsigned DstSubReg = MI->getOperand(0).getSubReg();
894 bool isDead = MI->getOperand(0).isDead();
895 bool isUndef = MI->getOperand(0).isUndef();
896 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
899 getDeadRegState(isDead) |
900 getUndefRegState(isUndef),
902 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
910 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
912 const SmallVectorImpl<unsigned> &Ops,
913 MachineInstr* LoadMI) const {
919 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
920 const SmallVectorImpl<unsigned> &Ops) const {
921 if (Ops.size() != 1) return false;
923 unsigned Opc = MI->getOpcode();
924 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
925 // If it is updating CPSR, then it cannot be folded.
926 return MI->getOperand(4).getReg() != ARM::CPSR ||
927 MI->getOperand(4).isDead();
928 } else if (Opc == ARM::tMOVgpr2gpr ||
929 Opc == ARM::tMOVtgpr2gpr ||
930 Opc == ARM::tMOVgpr2tgpr) {
932 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD) {
934 } else if (Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
935 return false; // FIXME
941 void ARMBaseInstrInfo::
942 reMaterialize(MachineBasicBlock &MBB,
943 MachineBasicBlock::iterator I,
944 unsigned DestReg, unsigned SubIdx,
945 const MachineInstr *Orig,
946 const TargetRegisterInfo *TRI) const {
947 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
948 DestReg = TRI->getSubReg(DestReg, SubIdx);
952 unsigned Opcode = Orig->getOpcode();
955 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
956 MI->getOperand(0).setReg(DestReg);
960 case ARM::tLDRpci_pic:
961 case ARM::t2LDRpci_pic: {
962 MachineFunction &MF = *MBB.getParent();
963 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
964 MachineConstantPool *MCP = MF.getConstantPool();
965 unsigned CPI = Orig->getOperand(1).getIndex();
966 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
967 assert(MCPE.isMachineConstantPoolEntry() &&
968 "Expecting a machine constantpool entry!");
969 ARMConstantPoolValue *ACPV =
970 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
971 unsigned PCLabelId = AFI->createConstPoolEntryUId();
972 ARMConstantPoolValue *NewCPV = 0;
973 if (ACPV->isGlobalValue())
974 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
976 else if (ACPV->isExtSymbol())
977 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
978 ACPV->getSymbol(), PCLabelId, 4);
979 else if (ACPV->isBlockAddress())
980 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
981 ARMCP::CPBlockAddress, 4);
983 llvm_unreachable("Unexpected ARM constantpool value type!!");
984 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
985 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
987 .addConstantPoolIndex(CPI).addImm(PCLabelId);
988 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
993 MachineInstr *NewMI = prior(I);
994 NewMI->getOperand(0).setSubReg(SubIdx);
997 bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
998 const MachineInstr *MI1,
999 const MachineRegisterInfo *MRI) const {
1000 int Opcode = MI0->getOpcode();
1001 if (Opcode == ARM::t2LDRpci ||
1002 Opcode == ARM::t2LDRpci_pic ||
1003 Opcode == ARM::tLDRpci ||
1004 Opcode == ARM::tLDRpci_pic) {
1005 if (MI1->getOpcode() != Opcode)
1007 if (MI0->getNumOperands() != MI1->getNumOperands())
1010 const MachineOperand &MO0 = MI0->getOperand(1);
1011 const MachineOperand &MO1 = MI1->getOperand(1);
1012 if (MO0.getOffset() != MO1.getOffset())
1015 const MachineFunction *MF = MI0->getParent()->getParent();
1016 const MachineConstantPool *MCP = MF->getConstantPool();
1017 int CPI0 = MO0.getIndex();
1018 int CPI1 = MO1.getIndex();
1019 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1020 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1021 ARMConstantPoolValue *ACPV0 =
1022 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1023 ARMConstantPoolValue *ACPV1 =
1024 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1025 return ACPV0->hasSameValue(ACPV1);
1028 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
1031 /// getInstrPredicate - If instruction is predicated, returns its predicate
1032 /// condition, otherwise returns AL. It also returns the condition code
1033 /// register by reference.
1035 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1036 int PIdx = MI->findFirstPredOperandIdx();
1042 PredReg = MI->getOperand(PIdx+1).getReg();
1043 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1047 int llvm::getMatchingCondBranchOpcode(int Opc) {
1050 else if (Opc == ARM::tB)
1052 else if (Opc == ARM::t2B)
1055 llvm_unreachable("Unknown unconditional branch opcode!");
1060 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1061 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1062 unsigned DestReg, unsigned BaseReg, int NumBytes,
1063 ARMCC::CondCodes Pred, unsigned PredReg,
1064 const ARMBaseInstrInfo &TII) {
1065 bool isSub = NumBytes < 0;
1066 if (isSub) NumBytes = -NumBytes;
1069 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1070 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1071 assert(ThisVal && "Didn't extract field correctly");
1073 // We will handle these bits from offset, clear them.
1074 NumBytes &= ~ThisVal;
1076 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1078 // Build the new ADD / SUB.
1079 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1080 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1081 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1082 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1087 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1088 unsigned FrameReg, int &Offset,
1089 const ARMBaseInstrInfo &TII) {
1090 unsigned Opcode = MI.getOpcode();
1091 const TargetInstrDesc &Desc = MI.getDesc();
1092 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1095 // Memory operands in inline assembly always use AddrMode2.
1096 if (Opcode == ARM::INLINEASM)
1097 AddrMode = ARMII::AddrMode2;
1099 if (Opcode == ARM::ADDri) {
1100 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1102 // Turn it into a move.
1103 MI.setDesc(TII.get(ARM::MOVr));
1104 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1105 MI.RemoveOperand(FrameRegIdx+1);
1108 } else if (Offset < 0) {
1111 MI.setDesc(TII.get(ARM::SUBri));
1114 // Common case: small offset, fits into instruction.
1115 if (ARM_AM::getSOImmVal(Offset) != -1) {
1116 // Replace the FrameIndex with sp / fp
1117 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1118 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1123 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1125 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1126 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1128 // We will handle these bits from offset, clear them.
1129 Offset &= ~ThisImmVal;
1131 // Get the properly encoded SOImmVal field.
1132 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1133 "Bit extraction didn't work?");
1134 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1136 unsigned ImmIdx = 0;
1138 unsigned NumBits = 0;
1141 case ARMII::AddrMode2: {
1142 ImmIdx = FrameRegIdx+2;
1143 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1144 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1149 case ARMII::AddrMode3: {
1150 ImmIdx = FrameRegIdx+2;
1151 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1152 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1157 case ARMII::AddrMode4:
1158 case ARMII::AddrMode6:
1159 // Can't fold any offset even if it's zero.
1161 case ARMII::AddrMode5: {
1162 ImmIdx = FrameRegIdx+1;
1163 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1164 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1171 llvm_unreachable("Unsupported addressing mode!");
1175 Offset += InstrOffs * Scale;
1176 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1182 // Attempt to fold address comp. if opcode has offset bits
1184 // Common case: small offset, fits into instruction.
1185 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1186 int ImmedOffset = Offset / Scale;
1187 unsigned Mask = (1 << NumBits) - 1;
1188 if ((unsigned)Offset <= Mask * Scale) {
1189 // Replace the FrameIndex with sp
1190 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1192 ImmedOffset |= 1 << NumBits;
1193 ImmOp.ChangeToImmediate(ImmedOffset);
1198 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1199 ImmedOffset = ImmedOffset & Mask;
1201 ImmedOffset |= 1 << NumBits;
1202 ImmOp.ChangeToImmediate(ImmedOffset);
1203 Offset &= ~(Mask*Scale);
1207 Offset = (isSub) ? -Offset : Offset;