1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Handle register classes that require multiple instructions.
684 unsigned BeginIdx = 0;
685 unsigned SubRegs = 0;
686 unsigned Spacing = 1;
688 // Use VORRq when possible.
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
693 // Fall back to VMOVD.
694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
709 const TargetRegisterInfo *TRI = &getRegisterInfo();
710 MachineInstrBuilder Mov;
711 for (unsigned i = 0; i != SubRegs; ++i) {
712 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
713 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
714 assert(Dst && Src && "Bad sub-register");
715 Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
717 // VORR takes two source operands.
718 if (Opc == ARM::VORRq)
721 // Add implicit super-register defs and kills to the last instruction.
722 Mov->addRegisterDefined(DestReg, TRI);
724 Mov->addRegisterKilled(SrcReg, TRI);
728 llvm_unreachable("Impossible reg-to-reg copy");
732 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
733 unsigned Reg, unsigned SubIdx, unsigned State,
734 const TargetRegisterInfo *TRI) {
736 return MIB.addReg(Reg, State);
738 if (TargetRegisterInfo::isPhysicalRegister(Reg))
739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
740 return MIB.addReg(Reg, State, SubIdx);
743 void ARMBaseInstrInfo::
744 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
745 unsigned SrcReg, bool isKill, int FI,
746 const TargetRegisterClass *RC,
747 const TargetRegisterInfo *TRI) const {
749 if (I != MBB.end()) DL = I->getDebugLoc();
750 MachineFunction &MF = *MBB.getParent();
751 MachineFrameInfo &MFI = *MF.getFrameInfo();
752 unsigned Align = MFI.getObjectAlignment(FI);
754 MachineMemOperand *MMO =
755 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
756 MachineMemOperand::MOStore,
757 MFI.getObjectSize(FI),
760 switch (RC->getSize()) {
762 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
764 .addReg(SrcReg, getKillRegState(isKill))
765 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
766 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
768 .addReg(SrcReg, getKillRegState(isKill))
769 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
771 llvm_unreachable("Unknown reg class!");
774 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
775 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
776 .addReg(SrcReg, getKillRegState(isKill))
777 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
779 llvm_unreachable("Unknown reg class!");
782 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
783 // Use aligned spills if the stack can be realigned.
784 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
785 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
786 .addFrameIndex(FI).addImm(16)
787 .addReg(SrcReg, getKillRegState(isKill))
788 .addMemOperand(MMO));
790 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
791 .addReg(SrcReg, getKillRegState(isKill))
793 .addMemOperand(MMO));
796 llvm_unreachable("Unknown reg class!");
799 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
800 // Use aligned spills if the stack can be realigned.
801 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
802 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
803 .addFrameIndex(FI).addImm(16)
804 .addReg(SrcReg, getKillRegState(isKill))
805 .addMemOperand(MMO));
807 MachineInstrBuilder MIB =
808 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
813 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
816 llvm_unreachable("Unknown reg class!");
819 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
820 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
821 // FIXME: It's possible to only store part of the QQ register if the
822 // spilled def has a sub-register index.
823 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
824 .addFrameIndex(FI).addImm(16)
825 .addReg(SrcReg, getKillRegState(isKill))
826 .addMemOperand(MMO));
828 MachineInstrBuilder MIB =
829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
832 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
833 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
834 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
835 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
838 llvm_unreachable("Unknown reg class!");
841 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
842 MachineInstrBuilder MIB =
843 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
846 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
851 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
852 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
853 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
855 llvm_unreachable("Unknown reg class!");
858 llvm_unreachable("Unknown reg class!");
863 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
864 int &FrameIndex) const {
865 switch (MI->getOpcode()) {
868 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
869 if (MI->getOperand(1).isFI() &&
870 MI->getOperand(2).isReg() &&
871 MI->getOperand(3).isImm() &&
872 MI->getOperand(2).getReg() == 0 &&
873 MI->getOperand(3).getImm() == 0) {
874 FrameIndex = MI->getOperand(1).getIndex();
875 return MI->getOperand(0).getReg();
883 if (MI->getOperand(1).isFI() &&
884 MI->getOperand(2).isImm() &&
885 MI->getOperand(2).getImm() == 0) {
886 FrameIndex = MI->getOperand(1).getIndex();
887 return MI->getOperand(0).getReg();
891 case ARM::VST1d64TPseudo:
892 case ARM::VST1d64QPseudo:
893 if (MI->getOperand(0).isFI() &&
894 MI->getOperand(2).getSubReg() == 0) {
895 FrameIndex = MI->getOperand(0).getIndex();
896 return MI->getOperand(2).getReg();
900 if (MI->getOperand(1).isFI() &&
901 MI->getOperand(0).getSubReg() == 0) {
902 FrameIndex = MI->getOperand(1).getIndex();
903 return MI->getOperand(0).getReg();
911 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
912 int &FrameIndex) const {
913 const MachineMemOperand *Dummy;
914 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
917 void ARMBaseInstrInfo::
918 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
919 unsigned DestReg, int FI,
920 const TargetRegisterClass *RC,
921 const TargetRegisterInfo *TRI) const {
923 if (I != MBB.end()) DL = I->getDebugLoc();
924 MachineFunction &MF = *MBB.getParent();
925 MachineFrameInfo &MFI = *MF.getFrameInfo();
926 unsigned Align = MFI.getObjectAlignment(FI);
927 MachineMemOperand *MMO =
928 MF.getMachineMemOperand(
929 MachinePointerInfo::getFixedStack(FI),
930 MachineMemOperand::MOLoad,
931 MFI.getObjectSize(FI),
934 switch (RC->getSize()) {
936 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
937 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
938 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
940 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
941 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
942 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
944 llvm_unreachable("Unknown reg class!");
947 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
948 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
949 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
951 llvm_unreachable("Unknown reg class!");
954 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
955 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
956 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
957 .addFrameIndex(FI).addImm(16)
958 .addMemOperand(MMO));
960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
962 .addMemOperand(MMO));
965 llvm_unreachable("Unknown reg class!");
968 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
969 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
970 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
971 .addFrameIndex(FI).addImm(16)
972 .addMemOperand(MMO));
974 MachineInstrBuilder MIB =
975 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
977 .addMemOperand(MMO));
978 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
979 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
980 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
981 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
982 MIB.addReg(DestReg, RegState::ImplicitDefine);
985 llvm_unreachable("Unknown reg class!");
988 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
989 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
990 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
991 .addFrameIndex(FI).addImm(16)
992 .addMemOperand(MMO));
994 MachineInstrBuilder MIB =
995 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
998 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
999 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1000 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1001 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1002 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1003 MIB.addReg(DestReg, RegState::ImplicitDefine);
1006 llvm_unreachable("Unknown reg class!");
1009 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1010 MachineInstrBuilder MIB =
1011 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1013 .addMemOperand(MMO);
1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1018 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1019 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1020 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1021 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1022 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1023 MIB.addReg(DestReg, RegState::ImplicitDefine);
1025 llvm_unreachable("Unknown reg class!");
1028 llvm_unreachable("Unknown regclass!");
1033 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1034 int &FrameIndex) const {
1035 switch (MI->getOpcode()) {
1038 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1039 if (MI->getOperand(1).isFI() &&
1040 MI->getOperand(2).isReg() &&
1041 MI->getOperand(3).isImm() &&
1042 MI->getOperand(2).getReg() == 0 &&
1043 MI->getOperand(3).getImm() == 0) {
1044 FrameIndex = MI->getOperand(1).getIndex();
1045 return MI->getOperand(0).getReg();
1053 if (MI->getOperand(1).isFI() &&
1054 MI->getOperand(2).isImm() &&
1055 MI->getOperand(2).getImm() == 0) {
1056 FrameIndex = MI->getOperand(1).getIndex();
1057 return MI->getOperand(0).getReg();
1061 case ARM::VLD1d64TPseudo:
1062 case ARM::VLD1d64QPseudo:
1063 if (MI->getOperand(1).isFI() &&
1064 MI->getOperand(0).getSubReg() == 0) {
1065 FrameIndex = MI->getOperand(1).getIndex();
1066 return MI->getOperand(0).getReg();
1070 if (MI->getOperand(1).isFI() &&
1071 MI->getOperand(0).getSubReg() == 0) {
1072 FrameIndex = MI->getOperand(1).getIndex();
1073 return MI->getOperand(0).getReg();
1081 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1082 int &FrameIndex) const {
1083 const MachineMemOperand *Dummy;
1084 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1087 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1088 // This hook gets to expand COPY instructions before they become
1089 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1090 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1091 // changed into a VORR that can go down the NEON pipeline.
1092 if (!WidenVMOVS || !MI->isCopy())
1095 // Look for a copy between even S-registers. That is where we keep floats
1096 // when using NEON v2f32 instructions for f32 arithmetic.
1097 unsigned DstRegS = MI->getOperand(0).getReg();
1098 unsigned SrcRegS = MI->getOperand(1).getReg();
1099 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1102 const TargetRegisterInfo *TRI = &getRegisterInfo();
1103 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1105 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1107 if (!DstRegD || !SrcRegD)
1110 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1111 // legal if the COPY already defines the full DstRegD, and it isn't a
1112 // sub-register insertion.
1113 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1116 // A dead copy shouldn't show up here, but reject it just in case.
1117 if (MI->getOperand(0).isDead())
1120 // All clear, widen the COPY.
1121 DEBUG(dbgs() << "widening: " << *MI);
1123 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1124 // or some other super-register.
1125 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1126 if (ImpDefIdx != -1)
1127 MI->RemoveOperand(ImpDefIdx);
1129 // Change the opcode and operands.
1130 MI->setDesc(get(ARM::VMOVD));
1131 MI->getOperand(0).setReg(DstRegD);
1132 MI->getOperand(1).setReg(SrcRegD);
1133 AddDefaultPred(MachineInstrBuilder(MI));
1135 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1136 // register scavenger and machine verifier, so we need to indicate that we
1137 // are reading an undefined value from SrcRegD, but a proper value from
1139 MI->getOperand(1).setIsUndef();
1140 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1142 // SrcRegD may actually contain an unrelated value in the ssub_1
1143 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1144 if (MI->getOperand(1).isKill()) {
1145 MI->getOperand(1).setIsKill(false);
1146 MI->addRegisterKilled(SrcRegS, TRI, true);
1149 DEBUG(dbgs() << "replaced by: " << *MI);
1154 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1155 int FrameIx, uint64_t Offset,
1156 const MDNode *MDPtr,
1157 DebugLoc DL) const {
1158 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1159 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1163 /// Create a copy of a const pool value. Update CPI to the new index and return
1165 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1166 MachineConstantPool *MCP = MF.getConstantPool();
1167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1169 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1170 assert(MCPE.isMachineConstantPoolEntry() &&
1171 "Expecting a machine constantpool entry!");
1172 ARMConstantPoolValue *ACPV =
1173 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1175 unsigned PCLabelId = AFI->createPICLabelUId();
1176 ARMConstantPoolValue *NewCPV = 0;
1177 // FIXME: The below assumes PIC relocation model and that the function
1178 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1179 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1180 // instructions, so that's probably OK, but is PIC always correct when
1182 if (ACPV->isGlobalValue())
1183 NewCPV = ARMConstantPoolConstant::
1184 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1186 else if (ACPV->isExtSymbol())
1187 NewCPV = ARMConstantPoolSymbol::
1188 Create(MF.getFunction()->getContext(),
1189 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1190 else if (ACPV->isBlockAddress())
1191 NewCPV = ARMConstantPoolConstant::
1192 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1193 ARMCP::CPBlockAddress, 4);
1194 else if (ACPV->isLSDA())
1195 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1197 else if (ACPV->isMachineBasicBlock())
1198 NewCPV = ARMConstantPoolMBB::
1199 Create(MF.getFunction()->getContext(),
1200 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1202 llvm_unreachable("Unexpected ARM constantpool value type!!");
1203 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1207 void ARMBaseInstrInfo::
1208 reMaterialize(MachineBasicBlock &MBB,
1209 MachineBasicBlock::iterator I,
1210 unsigned DestReg, unsigned SubIdx,
1211 const MachineInstr *Orig,
1212 const TargetRegisterInfo &TRI) const {
1213 unsigned Opcode = Orig->getOpcode();
1216 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1217 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1221 case ARM::tLDRpci_pic:
1222 case ARM::t2LDRpci_pic: {
1223 MachineFunction &MF = *MBB.getParent();
1224 unsigned CPI = Orig->getOperand(1).getIndex();
1225 unsigned PCLabelId = duplicateCPV(MF, CPI);
1226 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1228 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1229 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1236 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1237 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1238 switch(Orig->getOpcode()) {
1239 case ARM::tLDRpci_pic:
1240 case ARM::t2LDRpci_pic: {
1241 unsigned CPI = Orig->getOperand(1).getIndex();
1242 unsigned PCLabelId = duplicateCPV(MF, CPI);
1243 Orig->getOperand(1).setIndex(CPI);
1244 Orig->getOperand(2).setImm(PCLabelId);
1251 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1252 const MachineInstr *MI1,
1253 const MachineRegisterInfo *MRI) const {
1254 int Opcode = MI0->getOpcode();
1255 if (Opcode == ARM::t2LDRpci ||
1256 Opcode == ARM::t2LDRpci_pic ||
1257 Opcode == ARM::tLDRpci ||
1258 Opcode == ARM::tLDRpci_pic ||
1259 Opcode == ARM::MOV_ga_dyn ||
1260 Opcode == ARM::MOV_ga_pcrel ||
1261 Opcode == ARM::MOV_ga_pcrel_ldr ||
1262 Opcode == ARM::t2MOV_ga_dyn ||
1263 Opcode == ARM::t2MOV_ga_pcrel) {
1264 if (MI1->getOpcode() != Opcode)
1266 if (MI0->getNumOperands() != MI1->getNumOperands())
1269 const MachineOperand &MO0 = MI0->getOperand(1);
1270 const MachineOperand &MO1 = MI1->getOperand(1);
1271 if (MO0.getOffset() != MO1.getOffset())
1274 if (Opcode == ARM::MOV_ga_dyn ||
1275 Opcode == ARM::MOV_ga_pcrel ||
1276 Opcode == ARM::MOV_ga_pcrel_ldr ||
1277 Opcode == ARM::t2MOV_ga_dyn ||
1278 Opcode == ARM::t2MOV_ga_pcrel)
1279 // Ignore the PC labels.
1280 return MO0.getGlobal() == MO1.getGlobal();
1282 const MachineFunction *MF = MI0->getParent()->getParent();
1283 const MachineConstantPool *MCP = MF->getConstantPool();
1284 int CPI0 = MO0.getIndex();
1285 int CPI1 = MO1.getIndex();
1286 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1287 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1288 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1289 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1290 if (isARMCP0 && isARMCP1) {
1291 ARMConstantPoolValue *ACPV0 =
1292 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1293 ARMConstantPoolValue *ACPV1 =
1294 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1295 return ACPV0->hasSameValue(ACPV1);
1296 } else if (!isARMCP0 && !isARMCP1) {
1297 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1300 } else if (Opcode == ARM::PICLDR) {
1301 if (MI1->getOpcode() != Opcode)
1303 if (MI0->getNumOperands() != MI1->getNumOperands())
1306 unsigned Addr0 = MI0->getOperand(1).getReg();
1307 unsigned Addr1 = MI1->getOperand(1).getReg();
1308 if (Addr0 != Addr1) {
1310 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1311 !TargetRegisterInfo::isVirtualRegister(Addr1))
1314 // This assumes SSA form.
1315 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1316 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1317 // Check if the loaded value, e.g. a constantpool of a global address, are
1319 if (!produceSameValue(Def0, Def1, MRI))
1323 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1324 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1325 const MachineOperand &MO0 = MI0->getOperand(i);
1326 const MachineOperand &MO1 = MI1->getOperand(i);
1327 if (!MO0.isIdenticalTo(MO1))
1333 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1336 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1337 /// determine if two loads are loading from the same base address. It should
1338 /// only return true if the base pointers are the same and the only differences
1339 /// between the two addresses is the offset. It also returns the offsets by
1341 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1343 int64_t &Offset2) const {
1344 // Don't worry about Thumb: just ARM and Thumb2.
1345 if (Subtarget.isThumb1Only()) return false;
1347 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1350 switch (Load1->getMachineOpcode()) {
1363 case ARM::t2LDRSHi8:
1365 case ARM::t2LDRSHi12:
1369 switch (Load2->getMachineOpcode()) {
1382 case ARM::t2LDRSHi8:
1384 case ARM::t2LDRSHi12:
1388 // Check if base addresses and chain operands match.
1389 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1390 Load1->getOperand(4) != Load2->getOperand(4))
1393 // Index should be Reg0.
1394 if (Load1->getOperand(3) != Load2->getOperand(3))
1397 // Determine the offsets.
1398 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1399 isa<ConstantSDNode>(Load2->getOperand(1))) {
1400 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1401 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1408 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1409 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1410 /// be scheduled togther. On some targets if two loads are loading from
1411 /// addresses in the same cache line, it's better if they are scheduled
1412 /// together. This function takes two integers that represent the load offsets
1413 /// from the common base address. It returns true if it decides it's desirable
1414 /// to schedule the two loads together. "NumLoads" is the number of loads that
1415 /// have already been scheduled after Load1.
1416 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1417 int64_t Offset1, int64_t Offset2,
1418 unsigned NumLoads) const {
1419 // Don't worry about Thumb: just ARM and Thumb2.
1420 if (Subtarget.isThumb1Only()) return false;
1422 assert(Offset2 > Offset1);
1424 if ((Offset2 - Offset1) / 8 > 64)
1427 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1428 return false; // FIXME: overly conservative?
1430 // Four loads in a row should be sufficient.
1437 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1438 const MachineBasicBlock *MBB,
1439 const MachineFunction &MF) const {
1440 // Debug info is never a scheduling boundary. It's necessary to be explicit
1441 // due to the special treatment of IT instructions below, otherwise a
1442 // dbg_value followed by an IT will result in the IT instruction being
1443 // considered a scheduling hazard, which is wrong. It should be the actual
1444 // instruction preceding the dbg_value instruction(s), just like it is
1445 // when debug info is not present.
1446 if (MI->isDebugValue())
1449 // Terminators and labels can't be scheduled around.
1450 if (MI->isTerminator() || MI->isLabel())
1453 // Treat the start of the IT block as a scheduling boundary, but schedule
1454 // t2IT along with all instructions following it.
1455 // FIXME: This is a big hammer. But the alternative is to add all potential
1456 // true and anti dependencies to IT block instructions as implicit operands
1457 // to the t2IT instruction. The added compile time and complexity does not
1459 MachineBasicBlock::const_iterator I = MI;
1460 // Make sure to skip any dbg_value instructions
1461 while (++I != MBB->end() && I->isDebugValue())
1463 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1466 // Don't attempt to schedule around any instruction that defines
1467 // a stack-oriented pointer, as it's unlikely to be profitable. This
1468 // saves compile time, because it doesn't require every single
1469 // stack slot reference to depend on the instruction that does the
1471 // Calls don't actually change the stack pointer, even if they have imp-defs.
1472 // No ARM calling conventions change the stack pointer. (X86 calling
1473 // conventions sometimes do).
1474 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1480 bool ARMBaseInstrInfo::
1481 isProfitableToIfCvt(MachineBasicBlock &MBB,
1482 unsigned NumCycles, unsigned ExtraPredCycles,
1483 const BranchProbability &Probability) const {
1487 // Attempt to estimate the relative costs of predication versus branching.
1488 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1489 UnpredCost /= Probability.getDenominator();
1490 UnpredCost += 1; // The branch itself
1491 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1493 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1496 bool ARMBaseInstrInfo::
1497 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1498 unsigned TCycles, unsigned TExtra,
1499 MachineBasicBlock &FMBB,
1500 unsigned FCycles, unsigned FExtra,
1501 const BranchProbability &Probability) const {
1502 if (!TCycles || !FCycles)
1505 // Attempt to estimate the relative costs of predication versus branching.
1506 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1507 TUnpredCost /= Probability.getDenominator();
1509 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1510 unsigned FUnpredCost = Comp * FCycles;
1511 FUnpredCost /= Probability.getDenominator();
1513 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1514 UnpredCost += 1; // The branch itself
1515 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1517 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1520 /// getInstrPredicate - If instruction is predicated, returns its predicate
1521 /// condition, otherwise returns AL. It also returns the condition code
1522 /// register by reference.
1524 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1525 int PIdx = MI->findFirstPredOperandIdx();
1531 PredReg = MI->getOperand(PIdx+1).getReg();
1532 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1536 int llvm::getMatchingCondBranchOpcode(int Opc) {
1541 if (Opc == ARM::t2B)
1544 llvm_unreachable("Unknown unconditional branch opcode!");
1547 /// commuteInstruction - Handle commutable instructions.
1549 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1550 switch (MI->getOpcode()) {
1552 case ARM::t2MOVCCr: {
1553 // MOVCC can be commuted by inverting the condition.
1554 unsigned PredReg = 0;
1555 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1556 // MOVCC AL can't be inverted. Shouldn't happen.
1557 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1559 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1562 // After swapping the MOVCC operands, also invert the condition.
1563 MI->getOperand(MI->findFirstPredOperandIdx())
1564 .setImm(ARMCC::getOppositeCondition(CC));
1568 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1571 /// Identify instructions that can be folded into a MOVCC instruction, and
1572 /// return the corresponding opcode for the predicated pseudo-instruction.
1573 static unsigned canFoldIntoMOVCC(unsigned Reg, MachineInstr *&MI,
1574 const MachineRegisterInfo &MRI) {
1575 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1577 if (!MRI.hasOneNonDBGUse(Reg))
1579 MI = MRI.getVRegDef(Reg);
1582 // Check if MI has any non-dead defs or physreg uses. This also detects
1583 // predicated instructions which will be reading CPSR.
1584 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1585 const MachineOperand &MO = MI->getOperand(i);
1586 // Reject frame index operands, PEI can't handle the predicated pseudos.
1587 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1591 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1593 if (MO.isDef() && !MO.isDead())
1596 switch (MI->getOpcode()) {
1598 case ARM::ANDri: return ARM::ANDCCri;
1599 case ARM::ANDrr: return ARM::ANDCCrr;
1600 case ARM::ANDrsi: return ARM::ANDCCrsi;
1601 case ARM::ANDrsr: return ARM::ANDCCrsr;
1602 case ARM::t2ANDri: return ARM::t2ANDCCri;
1603 case ARM::t2ANDrr: return ARM::t2ANDCCrr;
1604 case ARM::t2ANDrs: return ARM::t2ANDCCrs;
1605 case ARM::EORri: return ARM::EORCCri;
1606 case ARM::EORrr: return ARM::EORCCrr;
1607 case ARM::EORrsi: return ARM::EORCCrsi;
1608 case ARM::EORrsr: return ARM::EORCCrsr;
1609 case ARM::t2EORri: return ARM::t2EORCCri;
1610 case ARM::t2EORrr: return ARM::t2EORCCrr;
1611 case ARM::t2EORrs: return ARM::t2EORCCrs;
1612 case ARM::ORRri: return ARM::ORRCCri;
1613 case ARM::ORRrr: return ARM::ORRCCrr;
1614 case ARM::ORRrsi: return ARM::ORRCCrsi;
1615 case ARM::ORRrsr: return ARM::ORRCCrsr;
1616 case ARM::t2ORRri: return ARM::t2ORRCCri;
1617 case ARM::t2ORRrr: return ARM::t2ORRCCrr;
1618 case ARM::t2ORRrs: return ARM::t2ORRCCrs;
1621 case ARM::ADDri: return ARM::ADDCCri;
1622 case ARM::ADDrr: return ARM::ADDCCrr;
1623 case ARM::ADDrsi: return ARM::ADDCCrsi;
1624 case ARM::ADDrsr: return ARM::ADDCCrsr;
1625 case ARM::SUBri: return ARM::SUBCCri;
1626 case ARM::SUBrr: return ARM::SUBCCrr;
1627 case ARM::SUBrsi: return ARM::SUBCCrsi;
1628 case ARM::SUBrsr: return ARM::SUBCCrsr;
1631 case ARM::t2ADDri: return ARM::t2ADDCCri;
1632 case ARM::t2ADDri12: return ARM::t2ADDCCri12;
1633 case ARM::t2ADDrr: return ARM::t2ADDCCrr;
1634 case ARM::t2ADDrs: return ARM::t2ADDCCrs;
1635 case ARM::t2SUBri: return ARM::t2SUBCCri;
1636 case ARM::t2SUBri12: return ARM::t2SUBCCri12;
1637 case ARM::t2SUBrr: return ARM::t2SUBCCrr;
1638 case ARM::t2SUBrs: return ARM::t2SUBCCrs;
1642 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1643 SmallVectorImpl<MachineOperand> &Cond,
1644 unsigned &TrueOp, unsigned &FalseOp,
1645 bool &Optimizable) const {
1646 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1647 "Unknown select instruction");
1652 // 3: Condition code.
1656 Cond.push_back(MI->getOperand(3));
1657 Cond.push_back(MI->getOperand(4));
1658 // We can always fold a def.
1663 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1664 bool PreferFalse) const {
1665 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1666 "Unknown select instruction");
1667 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1668 MachineInstr *DefMI = 0;
1669 unsigned Opc = canFoldIntoMOVCC(MI->getOperand(2).getReg(), DefMI, MRI);
1672 Opc = canFoldIntoMOVCC(MI->getOperand(1).getReg(), DefMI, MRI);
1676 // Create a new predicated version of DefMI.
1677 // Rfalse is the first use.
1678 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1679 get(Opc), MI->getOperand(0).getReg())
1680 .addOperand(MI->getOperand(Invert ? 2 : 1));
1682 // Copy all the DefMI operands, excluding its (null) predicate.
1683 const MCInstrDesc &DefDesc = DefMI->getDesc();
1684 for (unsigned i = 1, e = DefDesc.getNumOperands();
1685 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1686 NewMI.addOperand(DefMI->getOperand(i));
1688 unsigned CondCode = MI->getOperand(3).getImm();
1690 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1692 NewMI.addImm(CondCode);
1693 NewMI.addOperand(MI->getOperand(4));
1695 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1696 if (NewMI->hasOptionalDef())
1697 AddDefaultCC(NewMI);
1699 // The caller will erase MI, but not DefMI.
1700 DefMI->eraseFromParent();
1704 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1705 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1708 /// This will go away once we can teach tblgen how to set the optional CPSR def
1710 struct AddSubFlagsOpcodePair {
1712 uint16_t MachineOpc;
1715 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1716 {ARM::ADDSri, ARM::ADDri},
1717 {ARM::ADDSrr, ARM::ADDrr},
1718 {ARM::ADDSrsi, ARM::ADDrsi},
1719 {ARM::ADDSrsr, ARM::ADDrsr},
1721 {ARM::SUBSri, ARM::SUBri},
1722 {ARM::SUBSrr, ARM::SUBrr},
1723 {ARM::SUBSrsi, ARM::SUBrsi},
1724 {ARM::SUBSrsr, ARM::SUBrsr},
1726 {ARM::RSBSri, ARM::RSBri},
1727 {ARM::RSBSrsi, ARM::RSBrsi},
1728 {ARM::RSBSrsr, ARM::RSBrsr},
1730 {ARM::t2ADDSri, ARM::t2ADDri},
1731 {ARM::t2ADDSrr, ARM::t2ADDrr},
1732 {ARM::t2ADDSrs, ARM::t2ADDrs},
1734 {ARM::t2SUBSri, ARM::t2SUBri},
1735 {ARM::t2SUBSrr, ARM::t2SUBrr},
1736 {ARM::t2SUBSrs, ARM::t2SUBrs},
1738 {ARM::t2RSBSri, ARM::t2RSBri},
1739 {ARM::t2RSBSrs, ARM::t2RSBrs},
1742 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1743 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1744 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1745 return AddSubFlagsOpcodeMap[i].MachineOpc;
1749 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1750 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1751 unsigned DestReg, unsigned BaseReg, int NumBytes,
1752 ARMCC::CondCodes Pred, unsigned PredReg,
1753 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1754 bool isSub = NumBytes < 0;
1755 if (isSub) NumBytes = -NumBytes;
1758 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1759 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1760 assert(ThisVal && "Didn't extract field correctly");
1762 // We will handle these bits from offset, clear them.
1763 NumBytes &= ~ThisVal;
1765 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1767 // Build the new ADD / SUB.
1768 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1769 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1770 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1771 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1772 .setMIFlags(MIFlags);
1777 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1778 unsigned FrameReg, int &Offset,
1779 const ARMBaseInstrInfo &TII) {
1780 unsigned Opcode = MI.getOpcode();
1781 const MCInstrDesc &Desc = MI.getDesc();
1782 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1785 // Memory operands in inline assembly always use AddrMode2.
1786 if (Opcode == ARM::INLINEASM)
1787 AddrMode = ARMII::AddrMode2;
1789 if (Opcode == ARM::ADDri) {
1790 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1792 // Turn it into a move.
1793 MI.setDesc(TII.get(ARM::MOVr));
1794 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1795 MI.RemoveOperand(FrameRegIdx+1);
1798 } else if (Offset < 0) {
1801 MI.setDesc(TII.get(ARM::SUBri));
1804 // Common case: small offset, fits into instruction.
1805 if (ARM_AM::getSOImmVal(Offset) != -1) {
1806 // Replace the FrameIndex with sp / fp
1807 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1808 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1813 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1815 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1816 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1818 // We will handle these bits from offset, clear them.
1819 Offset &= ~ThisImmVal;
1821 // Get the properly encoded SOImmVal field.
1822 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1823 "Bit extraction didn't work?");
1824 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1826 unsigned ImmIdx = 0;
1828 unsigned NumBits = 0;
1831 case ARMII::AddrMode_i12: {
1832 ImmIdx = FrameRegIdx + 1;
1833 InstrOffs = MI.getOperand(ImmIdx).getImm();
1837 case ARMII::AddrMode2: {
1838 ImmIdx = FrameRegIdx+2;
1839 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1840 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1845 case ARMII::AddrMode3: {
1846 ImmIdx = FrameRegIdx+2;
1847 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1848 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1853 case ARMII::AddrMode4:
1854 case ARMII::AddrMode6:
1855 // Can't fold any offset even if it's zero.
1857 case ARMII::AddrMode5: {
1858 ImmIdx = FrameRegIdx+1;
1859 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1860 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1867 llvm_unreachable("Unsupported addressing mode!");
1870 Offset += InstrOffs * Scale;
1871 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1877 // Attempt to fold address comp. if opcode has offset bits
1879 // Common case: small offset, fits into instruction.
1880 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1881 int ImmedOffset = Offset / Scale;
1882 unsigned Mask = (1 << NumBits) - 1;
1883 if ((unsigned)Offset <= Mask * Scale) {
1884 // Replace the FrameIndex with sp
1885 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1886 // FIXME: When addrmode2 goes away, this will simplify (like the
1887 // T2 version), as the LDR.i12 versions don't need the encoding
1888 // tricks for the offset value.
1890 if (AddrMode == ARMII::AddrMode_i12)
1891 ImmedOffset = -ImmedOffset;
1893 ImmedOffset |= 1 << NumBits;
1895 ImmOp.ChangeToImmediate(ImmedOffset);
1900 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1901 ImmedOffset = ImmedOffset & Mask;
1903 if (AddrMode == ARMII::AddrMode_i12)
1904 ImmedOffset = -ImmedOffset;
1906 ImmedOffset |= 1 << NumBits;
1908 ImmOp.ChangeToImmediate(ImmedOffset);
1909 Offset &= ~(Mask*Scale);
1913 Offset = (isSub) ? -Offset : Offset;
1917 /// analyzeCompare - For a comparison instruction, return the source registers
1918 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1919 /// compares against in CmpValue. Return true if the comparison instruction
1920 /// can be analyzed.
1921 bool ARMBaseInstrInfo::
1922 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1923 int &CmpMask, int &CmpValue) const {
1924 switch (MI->getOpcode()) {
1928 SrcReg = MI->getOperand(0).getReg();
1931 CmpValue = MI->getOperand(1).getImm();
1935 SrcReg = MI->getOperand(0).getReg();
1936 SrcReg2 = MI->getOperand(1).getReg();
1942 SrcReg = MI->getOperand(0).getReg();
1944 CmpMask = MI->getOperand(1).getImm();
1952 /// isSuitableForMask - Identify a suitable 'and' instruction that
1953 /// operates on the given source register and applies the same mask
1954 /// as a 'tst' instruction. Provide a limited look-through for copies.
1955 /// When successful, MI will hold the found instruction.
1956 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1957 int CmpMask, bool CommonUse) {
1958 switch (MI->getOpcode()) {
1961 if (CmpMask != MI->getOperand(2).getImm())
1963 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1967 // Walk down one instruction which is potentially an 'and'.
1968 const MachineInstr &Copy = *MI;
1969 MachineBasicBlock::iterator AND(
1970 llvm::next(MachineBasicBlock::iterator(MI)));
1971 if (AND == MI->getParent()->end()) return false;
1973 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1981 /// getSwappedCondition - assume the flags are set by MI(a,b), return
1982 /// the condition code if we modify the instructions such that flags are
1984 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
1986 default: return ARMCC::AL;
1987 case ARMCC::EQ: return ARMCC::EQ;
1988 case ARMCC::NE: return ARMCC::NE;
1989 case ARMCC::HS: return ARMCC::LS;
1990 case ARMCC::LO: return ARMCC::HI;
1991 case ARMCC::HI: return ARMCC::LO;
1992 case ARMCC::LS: return ARMCC::HS;
1993 case ARMCC::GE: return ARMCC::LE;
1994 case ARMCC::LT: return ARMCC::GT;
1995 case ARMCC::GT: return ARMCC::LT;
1996 case ARMCC::LE: return ARMCC::GE;
2000 /// isRedundantFlagInstr - check whether the first instruction, whose only
2001 /// purpose is to update flags, can be made redundant.
2002 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2003 /// CMPri can be made redundant by SUBri if the operands are the same.
2004 /// This function can be extended later on.
2005 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2006 unsigned SrcReg2, int ImmValue,
2008 if ((CmpI->getOpcode() == ARM::CMPrr ||
2009 CmpI->getOpcode() == ARM::t2CMPrr) &&
2010 (OI->getOpcode() == ARM::SUBrr ||
2011 OI->getOpcode() == ARM::t2SUBrr) &&
2012 ((OI->getOperand(1).getReg() == SrcReg &&
2013 OI->getOperand(2).getReg() == SrcReg2) ||
2014 (OI->getOperand(1).getReg() == SrcReg2 &&
2015 OI->getOperand(2).getReg() == SrcReg)))
2018 if ((CmpI->getOpcode() == ARM::CMPri ||
2019 CmpI->getOpcode() == ARM::t2CMPri) &&
2020 (OI->getOpcode() == ARM::SUBri ||
2021 OI->getOpcode() == ARM::t2SUBri) &&
2022 OI->getOperand(1).getReg() == SrcReg &&
2023 OI->getOperand(2).getImm() == ImmValue)
2028 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2029 /// comparison into one that sets the zero bit in the flags register;
2030 /// Remove a redundant Compare instruction if an earlier instruction can set the
2031 /// flags in the same way as Compare.
2032 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2033 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2034 /// condition code of instructions which use the flags.
2035 bool ARMBaseInstrInfo::
2036 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2037 int CmpMask, int CmpValue,
2038 const MachineRegisterInfo *MRI) const {
2039 // Get the unique definition of SrcReg.
2040 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2041 if (!MI) return false;
2043 // Masked compares sometimes use the same register as the corresponding 'and'.
2044 if (CmpMask != ~0) {
2045 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
2047 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2048 UE = MRI->use_end(); UI != UE; ++UI) {
2049 if (UI->getParent() != CmpInstr->getParent()) continue;
2050 MachineInstr *PotentialAND = &*UI;
2051 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
2056 if (!MI) return false;
2060 // Get ready to iterate backward from CmpInstr.
2061 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2062 B = CmpInstr->getParent()->begin();
2064 // Early exit if CmpInstr is at the beginning of the BB.
2065 if (I == B) return false;
2067 // There are two possible candidates which can be changed to set CPSR:
2068 // One is MI, the other is a SUB instruction.
2069 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2070 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2071 MachineInstr *Sub = NULL;
2073 // MI is not a candidate for CMPrr.
2075 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2076 // Conservatively refuse to convert an instruction which isn't in the same
2077 // BB as the comparison.
2078 // For CMPri, we need to check Sub, thus we can't return here.
2079 if (CmpInstr->getOpcode() == ARM::CMPri ||
2080 CmpInstr->getOpcode() == ARM::t2CMPri)
2086 // Check that CPSR isn't set between the comparison instruction and the one we
2087 // want to change. At the same time, search for Sub.
2088 const TargetRegisterInfo *TRI = &getRegisterInfo();
2090 for (; I != E; --I) {
2091 const MachineInstr &Instr = *I;
2093 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2094 Instr.readsRegister(ARM::CPSR, TRI))
2095 // This instruction modifies or uses CPSR after the one we want to
2096 // change. We can't do this transformation.
2099 // Check whether CmpInstr can be made redundant by the current instruction.
2100 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2106 // The 'and' is below the comparison instruction.
2110 // Return false if no candidates exist.
2114 // The single candidate is called MI.
2117 switch (MI->getOpcode()) {
2151 case ARM::t2EORri: {
2152 // Scan forward for the use of CPSR
2153 // When checking against MI: if it's a conditional code requires
2154 // checking of V bit, then this is not safe to do.
2155 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2156 // If we are done with the basic block, we need to check whether CPSR is
2158 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2160 bool isSafe = false;
2162 E = CmpInstr->getParent()->end();
2163 while (!isSafe && ++I != E) {
2164 const MachineInstr &Instr = *I;
2165 for (unsigned IO = 0, EO = Instr.getNumOperands();
2166 !isSafe && IO != EO; ++IO) {
2167 const MachineOperand &MO = Instr.getOperand(IO);
2168 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2172 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2178 // Condition code is after the operand before CPSR.
2179 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2181 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2182 if (NewCC == ARMCC::AL)
2184 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2185 // on CMP needs to be updated to be based on SUB.
2186 // Push the condition code operands to OperandsToUpdate.
2187 // If it is safe to remove CmpInstr, the condition code of these
2188 // operands will be modified.
2189 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2190 Sub->getOperand(2).getReg() == SrcReg)
2191 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2197 // CPSR can be used multiple times, we should continue.
2210 // If CPSR is not killed nor re-defined, we should check whether it is
2211 // live-out. If it is live-out, do not optimize.
2213 MachineBasicBlock *MBB = CmpInstr->getParent();
2214 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2215 SE = MBB->succ_end(); SI != SE; ++SI)
2216 if ((*SI)->isLiveIn(ARM::CPSR))
2220 // Toggle the optional operand to CPSR.
2221 MI->getOperand(5).setReg(ARM::CPSR);
2222 MI->getOperand(5).setIsDef(true);
2223 CmpInstr->eraseFromParent();
2225 // Modify the condition code of operands in OperandsToUpdate.
2226 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2227 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2228 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2229 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2237 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2238 MachineInstr *DefMI, unsigned Reg,
2239 MachineRegisterInfo *MRI) const {
2240 // Fold large immediates into add, sub, or, xor.
2241 unsigned DefOpc = DefMI->getOpcode();
2242 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2244 if (!DefMI->getOperand(1).isImm())
2245 // Could be t2MOVi32imm <ga:xx>
2248 if (!MRI->hasOneNonDBGUse(Reg))
2251 const MCInstrDesc &DefMCID = DefMI->getDesc();
2252 if (DefMCID.hasOptionalDef()) {
2253 unsigned NumOps = DefMCID.getNumOperands();
2254 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2255 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2256 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2261 const MCInstrDesc &UseMCID = UseMI->getDesc();
2262 if (UseMCID.hasOptionalDef()) {
2263 unsigned NumOps = UseMCID.getNumOperands();
2264 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2265 // If the instruction sets the flag, do not attempt this optimization
2266 // since it may change the semantics of the code.
2270 unsigned UseOpc = UseMI->getOpcode();
2271 unsigned NewUseOpc = 0;
2272 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2273 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2274 bool Commute = false;
2276 default: return false;
2284 case ARM::t2EORrr: {
2285 Commute = UseMI->getOperand(2).getReg() != Reg;
2292 NewUseOpc = ARM::SUBri;
2298 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2300 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2301 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2304 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2305 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2306 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2310 case ARM::t2SUBrr: {
2314 NewUseOpc = ARM::t2SUBri;
2319 case ARM::t2EORrr: {
2320 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2322 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2323 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2326 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2327 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2328 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2336 unsigned OpIdx = Commute ? 2 : 1;
2337 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2338 bool isKill = UseMI->getOperand(OpIdx).isKill();
2339 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2340 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2341 UseMI, UseMI->getDebugLoc(),
2342 get(NewUseOpc), NewReg)
2343 .addReg(Reg1, getKillRegState(isKill))
2344 .addImm(SOImmValV1)));
2345 UseMI->setDesc(get(NewUseOpc));
2346 UseMI->getOperand(1).setReg(NewReg);
2347 UseMI->getOperand(1).setIsKill();
2348 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2349 DefMI->eraseFromParent();
2354 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2355 const MachineInstr *MI) const {
2356 if (!ItinData || ItinData->isEmpty())
2359 const MCInstrDesc &Desc = MI->getDesc();
2360 unsigned Class = Desc.getSchedClass();
2361 int ItinUOps = ItinData->getNumMicroOps(Class);
2365 unsigned Opc = MI->getOpcode();
2368 llvm_unreachable("Unexpected multi-uops instruction!");
2373 // The number of uOps for load / store multiple are determined by the number
2376 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2377 // same cycle. The scheduling for the first load / store must be done
2378 // separately by assuming the address is not 64-bit aligned.
2380 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2381 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2382 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2384 case ARM::VLDMDIA_UPD:
2385 case ARM::VLDMDDB_UPD:
2387 case ARM::VLDMSIA_UPD:
2388 case ARM::VLDMSDB_UPD:
2390 case ARM::VSTMDIA_UPD:
2391 case ARM::VSTMDDB_UPD:
2393 case ARM::VSTMSIA_UPD:
2394 case ARM::VSTMSDB_UPD: {
2395 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2396 return (NumRegs / 2) + (NumRegs % 2) + 1;
2399 case ARM::LDMIA_RET:
2404 case ARM::LDMIA_UPD:
2405 case ARM::LDMDA_UPD:
2406 case ARM::LDMDB_UPD:
2407 case ARM::LDMIB_UPD:
2412 case ARM::STMIA_UPD:
2413 case ARM::STMDA_UPD:
2414 case ARM::STMDB_UPD:
2415 case ARM::STMIB_UPD:
2417 case ARM::tLDMIA_UPD:
2418 case ARM::tSTMIA_UPD:
2422 case ARM::t2LDMIA_RET:
2425 case ARM::t2LDMIA_UPD:
2426 case ARM::t2LDMDB_UPD:
2429 case ARM::t2STMIA_UPD:
2430 case ARM::t2STMDB_UPD: {
2431 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2432 if (Subtarget.isCortexA8()) {
2435 // 4 registers would be issued: 2, 2.
2436 // 5 registers would be issued: 2, 2, 1.
2437 int A8UOps = (NumRegs / 2);
2441 } else if (Subtarget.isCortexA9()) {
2442 int A9UOps = (NumRegs / 2);
2443 // If there are odd number of registers or if it's not 64-bit aligned,
2444 // then it takes an extra AGU (Address Generation Unit) cycle.
2445 if ((NumRegs % 2) ||
2446 !MI->hasOneMemOperand() ||
2447 (*MI->memoperands_begin())->getAlignment() < 8)
2451 // Assume the worst.
2459 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2460 const MCInstrDesc &DefMCID,
2462 unsigned DefIdx, unsigned DefAlign) const {
2463 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2465 // Def is the address writeback.
2466 return ItinData->getOperandCycle(DefClass, DefIdx);
2469 if (Subtarget.isCortexA8()) {
2470 // (regno / 2) + (regno % 2) + 1
2471 DefCycle = RegNo / 2 + 1;
2474 } else if (Subtarget.isCortexA9()) {
2476 bool isSLoad = false;
2478 switch (DefMCID.getOpcode()) {
2481 case ARM::VLDMSIA_UPD:
2482 case ARM::VLDMSDB_UPD:
2487 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2488 // then it takes an extra cycle.
2489 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2492 // Assume the worst.
2493 DefCycle = RegNo + 2;
2500 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2501 const MCInstrDesc &DefMCID,
2503 unsigned DefIdx, unsigned DefAlign) const {
2504 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2506 // Def is the address writeback.
2507 return ItinData->getOperandCycle(DefClass, DefIdx);
2510 if (Subtarget.isCortexA8()) {
2511 // 4 registers would be issued: 1, 2, 1.
2512 // 5 registers would be issued: 1, 2, 2.
2513 DefCycle = RegNo / 2;
2516 // Result latency is issue cycle + 2: E2.
2518 } else if (Subtarget.isCortexA9()) {
2519 DefCycle = (RegNo / 2);
2520 // If there are odd number of registers or if it's not 64-bit aligned,
2521 // then it takes an extra AGU (Address Generation Unit) cycle.
2522 if ((RegNo % 2) || DefAlign < 8)
2524 // Result latency is AGU cycles + 2.
2527 // Assume the worst.
2528 DefCycle = RegNo + 2;
2535 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2536 const MCInstrDesc &UseMCID,
2538 unsigned UseIdx, unsigned UseAlign) const {
2539 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2541 return ItinData->getOperandCycle(UseClass, UseIdx);
2544 if (Subtarget.isCortexA8()) {
2545 // (regno / 2) + (regno % 2) + 1
2546 UseCycle = RegNo / 2 + 1;
2549 } else if (Subtarget.isCortexA9()) {
2551 bool isSStore = false;
2553 switch (UseMCID.getOpcode()) {
2556 case ARM::VSTMSIA_UPD:
2557 case ARM::VSTMSDB_UPD:
2562 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2563 // then it takes an extra cycle.
2564 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2567 // Assume the worst.
2568 UseCycle = RegNo + 2;
2575 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2576 const MCInstrDesc &UseMCID,
2578 unsigned UseIdx, unsigned UseAlign) const {
2579 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2581 return ItinData->getOperandCycle(UseClass, UseIdx);
2584 if (Subtarget.isCortexA8()) {
2585 UseCycle = RegNo / 2;
2590 } else if (Subtarget.isCortexA9()) {
2591 UseCycle = (RegNo / 2);
2592 // If there are odd number of registers or if it's not 64-bit aligned,
2593 // then it takes an extra AGU (Address Generation Unit) cycle.
2594 if ((RegNo % 2) || UseAlign < 8)
2597 // Assume the worst.
2604 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2605 const MCInstrDesc &DefMCID,
2606 unsigned DefIdx, unsigned DefAlign,
2607 const MCInstrDesc &UseMCID,
2608 unsigned UseIdx, unsigned UseAlign) const {
2609 unsigned DefClass = DefMCID.getSchedClass();
2610 unsigned UseClass = UseMCID.getSchedClass();
2612 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2613 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2615 // This may be a def / use of a variable_ops instruction, the operand
2616 // latency might be determinable dynamically. Let the target try to
2619 bool LdmBypass = false;
2620 switch (DefMCID.getOpcode()) {
2622 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2626 case ARM::VLDMDIA_UPD:
2627 case ARM::VLDMDDB_UPD:
2629 case ARM::VLDMSIA_UPD:
2630 case ARM::VLDMSDB_UPD:
2631 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2634 case ARM::LDMIA_RET:
2639 case ARM::LDMIA_UPD:
2640 case ARM::LDMDA_UPD:
2641 case ARM::LDMDB_UPD:
2642 case ARM::LDMIB_UPD:
2644 case ARM::tLDMIA_UPD:
2646 case ARM::t2LDMIA_RET:
2649 case ARM::t2LDMIA_UPD:
2650 case ARM::t2LDMDB_UPD:
2652 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2657 // We can't seem to determine the result latency of the def, assume it's 2.
2661 switch (UseMCID.getOpcode()) {
2663 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2667 case ARM::VSTMDIA_UPD:
2668 case ARM::VSTMDDB_UPD:
2670 case ARM::VSTMSIA_UPD:
2671 case ARM::VSTMSDB_UPD:
2672 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2679 case ARM::STMIA_UPD:
2680 case ARM::STMDA_UPD:
2681 case ARM::STMDB_UPD:
2682 case ARM::STMIB_UPD:
2683 case ARM::tSTMIA_UPD:
2688 case ARM::t2STMIA_UPD:
2689 case ARM::t2STMDB_UPD:
2690 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2695 // Assume it's read in the first stage.
2698 UseCycle = DefCycle - UseCycle + 1;
2701 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2702 // first def operand.
2703 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2706 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2707 UseClass, UseIdx)) {
2715 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2716 const MachineInstr *MI, unsigned Reg,
2717 unsigned &DefIdx, unsigned &Dist) {
2720 MachineBasicBlock::const_iterator I = MI; ++I;
2721 MachineBasicBlock::const_instr_iterator II =
2722 llvm::prior(I.getInstrIterator());
2723 assert(II->isInsideBundle() && "Empty bundle?");
2726 while (II->isInsideBundle()) {
2727 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2734 assert(Idx != -1 && "Cannot find bundled definition!");
2739 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2740 const MachineInstr *MI, unsigned Reg,
2741 unsigned &UseIdx, unsigned &Dist) {
2744 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2745 assert(II->isInsideBundle() && "Empty bundle?");
2746 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2748 // FIXME: This doesn't properly handle multiple uses.
2750 while (II != E && II->isInsideBundle()) {
2751 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2754 if (II->getOpcode() != ARM::t2IT)
2768 /// Return the number of cycles to add to (or subtract from) the static
2769 /// itinerary based on the def opcode and alignment. The caller will ensure that
2770 /// adjusted latency is at least one cycle.
2771 static int adjustDefLatency(const ARMSubtarget &Subtarget,
2772 const MachineInstr *DefMI,
2773 const MCInstrDesc *DefMCID, unsigned DefAlign) {
2775 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) {
2776 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2777 // variants are one cycle cheaper.
2778 switch (DefMCID->getOpcode()) {
2782 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2783 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2785 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2792 case ARM::t2LDRSHs: {
2793 // Thumb2 mode: lsl only.
2794 unsigned ShAmt = DefMI->getOperand(3).getImm();
2795 if (ShAmt == 0 || ShAmt == 2)
2802 if (DefAlign < 8 && Subtarget.isCortexA9()) {
2803 switch (DefMCID->getOpcode()) {
2809 case ARM::VLD1q8wb_fixed:
2810 case ARM::VLD1q16wb_fixed:
2811 case ARM::VLD1q32wb_fixed:
2812 case ARM::VLD1q64wb_fixed:
2813 case ARM::VLD1q8wb_register:
2814 case ARM::VLD1q16wb_register:
2815 case ARM::VLD1q32wb_register:
2816 case ARM::VLD1q64wb_register:
2823 case ARM::VLD2d8wb_fixed:
2824 case ARM::VLD2d16wb_fixed:
2825 case ARM::VLD2d32wb_fixed:
2826 case ARM::VLD2q8wb_fixed:
2827 case ARM::VLD2q16wb_fixed:
2828 case ARM::VLD2q32wb_fixed:
2829 case ARM::VLD2d8wb_register:
2830 case ARM::VLD2d16wb_register:
2831 case ARM::VLD2d32wb_register:
2832 case ARM::VLD2q8wb_register:
2833 case ARM::VLD2q16wb_register:
2834 case ARM::VLD2q32wb_register:
2839 case ARM::VLD3d8_UPD:
2840 case ARM::VLD3d16_UPD:
2841 case ARM::VLD3d32_UPD:
2842 case ARM::VLD1d64Twb_fixed:
2843 case ARM::VLD1d64Twb_register:
2844 case ARM::VLD3q8_UPD:
2845 case ARM::VLD3q16_UPD:
2846 case ARM::VLD3q32_UPD:
2851 case ARM::VLD4d8_UPD:
2852 case ARM::VLD4d16_UPD:
2853 case ARM::VLD4d32_UPD:
2854 case ARM::VLD1d64Qwb_fixed:
2855 case ARM::VLD1d64Qwb_register:
2856 case ARM::VLD4q8_UPD:
2857 case ARM::VLD4q16_UPD:
2858 case ARM::VLD4q32_UPD:
2859 case ARM::VLD1DUPq8:
2860 case ARM::VLD1DUPq16:
2861 case ARM::VLD1DUPq32:
2862 case ARM::VLD1DUPq8wb_fixed:
2863 case ARM::VLD1DUPq16wb_fixed:
2864 case ARM::VLD1DUPq32wb_fixed:
2865 case ARM::VLD1DUPq8wb_register:
2866 case ARM::VLD1DUPq16wb_register:
2867 case ARM::VLD1DUPq32wb_register:
2868 case ARM::VLD2DUPd8:
2869 case ARM::VLD2DUPd16:
2870 case ARM::VLD2DUPd32:
2871 case ARM::VLD2DUPd8wb_fixed:
2872 case ARM::VLD2DUPd16wb_fixed:
2873 case ARM::VLD2DUPd32wb_fixed:
2874 case ARM::VLD2DUPd8wb_register:
2875 case ARM::VLD2DUPd16wb_register:
2876 case ARM::VLD2DUPd32wb_register:
2877 case ARM::VLD4DUPd8:
2878 case ARM::VLD4DUPd16:
2879 case ARM::VLD4DUPd32:
2880 case ARM::VLD4DUPd8_UPD:
2881 case ARM::VLD4DUPd16_UPD:
2882 case ARM::VLD4DUPd32_UPD:
2884 case ARM::VLD1LNd16:
2885 case ARM::VLD1LNd32:
2886 case ARM::VLD1LNd8_UPD:
2887 case ARM::VLD1LNd16_UPD:
2888 case ARM::VLD1LNd32_UPD:
2890 case ARM::VLD2LNd16:
2891 case ARM::VLD2LNd32:
2892 case ARM::VLD2LNq16:
2893 case ARM::VLD2LNq32:
2894 case ARM::VLD2LNd8_UPD:
2895 case ARM::VLD2LNd16_UPD:
2896 case ARM::VLD2LNd32_UPD:
2897 case ARM::VLD2LNq16_UPD:
2898 case ARM::VLD2LNq32_UPD:
2900 case ARM::VLD4LNd16:
2901 case ARM::VLD4LNd32:
2902 case ARM::VLD4LNq16:
2903 case ARM::VLD4LNq32:
2904 case ARM::VLD4LNd8_UPD:
2905 case ARM::VLD4LNd16_UPD:
2906 case ARM::VLD4LNd32_UPD:
2907 case ARM::VLD4LNq16_UPD:
2908 case ARM::VLD4LNq32_UPD:
2909 // If the address is not 64-bit aligned, the latencies of these
2910 // instructions increases by one.
2921 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2922 const MachineInstr *DefMI, unsigned DefIdx,
2923 const MachineInstr *UseMI,
2924 unsigned UseIdx) const {
2925 // No operand latency. The caller may fall back to getInstrLatency.
2926 if (!ItinData || ItinData->isEmpty())
2929 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2930 unsigned Reg = DefMO.getReg();
2931 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2932 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2934 unsigned DefAdj = 0;
2935 if (DefMI->isBundle()) {
2936 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2937 DefMCID = &DefMI->getDesc();
2939 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2940 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
2944 unsigned UseAdj = 0;
2945 if (UseMI->isBundle()) {
2947 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2948 Reg, NewUseIdx, UseAdj);
2954 UseMCID = &UseMI->getDesc();
2957 if (Reg == ARM::CPSR) {
2958 if (DefMI->getOpcode() == ARM::FMSTAT) {
2959 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2960 return Subtarget.isCortexA9() ? 1 : 20;
2963 // CPSR set and branch can be paired in the same cycle.
2964 if (UseMI->isBranch())
2967 // Otherwise it takes the instruction latency (generally one).
2968 unsigned Latency = getInstrLatency(ItinData, DefMI);
2970 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2971 // its uses. Instructions which are otherwise scheduled between them may
2972 // incur a code size penalty (not able to use the CPSR setting 16-bit
2974 if (Latency > 0 && Subtarget.isThumb2()) {
2975 const MachineFunction *MF = DefMI->getParent()->getParent();
2976 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2982 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
2985 unsigned DefAlign = DefMI->hasOneMemOperand()
2986 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2987 unsigned UseAlign = UseMI->hasOneMemOperand()
2988 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2990 // Get the itinerary's latency if possible, and handle variable_ops.
2991 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2992 *UseMCID, UseIdx, UseAlign);
2993 // Unable to find operand latency. The caller may resort to getInstrLatency.
2997 // Adjust for IT block position.
2998 int Adj = DefAdj + UseAdj;
3000 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3001 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3002 if (Adj >= 0 || (int)Latency > -Adj) {
3003 return Latency + Adj;
3005 // Return the itinerary latency, which may be zero but not less than zero.
3010 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3011 SDNode *DefNode, unsigned DefIdx,
3012 SDNode *UseNode, unsigned UseIdx) const {
3013 if (!DefNode->isMachineOpcode())
3016 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3018 if (isZeroCost(DefMCID.Opcode))
3021 if (!ItinData || ItinData->isEmpty())
3022 return DefMCID.mayLoad() ? 3 : 1;
3024 if (!UseNode->isMachineOpcode()) {
3025 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3026 if (Subtarget.isCortexA9())
3027 return Latency <= 2 ? 1 : Latency - 1;
3029 return Latency <= 3 ? 1 : Latency - 2;
3032 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3033 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3034 unsigned DefAlign = !DefMN->memoperands_empty()
3035 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3036 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3037 unsigned UseAlign = !UseMN->memoperands_empty()
3038 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3039 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3040 UseMCID, UseIdx, UseAlign);
3043 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
3044 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3045 // variants are one cycle cheaper.
3046 switch (DefMCID.getOpcode()) {
3051 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3052 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3054 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3061 case ARM::t2LDRSHs: {
3062 // Thumb2 mode: lsl only.
3064 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3065 if (ShAmt == 0 || ShAmt == 2)
3072 if (DefAlign < 8 && Subtarget.isCortexA9())
3073 switch (DefMCID.getOpcode()) {
3079 case ARM::VLD1q8wb_register:
3080 case ARM::VLD1q16wb_register:
3081 case ARM::VLD1q32wb_register:
3082 case ARM::VLD1q64wb_register:
3083 case ARM::VLD1q8wb_fixed:
3084 case ARM::VLD1q16wb_fixed:
3085 case ARM::VLD1q32wb_fixed:
3086 case ARM::VLD1q64wb_fixed:
3090 case ARM::VLD2q8Pseudo:
3091 case ARM::VLD2q16Pseudo:
3092 case ARM::VLD2q32Pseudo:
3093 case ARM::VLD2d8wb_fixed:
3094 case ARM::VLD2d16wb_fixed:
3095 case ARM::VLD2d32wb_fixed:
3096 case ARM::VLD2q8PseudoWB_fixed:
3097 case ARM::VLD2q16PseudoWB_fixed:
3098 case ARM::VLD2q32PseudoWB_fixed:
3099 case ARM::VLD2d8wb_register:
3100 case ARM::VLD2d16wb_register:
3101 case ARM::VLD2d32wb_register:
3102 case ARM::VLD2q8PseudoWB_register:
3103 case ARM::VLD2q16PseudoWB_register:
3104 case ARM::VLD2q32PseudoWB_register:
3105 case ARM::VLD3d8Pseudo:
3106 case ARM::VLD3d16Pseudo:
3107 case ARM::VLD3d32Pseudo:
3108 case ARM::VLD1d64TPseudo:
3109 case ARM::VLD3d8Pseudo_UPD:
3110 case ARM::VLD3d16Pseudo_UPD:
3111 case ARM::VLD3d32Pseudo_UPD:
3112 case ARM::VLD3q8Pseudo_UPD:
3113 case ARM::VLD3q16Pseudo_UPD:
3114 case ARM::VLD3q32Pseudo_UPD:
3115 case ARM::VLD3q8oddPseudo:
3116 case ARM::VLD3q16oddPseudo:
3117 case ARM::VLD3q32oddPseudo:
3118 case ARM::VLD3q8oddPseudo_UPD:
3119 case ARM::VLD3q16oddPseudo_UPD:
3120 case ARM::VLD3q32oddPseudo_UPD:
3121 case ARM::VLD4d8Pseudo:
3122 case ARM::VLD4d16Pseudo:
3123 case ARM::VLD4d32Pseudo:
3124 case ARM::VLD1d64QPseudo:
3125 case ARM::VLD4d8Pseudo_UPD:
3126 case ARM::VLD4d16Pseudo_UPD:
3127 case ARM::VLD4d32Pseudo_UPD:
3128 case ARM::VLD4q8Pseudo_UPD:
3129 case ARM::VLD4q16Pseudo_UPD:
3130 case ARM::VLD4q32Pseudo_UPD:
3131 case ARM::VLD4q8oddPseudo:
3132 case ARM::VLD4q16oddPseudo:
3133 case ARM::VLD4q32oddPseudo:
3134 case ARM::VLD4q8oddPseudo_UPD:
3135 case ARM::VLD4q16oddPseudo_UPD:
3136 case ARM::VLD4q32oddPseudo_UPD:
3137 case ARM::VLD1DUPq8:
3138 case ARM::VLD1DUPq16:
3139 case ARM::VLD1DUPq32:
3140 case ARM::VLD1DUPq8wb_fixed:
3141 case ARM::VLD1DUPq16wb_fixed:
3142 case ARM::VLD1DUPq32wb_fixed:
3143 case ARM::VLD1DUPq8wb_register:
3144 case ARM::VLD1DUPq16wb_register:
3145 case ARM::VLD1DUPq32wb_register:
3146 case ARM::VLD2DUPd8:
3147 case ARM::VLD2DUPd16:
3148 case ARM::VLD2DUPd32:
3149 case ARM::VLD2DUPd8wb_fixed:
3150 case ARM::VLD2DUPd16wb_fixed:
3151 case ARM::VLD2DUPd32wb_fixed:
3152 case ARM::VLD2DUPd8wb_register:
3153 case ARM::VLD2DUPd16wb_register:
3154 case ARM::VLD2DUPd32wb_register:
3155 case ARM::VLD4DUPd8Pseudo:
3156 case ARM::VLD4DUPd16Pseudo:
3157 case ARM::VLD4DUPd32Pseudo:
3158 case ARM::VLD4DUPd8Pseudo_UPD:
3159 case ARM::VLD4DUPd16Pseudo_UPD:
3160 case ARM::VLD4DUPd32Pseudo_UPD:
3161 case ARM::VLD1LNq8Pseudo:
3162 case ARM::VLD1LNq16Pseudo:
3163 case ARM::VLD1LNq32Pseudo:
3164 case ARM::VLD1LNq8Pseudo_UPD:
3165 case ARM::VLD1LNq16Pseudo_UPD:
3166 case ARM::VLD1LNq32Pseudo_UPD:
3167 case ARM::VLD2LNd8Pseudo:
3168 case ARM::VLD2LNd16Pseudo:
3169 case ARM::VLD2LNd32Pseudo:
3170 case ARM::VLD2LNq16Pseudo:
3171 case ARM::VLD2LNq32Pseudo:
3172 case ARM::VLD2LNd8Pseudo_UPD:
3173 case ARM::VLD2LNd16Pseudo_UPD:
3174 case ARM::VLD2LNd32Pseudo_UPD:
3175 case ARM::VLD2LNq16Pseudo_UPD:
3176 case ARM::VLD2LNq32Pseudo_UPD:
3177 case ARM::VLD4LNd8Pseudo:
3178 case ARM::VLD4LNd16Pseudo:
3179 case ARM::VLD4LNd32Pseudo:
3180 case ARM::VLD4LNq16Pseudo:
3181 case ARM::VLD4LNq32Pseudo:
3182 case ARM::VLD4LNd8Pseudo_UPD:
3183 case ARM::VLD4LNd16Pseudo_UPD:
3184 case ARM::VLD4LNd32Pseudo_UPD:
3185 case ARM::VLD4LNq16Pseudo_UPD:
3186 case ARM::VLD4LNq32Pseudo_UPD:
3187 // If the address is not 64-bit aligned, the latencies of these
3188 // instructions increases by one.
3197 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
3198 const MachineInstr *DefMI, unsigned DefIdx,
3199 const MachineInstr *DepMI) const {
3200 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
3201 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
3204 // If the second MI is predicated, then there is an implicit use dependency.
3205 return getInstrLatency(ItinData, DefMI);
3208 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3209 const MachineInstr *MI,
3210 unsigned *PredCost) const {
3211 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3212 MI->isRegSequence() || MI->isImplicitDef())
3215 // An instruction scheduler typically runs on unbundled instructions, however
3216 // other passes may query the latency of a bundled instruction.
3217 if (MI->isBundle()) {
3218 unsigned Latency = 0;
3219 MachineBasicBlock::const_instr_iterator I = MI;
3220 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3221 while (++I != E && I->isInsideBundle()) {
3222 if (I->getOpcode() != ARM::t2IT)
3223 Latency += getInstrLatency(ItinData, I, PredCost);
3228 const MCInstrDesc &MCID = MI->getDesc();
3229 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3230 // When predicated, CPSR is an additional source operand for CPSR updating
3231 // instructions, this apparently increases their latencies.
3234 // Be sure to call getStageLatency for an empty itinerary in case it has a
3235 // valid MinLatency property.
3237 return MI->mayLoad() ? 3 : 1;
3239 unsigned Class = MCID.getSchedClass();
3241 // For instructions with variable uops, use uops as latency.
3242 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3243 return getNumMicroOps(ItinData, MI);
3245 // For the common case, fall back on the itinerary's latency.
3246 unsigned Latency = ItinData->getStageLatency(Class);
3248 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3249 unsigned DefAlign = MI->hasOneMemOperand()
3250 ? (*MI->memoperands_begin())->getAlignment() : 0;
3251 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3252 if (Adj >= 0 || (int)Latency > -Adj) {
3253 return Latency + Adj;
3258 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3259 SDNode *Node) const {
3260 if (!Node->isMachineOpcode())
3263 if (!ItinData || ItinData->isEmpty())
3266 unsigned Opcode = Node->getMachineOpcode();
3269 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3276 bool ARMBaseInstrInfo::
3277 hasHighOperandLatency(const InstrItineraryData *ItinData,
3278 const MachineRegisterInfo *MRI,
3279 const MachineInstr *DefMI, unsigned DefIdx,
3280 const MachineInstr *UseMI, unsigned UseIdx) const {
3281 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3282 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3283 if (Subtarget.isCortexA8() &&
3284 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3285 // CortexA8 VFP instructions are not pipelined.
3288 // Hoist VFP / NEON instructions with 4 or higher latency.
3289 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3292 Latency = getInstrLatency(ItinData, DefMI);
3295 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3296 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3299 bool ARMBaseInstrInfo::
3300 hasLowDefLatency(const InstrItineraryData *ItinData,
3301 const MachineInstr *DefMI, unsigned DefIdx) const {
3302 if (!ItinData || ItinData->isEmpty())
3305 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3306 if (DDomain == ARMII::DomainGeneral) {
3307 unsigned DefClass = DefMI->getDesc().getSchedClass();
3308 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3309 return (DefCycle != -1 && DefCycle <= 2);
3314 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3315 StringRef &ErrInfo) const {
3316 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3317 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3324 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3325 unsigned &AddSubOpc,
3326 bool &NegAcc, bool &HasLane) const {
3327 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3328 if (I == MLxEntryMap.end())
3331 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3332 MulOpc = Entry.MulOpc;
3333 AddSubOpc = Entry.AddSubOpc;
3334 NegAcc = Entry.NegAcc;
3335 HasLane = Entry.HasLane;
3339 //===----------------------------------------------------------------------===//
3340 // Execution domains.
3341 //===----------------------------------------------------------------------===//
3343 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3344 // and some can go down both. The vmov instructions go down the VFP pipeline,
3345 // but they can be changed to vorr equivalents that are executed by the NEON
3348 // We use the following execution domain numbering:
3356 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3358 std::pair<uint16_t, uint16_t>
3359 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3360 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3361 // if they are not predicated.
3362 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3363 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3365 // Cortex-A9 is particularly picky about mixing the two and wants these
3367 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3368 (MI->getOpcode() == ARM::VMOVRS ||
3369 MI->getOpcode() == ARM::VMOVSR))
3370 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3372 // No other instructions can be swizzled, so just determine their domain.
3373 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3375 if (Domain & ARMII::DomainNEON)
3376 return std::make_pair(ExeNEON, 0);
3378 // Certain instructions can go either way on Cortex-A8.
3379 // Treat them as NEON instructions.
3380 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3381 return std::make_pair(ExeNEON, 0);
3383 if (Domain & ARMII::DomainVFP)
3384 return std::make_pair(ExeVFP, 0);
3386 return std::make_pair(ExeGeneric, 0);
3390 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3391 unsigned DstReg, SrcReg, DReg;
3393 MachineInstrBuilder MIB(MI);
3394 const TargetRegisterInfo *TRI = &getRegisterInfo();
3396 switch (MI->getOpcode()) {
3398 llvm_unreachable("cannot handle opcode!");
3401 if (Domain != ExeNEON)
3404 // Zap the predicate operands.
3405 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3406 MI->RemoveOperand(3);
3407 MI->RemoveOperand(2);
3409 // Change to a VORRd which requires two identical use operands.
3410 MI->setDesc(get(ARM::VORRd));
3412 // Add the extra source operand and new predicates.
3413 // This will go before any implicit ops.
3414 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
3417 if (Domain != ExeNEON)
3419 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3421 DstReg = MI->getOperand(0).getReg();
3422 SrcReg = MI->getOperand(1).getReg();
3424 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, &ARM::DPRRegClass);
3426 if (DReg == ARM::NoRegister) {
3427 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_1, &ARM::DPRRegClass);
3429 assert(DReg && "S-register with no D super-register?");
3432 MI->RemoveOperand(3);
3433 MI->RemoveOperand(2);
3434 MI->RemoveOperand(1);
3436 MI->setDesc(get(ARM::VGETLNi32));
3440 MIB->getOperand(1).setIsUndef();
3441 MIB.addReg(SrcReg, RegState::Implicit);
3443 AddDefaultPred(MIB);
3446 if (Domain != ExeNEON)
3448 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3450 DstReg = MI->getOperand(0).getReg();
3451 SrcReg = MI->getOperand(1).getReg();
3452 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass);
3454 if (DReg == ARM::NoRegister) {
3455 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass);
3457 assert(DReg && "S-register with no D super-register?");
3459 isKill = MI->getOperand(0).isKill();
3461 MI->RemoveOperand(3);
3462 MI->RemoveOperand(2);
3463 MI->RemoveOperand(1);
3464 MI->RemoveOperand(0);
3466 MI->setDesc(get(ARM::VSETLNi32));
3472 MIB->getOperand(1).setIsUndef();
3475 MIB->addRegisterKilled(DstReg, TRI, true);
3476 MIB->addRegisterDefined(DstReg, TRI);
3478 AddDefaultPred(MIB);
3484 bool ARMBaseInstrInfo::hasNOP() const {
3485 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;