1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Handle register classes that require multiple instructions.
684 unsigned BeginIdx = 0;
685 unsigned SubRegs = 0;
686 unsigned Spacing = 1;
688 // Use VORRq when possible.
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
693 // Fall back to VMOVD.
694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
709 const TargetRegisterInfo *TRI = &getRegisterInfo();
710 MachineInstrBuilder Mov;
711 for (unsigned i = 0; i != SubRegs; ++i) {
712 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
713 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
714 assert(Dst && Src && "Bad sub-register");
715 Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
717 // VORR takes two source operands.
718 if (Opc == ARM::VORRq)
721 // Add implicit super-register defs and kills to the last instruction.
722 Mov->addRegisterDefined(DestReg, TRI);
724 Mov->addRegisterKilled(SrcReg, TRI);
728 llvm_unreachable("Impossible reg-to-reg copy");
732 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
733 unsigned Reg, unsigned SubIdx, unsigned State,
734 const TargetRegisterInfo *TRI) {
736 return MIB.addReg(Reg, State);
738 if (TargetRegisterInfo::isPhysicalRegister(Reg))
739 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
740 return MIB.addReg(Reg, State, SubIdx);
743 void ARMBaseInstrInfo::
744 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
745 unsigned SrcReg, bool isKill, int FI,
746 const TargetRegisterClass *RC,
747 const TargetRegisterInfo *TRI) const {
749 if (I != MBB.end()) DL = I->getDebugLoc();
750 MachineFunction &MF = *MBB.getParent();
751 MachineFrameInfo &MFI = *MF.getFrameInfo();
752 unsigned Align = MFI.getObjectAlignment(FI);
754 MachineMemOperand *MMO =
755 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
756 MachineMemOperand::MOStore,
757 MFI.getObjectSize(FI),
760 switch (RC->getSize()) {
762 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
764 .addReg(SrcReg, getKillRegState(isKill))
765 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
766 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
768 .addReg(SrcReg, getKillRegState(isKill))
769 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
771 llvm_unreachable("Unknown reg class!");
774 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
775 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
776 .addReg(SrcReg, getKillRegState(isKill))
777 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
779 llvm_unreachable("Unknown reg class!");
782 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
783 // Use aligned spills if the stack can be realigned.
784 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
785 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
786 .addFrameIndex(FI).addImm(16)
787 .addReg(SrcReg, getKillRegState(isKill))
788 .addMemOperand(MMO));
790 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
791 .addReg(SrcReg, getKillRegState(isKill))
793 .addMemOperand(MMO));
796 llvm_unreachable("Unknown reg class!");
799 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
800 // Use aligned spills if the stack can be realigned.
801 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
802 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
803 .addFrameIndex(FI).addImm(16)
804 .addReg(SrcReg, getKillRegState(isKill))
805 .addMemOperand(MMO));
807 MachineInstrBuilder MIB =
808 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
813 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
816 llvm_unreachable("Unknown reg class!");
819 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
820 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
821 // FIXME: It's possible to only store part of the QQ register if the
822 // spilled def has a sub-register index.
823 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
824 .addFrameIndex(FI).addImm(16)
825 .addReg(SrcReg, getKillRegState(isKill))
826 .addMemOperand(MMO));
828 MachineInstrBuilder MIB =
829 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
832 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
833 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
834 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
835 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
838 llvm_unreachable("Unknown reg class!");
841 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
842 MachineInstrBuilder MIB =
843 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
846 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
851 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
852 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
853 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
855 llvm_unreachable("Unknown reg class!");
858 llvm_unreachable("Unknown reg class!");
863 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
864 int &FrameIndex) const {
865 switch (MI->getOpcode()) {
868 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
869 if (MI->getOperand(1).isFI() &&
870 MI->getOperand(2).isReg() &&
871 MI->getOperand(3).isImm() &&
872 MI->getOperand(2).getReg() == 0 &&
873 MI->getOperand(3).getImm() == 0) {
874 FrameIndex = MI->getOperand(1).getIndex();
875 return MI->getOperand(0).getReg();
883 if (MI->getOperand(1).isFI() &&
884 MI->getOperand(2).isImm() &&
885 MI->getOperand(2).getImm() == 0) {
886 FrameIndex = MI->getOperand(1).getIndex();
887 return MI->getOperand(0).getReg();
891 if (MI->getOperand(0).isFI() &&
892 MI->getOperand(2).getSubReg() == 0) {
893 FrameIndex = MI->getOperand(0).getIndex();
894 return MI->getOperand(2).getReg();
898 if (MI->getOperand(1).isFI() &&
899 MI->getOperand(0).getSubReg() == 0) {
900 FrameIndex = MI->getOperand(1).getIndex();
901 return MI->getOperand(0).getReg();
909 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
910 int &FrameIndex) const {
911 const MachineMemOperand *Dummy;
912 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
915 void ARMBaseInstrInfo::
916 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
917 unsigned DestReg, int FI,
918 const TargetRegisterClass *RC,
919 const TargetRegisterInfo *TRI) const {
921 if (I != MBB.end()) DL = I->getDebugLoc();
922 MachineFunction &MF = *MBB.getParent();
923 MachineFrameInfo &MFI = *MF.getFrameInfo();
924 unsigned Align = MFI.getObjectAlignment(FI);
925 MachineMemOperand *MMO =
926 MF.getMachineMemOperand(
927 MachinePointerInfo::getFixedStack(FI),
928 MachineMemOperand::MOLoad,
929 MFI.getObjectSize(FI),
932 switch (RC->getSize()) {
934 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
935 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
936 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
938 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
939 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
940 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
942 llvm_unreachable("Unknown reg class!");
945 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
947 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
949 llvm_unreachable("Unknown reg class!");
952 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
953 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
954 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
955 .addFrameIndex(FI).addImm(16)
956 .addMemOperand(MMO));
958 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
960 .addMemOperand(MMO));
963 llvm_unreachable("Unknown reg class!");
966 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
967 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
968 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
969 .addFrameIndex(FI).addImm(16)
970 .addMemOperand(MMO));
972 MachineInstrBuilder MIB =
973 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
975 .addMemOperand(MMO));
976 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
977 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
978 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
979 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
980 MIB.addReg(DestReg, RegState::ImplicitDefine);
983 llvm_unreachable("Unknown reg class!");
986 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
987 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
988 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
989 .addFrameIndex(FI).addImm(16)
990 .addMemOperand(MMO));
992 MachineInstrBuilder MIB =
993 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
996 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
997 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
998 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
999 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1000 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1001 MIB.addReg(DestReg, RegState::ImplicitDefine);
1004 llvm_unreachable("Unknown reg class!");
1007 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1008 MachineInstrBuilder MIB =
1009 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1011 .addMemOperand(MMO);
1012 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1013 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1014 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1018 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1019 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1020 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1021 MIB.addReg(DestReg, RegState::ImplicitDefine);
1023 llvm_unreachable("Unknown reg class!");
1026 llvm_unreachable("Unknown regclass!");
1031 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1032 int &FrameIndex) const {
1033 switch (MI->getOpcode()) {
1036 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1037 if (MI->getOperand(1).isFI() &&
1038 MI->getOperand(2).isReg() &&
1039 MI->getOperand(3).isImm() &&
1040 MI->getOperand(2).getReg() == 0 &&
1041 MI->getOperand(3).getImm() == 0) {
1042 FrameIndex = MI->getOperand(1).getIndex();
1043 return MI->getOperand(0).getReg();
1051 if (MI->getOperand(1).isFI() &&
1052 MI->getOperand(2).isImm() &&
1053 MI->getOperand(2).getImm() == 0) {
1054 FrameIndex = MI->getOperand(1).getIndex();
1055 return MI->getOperand(0).getReg();
1059 if (MI->getOperand(1).isFI() &&
1060 MI->getOperand(0).getSubReg() == 0) {
1061 FrameIndex = MI->getOperand(1).getIndex();
1062 return MI->getOperand(0).getReg();
1066 if (MI->getOperand(1).isFI() &&
1067 MI->getOperand(0).getSubReg() == 0) {
1068 FrameIndex = MI->getOperand(1).getIndex();
1069 return MI->getOperand(0).getReg();
1077 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1078 int &FrameIndex) const {
1079 const MachineMemOperand *Dummy;
1080 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1083 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1084 // This hook gets to expand COPY instructions before they become
1085 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1086 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1087 // changed into a VORR that can go down the NEON pipeline.
1088 if (!WidenVMOVS || !MI->isCopy())
1091 // Look for a copy between even S-registers. That is where we keep floats
1092 // when using NEON v2f32 instructions for f32 arithmetic.
1093 unsigned DstRegS = MI->getOperand(0).getReg();
1094 unsigned SrcRegS = MI->getOperand(1).getReg();
1095 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1098 const TargetRegisterInfo *TRI = &getRegisterInfo();
1099 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1101 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1103 if (!DstRegD || !SrcRegD)
1106 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1107 // legal if the COPY already defines the full DstRegD, and it isn't a
1108 // sub-register insertion.
1109 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1112 // A dead copy shouldn't show up here, but reject it just in case.
1113 if (MI->getOperand(0).isDead())
1116 // All clear, widen the COPY.
1117 DEBUG(dbgs() << "widening: " << *MI);
1119 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1120 // or some other super-register.
1121 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1122 if (ImpDefIdx != -1)
1123 MI->RemoveOperand(ImpDefIdx);
1125 // Change the opcode and operands.
1126 MI->setDesc(get(ARM::VMOVD));
1127 MI->getOperand(0).setReg(DstRegD);
1128 MI->getOperand(1).setReg(SrcRegD);
1129 AddDefaultPred(MachineInstrBuilder(MI));
1131 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1132 // register scavenger and machine verifier, so we need to indicate that we
1133 // are reading an undefined value from SrcRegD, but a proper value from
1135 MI->getOperand(1).setIsUndef();
1136 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1138 // SrcRegD may actually contain an unrelated value in the ssub_1
1139 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1140 if (MI->getOperand(1).isKill()) {
1141 MI->getOperand(1).setIsKill(false);
1142 MI->addRegisterKilled(SrcRegS, TRI, true);
1145 DEBUG(dbgs() << "replaced by: " << *MI);
1150 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1151 int FrameIx, uint64_t Offset,
1152 const MDNode *MDPtr,
1153 DebugLoc DL) const {
1154 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1155 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1159 /// Create a copy of a const pool value. Update CPI to the new index and return
1161 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1162 MachineConstantPool *MCP = MF.getConstantPool();
1163 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1165 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1166 assert(MCPE.isMachineConstantPoolEntry() &&
1167 "Expecting a machine constantpool entry!");
1168 ARMConstantPoolValue *ACPV =
1169 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1171 unsigned PCLabelId = AFI->createPICLabelUId();
1172 ARMConstantPoolValue *NewCPV = 0;
1173 // FIXME: The below assumes PIC relocation model and that the function
1174 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1175 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1176 // instructions, so that's probably OK, but is PIC always correct when
1178 if (ACPV->isGlobalValue())
1179 NewCPV = ARMConstantPoolConstant::
1180 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1182 else if (ACPV->isExtSymbol())
1183 NewCPV = ARMConstantPoolSymbol::
1184 Create(MF.getFunction()->getContext(),
1185 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1186 else if (ACPV->isBlockAddress())
1187 NewCPV = ARMConstantPoolConstant::
1188 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1189 ARMCP::CPBlockAddress, 4);
1190 else if (ACPV->isLSDA())
1191 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1193 else if (ACPV->isMachineBasicBlock())
1194 NewCPV = ARMConstantPoolMBB::
1195 Create(MF.getFunction()->getContext(),
1196 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1198 llvm_unreachable("Unexpected ARM constantpool value type!!");
1199 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1203 void ARMBaseInstrInfo::
1204 reMaterialize(MachineBasicBlock &MBB,
1205 MachineBasicBlock::iterator I,
1206 unsigned DestReg, unsigned SubIdx,
1207 const MachineInstr *Orig,
1208 const TargetRegisterInfo &TRI) const {
1209 unsigned Opcode = Orig->getOpcode();
1212 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1213 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1217 case ARM::tLDRpci_pic:
1218 case ARM::t2LDRpci_pic: {
1219 MachineFunction &MF = *MBB.getParent();
1220 unsigned CPI = Orig->getOperand(1).getIndex();
1221 unsigned PCLabelId = duplicateCPV(MF, CPI);
1222 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1224 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1225 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1232 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1233 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1234 switch(Orig->getOpcode()) {
1235 case ARM::tLDRpci_pic:
1236 case ARM::t2LDRpci_pic: {
1237 unsigned CPI = Orig->getOperand(1).getIndex();
1238 unsigned PCLabelId = duplicateCPV(MF, CPI);
1239 Orig->getOperand(1).setIndex(CPI);
1240 Orig->getOperand(2).setImm(PCLabelId);
1247 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1248 const MachineInstr *MI1,
1249 const MachineRegisterInfo *MRI) const {
1250 int Opcode = MI0->getOpcode();
1251 if (Opcode == ARM::t2LDRpci ||
1252 Opcode == ARM::t2LDRpci_pic ||
1253 Opcode == ARM::tLDRpci ||
1254 Opcode == ARM::tLDRpci_pic ||
1255 Opcode == ARM::MOV_ga_dyn ||
1256 Opcode == ARM::MOV_ga_pcrel ||
1257 Opcode == ARM::MOV_ga_pcrel_ldr ||
1258 Opcode == ARM::t2MOV_ga_dyn ||
1259 Opcode == ARM::t2MOV_ga_pcrel) {
1260 if (MI1->getOpcode() != Opcode)
1262 if (MI0->getNumOperands() != MI1->getNumOperands())
1265 const MachineOperand &MO0 = MI0->getOperand(1);
1266 const MachineOperand &MO1 = MI1->getOperand(1);
1267 if (MO0.getOffset() != MO1.getOffset())
1270 if (Opcode == ARM::MOV_ga_dyn ||
1271 Opcode == ARM::MOV_ga_pcrel ||
1272 Opcode == ARM::MOV_ga_pcrel_ldr ||
1273 Opcode == ARM::t2MOV_ga_dyn ||
1274 Opcode == ARM::t2MOV_ga_pcrel)
1275 // Ignore the PC labels.
1276 return MO0.getGlobal() == MO1.getGlobal();
1278 const MachineFunction *MF = MI0->getParent()->getParent();
1279 const MachineConstantPool *MCP = MF->getConstantPool();
1280 int CPI0 = MO0.getIndex();
1281 int CPI1 = MO1.getIndex();
1282 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1283 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1284 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1285 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1286 if (isARMCP0 && isARMCP1) {
1287 ARMConstantPoolValue *ACPV0 =
1288 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1289 ARMConstantPoolValue *ACPV1 =
1290 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1291 return ACPV0->hasSameValue(ACPV1);
1292 } else if (!isARMCP0 && !isARMCP1) {
1293 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1296 } else if (Opcode == ARM::PICLDR) {
1297 if (MI1->getOpcode() != Opcode)
1299 if (MI0->getNumOperands() != MI1->getNumOperands())
1302 unsigned Addr0 = MI0->getOperand(1).getReg();
1303 unsigned Addr1 = MI1->getOperand(1).getReg();
1304 if (Addr0 != Addr1) {
1306 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1307 !TargetRegisterInfo::isVirtualRegister(Addr1))
1310 // This assumes SSA form.
1311 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1312 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1313 // Check if the loaded value, e.g. a constantpool of a global address, are
1315 if (!produceSameValue(Def0, Def1, MRI))
1319 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1320 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1321 const MachineOperand &MO0 = MI0->getOperand(i);
1322 const MachineOperand &MO1 = MI1->getOperand(i);
1323 if (!MO0.isIdenticalTo(MO1))
1329 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1332 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1333 /// determine if two loads are loading from the same base address. It should
1334 /// only return true if the base pointers are the same and the only differences
1335 /// between the two addresses is the offset. It also returns the offsets by
1337 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1339 int64_t &Offset2) const {
1340 // Don't worry about Thumb: just ARM and Thumb2.
1341 if (Subtarget.isThumb1Only()) return false;
1343 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1346 switch (Load1->getMachineOpcode()) {
1359 case ARM::t2LDRSHi8:
1361 case ARM::t2LDRSHi12:
1365 switch (Load2->getMachineOpcode()) {
1378 case ARM::t2LDRSHi8:
1380 case ARM::t2LDRSHi12:
1384 // Check if base addresses and chain operands match.
1385 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1386 Load1->getOperand(4) != Load2->getOperand(4))
1389 // Index should be Reg0.
1390 if (Load1->getOperand(3) != Load2->getOperand(3))
1393 // Determine the offsets.
1394 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1395 isa<ConstantSDNode>(Load2->getOperand(1))) {
1396 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1397 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1404 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1405 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1406 /// be scheduled togther. On some targets if two loads are loading from
1407 /// addresses in the same cache line, it's better if they are scheduled
1408 /// together. This function takes two integers that represent the load offsets
1409 /// from the common base address. It returns true if it decides it's desirable
1410 /// to schedule the two loads together. "NumLoads" is the number of loads that
1411 /// have already been scheduled after Load1.
1412 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1413 int64_t Offset1, int64_t Offset2,
1414 unsigned NumLoads) const {
1415 // Don't worry about Thumb: just ARM and Thumb2.
1416 if (Subtarget.isThumb1Only()) return false;
1418 assert(Offset2 > Offset1);
1420 if ((Offset2 - Offset1) / 8 > 64)
1423 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1424 return false; // FIXME: overly conservative?
1426 // Four loads in a row should be sufficient.
1433 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1434 const MachineBasicBlock *MBB,
1435 const MachineFunction &MF) const {
1436 // Debug info is never a scheduling boundary. It's necessary to be explicit
1437 // due to the special treatment of IT instructions below, otherwise a
1438 // dbg_value followed by an IT will result in the IT instruction being
1439 // considered a scheduling hazard, which is wrong. It should be the actual
1440 // instruction preceding the dbg_value instruction(s), just like it is
1441 // when debug info is not present.
1442 if (MI->isDebugValue())
1445 // Terminators and labels can't be scheduled around.
1446 if (MI->isTerminator() || MI->isLabel())
1449 // Treat the start of the IT block as a scheduling boundary, but schedule
1450 // t2IT along with all instructions following it.
1451 // FIXME: This is a big hammer. But the alternative is to add all potential
1452 // true and anti dependencies to IT block instructions as implicit operands
1453 // to the t2IT instruction. The added compile time and complexity does not
1455 MachineBasicBlock::const_iterator I = MI;
1456 // Make sure to skip any dbg_value instructions
1457 while (++I != MBB->end() && I->isDebugValue())
1459 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1462 // Don't attempt to schedule around any instruction that defines
1463 // a stack-oriented pointer, as it's unlikely to be profitable. This
1464 // saves compile time, because it doesn't require every single
1465 // stack slot reference to depend on the instruction that does the
1467 // Calls don't actually change the stack pointer, even if they have imp-defs.
1468 // No ARM calling conventions change the stack pointer. (X86 calling
1469 // conventions sometimes do).
1470 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1476 bool ARMBaseInstrInfo::
1477 isProfitableToIfCvt(MachineBasicBlock &MBB,
1478 unsigned NumCycles, unsigned ExtraPredCycles,
1479 const BranchProbability &Probability) const {
1483 // Attempt to estimate the relative costs of predication versus branching.
1484 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1485 UnpredCost /= Probability.getDenominator();
1486 UnpredCost += 1; // The branch itself
1487 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1489 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1492 bool ARMBaseInstrInfo::
1493 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1494 unsigned TCycles, unsigned TExtra,
1495 MachineBasicBlock &FMBB,
1496 unsigned FCycles, unsigned FExtra,
1497 const BranchProbability &Probability) const {
1498 if (!TCycles || !FCycles)
1501 // Attempt to estimate the relative costs of predication versus branching.
1502 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1503 TUnpredCost /= Probability.getDenominator();
1505 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1506 unsigned FUnpredCost = Comp * FCycles;
1507 FUnpredCost /= Probability.getDenominator();
1509 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1510 UnpredCost += 1; // The branch itself
1511 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1513 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1516 /// getInstrPredicate - If instruction is predicated, returns its predicate
1517 /// condition, otherwise returns AL. It also returns the condition code
1518 /// register by reference.
1520 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1521 int PIdx = MI->findFirstPredOperandIdx();
1527 PredReg = MI->getOperand(PIdx+1).getReg();
1528 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1532 int llvm::getMatchingCondBranchOpcode(int Opc) {
1537 if (Opc == ARM::t2B)
1540 llvm_unreachable("Unknown unconditional branch opcode!");
1543 /// commuteInstruction - Handle commutable instructions.
1545 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1546 switch (MI->getOpcode()) {
1548 case ARM::t2MOVCCr: {
1549 // MOVCC can be commuted by inverting the condition.
1550 unsigned PredReg = 0;
1551 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1552 // MOVCC AL can't be inverted. Shouldn't happen.
1553 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1555 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1558 // After swapping the MOVCC operands, also invert the condition.
1559 MI->getOperand(MI->findFirstPredOperandIdx())
1560 .setImm(ARMCC::getOppositeCondition(CC));
1564 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1567 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1568 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1571 /// This will go away once we can teach tblgen how to set the optional CPSR def
1573 struct AddSubFlagsOpcodePair {
1575 uint16_t MachineOpc;
1578 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1579 {ARM::ADDSri, ARM::ADDri},
1580 {ARM::ADDSrr, ARM::ADDrr},
1581 {ARM::ADDSrsi, ARM::ADDrsi},
1582 {ARM::ADDSrsr, ARM::ADDrsr},
1584 {ARM::SUBSri, ARM::SUBri},
1585 {ARM::SUBSrr, ARM::SUBrr},
1586 {ARM::SUBSrsi, ARM::SUBrsi},
1587 {ARM::SUBSrsr, ARM::SUBrsr},
1589 {ARM::RSBSri, ARM::RSBri},
1590 {ARM::RSBSrsi, ARM::RSBrsi},
1591 {ARM::RSBSrsr, ARM::RSBrsr},
1593 {ARM::t2ADDSri, ARM::t2ADDri},
1594 {ARM::t2ADDSrr, ARM::t2ADDrr},
1595 {ARM::t2ADDSrs, ARM::t2ADDrs},
1597 {ARM::t2SUBSri, ARM::t2SUBri},
1598 {ARM::t2SUBSrr, ARM::t2SUBrr},
1599 {ARM::t2SUBSrs, ARM::t2SUBrs},
1601 {ARM::t2RSBSri, ARM::t2RSBri},
1602 {ARM::t2RSBSrs, ARM::t2RSBrs},
1605 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1606 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1607 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1608 return AddSubFlagsOpcodeMap[i].MachineOpc;
1612 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1613 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1614 unsigned DestReg, unsigned BaseReg, int NumBytes,
1615 ARMCC::CondCodes Pred, unsigned PredReg,
1616 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1617 bool isSub = NumBytes < 0;
1618 if (isSub) NumBytes = -NumBytes;
1621 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1622 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1623 assert(ThisVal && "Didn't extract field correctly");
1625 // We will handle these bits from offset, clear them.
1626 NumBytes &= ~ThisVal;
1628 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1630 // Build the new ADD / SUB.
1631 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1632 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1633 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1634 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1635 .setMIFlags(MIFlags);
1640 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1641 unsigned FrameReg, int &Offset,
1642 const ARMBaseInstrInfo &TII) {
1643 unsigned Opcode = MI.getOpcode();
1644 const MCInstrDesc &Desc = MI.getDesc();
1645 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1648 // Memory operands in inline assembly always use AddrMode2.
1649 if (Opcode == ARM::INLINEASM)
1650 AddrMode = ARMII::AddrMode2;
1652 if (Opcode == ARM::ADDri) {
1653 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1655 // Turn it into a move.
1656 MI.setDesc(TII.get(ARM::MOVr));
1657 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1658 MI.RemoveOperand(FrameRegIdx+1);
1661 } else if (Offset < 0) {
1664 MI.setDesc(TII.get(ARM::SUBri));
1667 // Common case: small offset, fits into instruction.
1668 if (ARM_AM::getSOImmVal(Offset) != -1) {
1669 // Replace the FrameIndex with sp / fp
1670 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1671 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1676 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1678 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1679 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1681 // We will handle these bits from offset, clear them.
1682 Offset &= ~ThisImmVal;
1684 // Get the properly encoded SOImmVal field.
1685 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1686 "Bit extraction didn't work?");
1687 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1689 unsigned ImmIdx = 0;
1691 unsigned NumBits = 0;
1694 case ARMII::AddrMode_i12: {
1695 ImmIdx = FrameRegIdx + 1;
1696 InstrOffs = MI.getOperand(ImmIdx).getImm();
1700 case ARMII::AddrMode2: {
1701 ImmIdx = FrameRegIdx+2;
1702 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1703 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1708 case ARMII::AddrMode3: {
1709 ImmIdx = FrameRegIdx+2;
1710 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1711 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1716 case ARMII::AddrMode4:
1717 case ARMII::AddrMode6:
1718 // Can't fold any offset even if it's zero.
1720 case ARMII::AddrMode5: {
1721 ImmIdx = FrameRegIdx+1;
1722 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1723 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1730 llvm_unreachable("Unsupported addressing mode!");
1733 Offset += InstrOffs * Scale;
1734 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1740 // Attempt to fold address comp. if opcode has offset bits
1742 // Common case: small offset, fits into instruction.
1743 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1744 int ImmedOffset = Offset / Scale;
1745 unsigned Mask = (1 << NumBits) - 1;
1746 if ((unsigned)Offset <= Mask * Scale) {
1747 // Replace the FrameIndex with sp
1748 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1749 // FIXME: When addrmode2 goes away, this will simplify (like the
1750 // T2 version), as the LDR.i12 versions don't need the encoding
1751 // tricks for the offset value.
1753 if (AddrMode == ARMII::AddrMode_i12)
1754 ImmedOffset = -ImmedOffset;
1756 ImmedOffset |= 1 << NumBits;
1758 ImmOp.ChangeToImmediate(ImmedOffset);
1763 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1764 ImmedOffset = ImmedOffset & Mask;
1766 if (AddrMode == ARMII::AddrMode_i12)
1767 ImmedOffset = -ImmedOffset;
1769 ImmedOffset |= 1 << NumBits;
1771 ImmOp.ChangeToImmediate(ImmedOffset);
1772 Offset &= ~(Mask*Scale);
1776 Offset = (isSub) ? -Offset : Offset;
1780 /// analyzeCompare - For a comparison instruction, return the source registers
1781 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1782 /// compares against in CmpValue. Return true if the comparison instruction
1783 /// can be analyzed.
1784 bool ARMBaseInstrInfo::
1785 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1786 int &CmpMask, int &CmpValue) const {
1787 switch (MI->getOpcode()) {
1791 SrcReg = MI->getOperand(0).getReg();
1794 CmpValue = MI->getOperand(1).getImm();
1798 SrcReg = MI->getOperand(0).getReg();
1799 SrcReg2 = MI->getOperand(1).getReg();
1805 SrcReg = MI->getOperand(0).getReg();
1807 CmpMask = MI->getOperand(1).getImm();
1815 /// isSuitableForMask - Identify a suitable 'and' instruction that
1816 /// operates on the given source register and applies the same mask
1817 /// as a 'tst' instruction. Provide a limited look-through for copies.
1818 /// When successful, MI will hold the found instruction.
1819 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1820 int CmpMask, bool CommonUse) {
1821 switch (MI->getOpcode()) {
1824 if (CmpMask != MI->getOperand(2).getImm())
1826 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1830 // Walk down one instruction which is potentially an 'and'.
1831 const MachineInstr &Copy = *MI;
1832 MachineBasicBlock::iterator AND(
1833 llvm::next(MachineBasicBlock::iterator(MI)));
1834 if (AND == MI->getParent()->end()) return false;
1836 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1844 /// getSwappedCondition - assume the flags are set by MI(a,b), return
1845 /// the condition code if we modify the instructions such that flags are
1847 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
1849 default: return ARMCC::AL;
1850 case ARMCC::EQ: return ARMCC::EQ;
1851 case ARMCC::NE: return ARMCC::NE;
1852 case ARMCC::HS: return ARMCC::LS;
1853 case ARMCC::LO: return ARMCC::HI;
1854 case ARMCC::HI: return ARMCC::LO;
1855 case ARMCC::LS: return ARMCC::HS;
1856 case ARMCC::GE: return ARMCC::LE;
1857 case ARMCC::LT: return ARMCC::GT;
1858 case ARMCC::GT: return ARMCC::LT;
1859 case ARMCC::LE: return ARMCC::GE;
1863 /// isRedundantFlagInstr - check whether the first instruction, whose only
1864 /// purpose is to update flags, can be made redundant.
1865 /// CMPrr can be made redundant by SUBrr if the operands are the same.
1866 /// CMPri can be made redundant by SUBri if the operands are the same.
1867 /// This function can be extended later on.
1868 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
1869 unsigned SrcReg2, int ImmValue,
1871 if ((CmpI->getOpcode() == ARM::CMPrr ||
1872 CmpI->getOpcode() == ARM::t2CMPrr) &&
1873 (OI->getOpcode() == ARM::SUBrr ||
1874 OI->getOpcode() == ARM::t2SUBrr) &&
1875 ((OI->getOperand(1).getReg() == SrcReg &&
1876 OI->getOperand(2).getReg() == SrcReg2) ||
1877 (OI->getOperand(1).getReg() == SrcReg2 &&
1878 OI->getOperand(2).getReg() == SrcReg)))
1881 if ((CmpI->getOpcode() == ARM::CMPri ||
1882 CmpI->getOpcode() == ARM::t2CMPri) &&
1883 (OI->getOpcode() == ARM::SUBri ||
1884 OI->getOpcode() == ARM::t2SUBri) &&
1885 OI->getOperand(1).getReg() == SrcReg &&
1886 OI->getOperand(2).getImm() == ImmValue)
1891 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
1892 /// comparison into one that sets the zero bit in the flags register;
1893 /// Remove a redundant Compare instruction if an earlier instruction can set the
1894 /// flags in the same way as Compare.
1895 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
1896 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
1897 /// condition code of instructions which use the flags.
1898 bool ARMBaseInstrInfo::
1899 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
1900 int CmpMask, int CmpValue,
1901 const MachineRegisterInfo *MRI) const {
1902 // Get the unique definition of SrcReg.
1903 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1904 if (!MI) return false;
1906 // Masked compares sometimes use the same register as the corresponding 'and'.
1907 if (CmpMask != ~0) {
1908 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1910 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1911 UE = MRI->use_end(); UI != UE; ++UI) {
1912 if (UI->getParent() != CmpInstr->getParent()) continue;
1913 MachineInstr *PotentialAND = &*UI;
1914 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1919 if (!MI) return false;
1923 // Get ready to iterate backward from CmpInstr.
1924 MachineBasicBlock::iterator I = CmpInstr, E = MI,
1925 B = CmpInstr->getParent()->begin();
1927 // Early exit if CmpInstr is at the beginning of the BB.
1928 if (I == B) return false;
1930 // There are two possible candidates which can be changed to set CPSR:
1931 // One is MI, the other is a SUB instruction.
1932 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1933 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
1934 MachineInstr *Sub = NULL;
1936 // MI is not a candidate for CMPrr.
1938 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
1939 // Conservatively refuse to convert an instruction which isn't in the same
1940 // BB as the comparison.
1941 // For CMPri, we need to check Sub, thus we can't return here.
1942 if (CmpInstr->getOpcode() == ARM::CMPri ||
1943 CmpInstr->getOpcode() == ARM::t2CMPri)
1949 // Check that CPSR isn't set between the comparison instruction and the one we
1950 // want to change. At the same time, search for Sub.
1951 const TargetRegisterInfo *TRI = &getRegisterInfo();
1953 for (; I != E; --I) {
1954 const MachineInstr &Instr = *I;
1956 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
1957 Instr.readsRegister(ARM::CPSR, TRI))
1958 // This instruction modifies or uses CPSR after the one we want to
1959 // change. We can't do this transformation.
1962 // Check whether CmpInstr can be made redundant by the current instruction.
1963 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
1969 // The 'and' is below the comparison instruction.
1973 // Return false if no candidates exist.
1977 // The single candidate is called MI.
1980 switch (MI->getOpcode()) {
2014 case ARM::t2EORri: {
2015 // Scan forward for the use of CPSR
2016 // When checking against MI: if it's a conditional code requires
2017 // checking of V bit, then this is not safe to do.
2018 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2019 // If we are done with the basic block, we need to check whether CPSR is
2021 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2023 bool isSafe = false;
2025 E = CmpInstr->getParent()->end();
2026 while (!isSafe && ++I != E) {
2027 const MachineInstr &Instr = *I;
2028 for (unsigned IO = 0, EO = Instr.getNumOperands();
2029 !isSafe && IO != EO; ++IO) {
2030 const MachineOperand &MO = Instr.getOperand(IO);
2031 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2035 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2041 // Condition code is after the operand before CPSR.
2042 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2044 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2045 if (NewCC == ARMCC::AL)
2047 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2048 // on CMP needs to be updated to be based on SUB.
2049 // Push the condition code operands to OperandsToUpdate.
2050 // If it is safe to remove CmpInstr, the condition code of these
2051 // operands will be modified.
2052 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2053 Sub->getOperand(2).getReg() == SrcReg)
2054 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2060 // CPSR can be used multiple times, we should continue.
2073 // If CPSR is not killed nor re-defined, we should check whether it is
2074 // live-out. If it is live-out, do not optimize.
2076 MachineBasicBlock *MBB = CmpInstr->getParent();
2077 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2078 SE = MBB->succ_end(); SI != SE; ++SI)
2079 if ((*SI)->isLiveIn(ARM::CPSR))
2083 // Toggle the optional operand to CPSR.
2084 MI->getOperand(5).setReg(ARM::CPSR);
2085 MI->getOperand(5).setIsDef(true);
2086 CmpInstr->eraseFromParent();
2088 // Modify the condition code of operands in OperandsToUpdate.
2089 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2090 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2091 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2092 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2100 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2101 MachineInstr *DefMI, unsigned Reg,
2102 MachineRegisterInfo *MRI) const {
2103 // Fold large immediates into add, sub, or, xor.
2104 unsigned DefOpc = DefMI->getOpcode();
2105 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2107 if (!DefMI->getOperand(1).isImm())
2108 // Could be t2MOVi32imm <ga:xx>
2111 if (!MRI->hasOneNonDBGUse(Reg))
2114 const MCInstrDesc &DefMCID = DefMI->getDesc();
2115 if (DefMCID.hasOptionalDef()) {
2116 unsigned NumOps = DefMCID.getNumOperands();
2117 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2118 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2119 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2124 const MCInstrDesc &UseMCID = UseMI->getDesc();
2125 if (UseMCID.hasOptionalDef()) {
2126 unsigned NumOps = UseMCID.getNumOperands();
2127 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2128 // If the instruction sets the flag, do not attempt this optimization
2129 // since it may change the semantics of the code.
2133 unsigned UseOpc = UseMI->getOpcode();
2134 unsigned NewUseOpc = 0;
2135 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2136 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2137 bool Commute = false;
2139 default: return false;
2147 case ARM::t2EORrr: {
2148 Commute = UseMI->getOperand(2).getReg() != Reg;
2155 NewUseOpc = ARM::SUBri;
2161 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2163 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2164 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2167 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2168 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2169 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2173 case ARM::t2SUBrr: {
2177 NewUseOpc = ARM::t2SUBri;
2182 case ARM::t2EORrr: {
2183 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2185 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2186 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2189 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2190 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2191 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2199 unsigned OpIdx = Commute ? 2 : 1;
2200 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2201 bool isKill = UseMI->getOperand(OpIdx).isKill();
2202 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2203 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2204 UseMI, UseMI->getDebugLoc(),
2205 get(NewUseOpc), NewReg)
2206 .addReg(Reg1, getKillRegState(isKill))
2207 .addImm(SOImmValV1)));
2208 UseMI->setDesc(get(NewUseOpc));
2209 UseMI->getOperand(1).setReg(NewReg);
2210 UseMI->getOperand(1).setIsKill();
2211 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2212 DefMI->eraseFromParent();
2217 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2218 const MachineInstr *MI) const {
2219 if (!ItinData || ItinData->isEmpty())
2222 const MCInstrDesc &Desc = MI->getDesc();
2223 unsigned Class = Desc.getSchedClass();
2224 int ItinUOps = ItinData->getNumMicroOps(Class);
2228 unsigned Opc = MI->getOpcode();
2231 llvm_unreachable("Unexpected multi-uops instruction!");
2236 // The number of uOps for load / store multiple are determined by the number
2239 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2240 // same cycle. The scheduling for the first load / store must be done
2241 // separately by assuming the address is not 64-bit aligned.
2243 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2244 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2245 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2247 case ARM::VLDMDIA_UPD:
2248 case ARM::VLDMDDB_UPD:
2250 case ARM::VLDMSIA_UPD:
2251 case ARM::VLDMSDB_UPD:
2253 case ARM::VSTMDIA_UPD:
2254 case ARM::VSTMDDB_UPD:
2256 case ARM::VSTMSIA_UPD:
2257 case ARM::VSTMSDB_UPD: {
2258 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2259 return (NumRegs / 2) + (NumRegs % 2) + 1;
2262 case ARM::LDMIA_RET:
2267 case ARM::LDMIA_UPD:
2268 case ARM::LDMDA_UPD:
2269 case ARM::LDMDB_UPD:
2270 case ARM::LDMIB_UPD:
2275 case ARM::STMIA_UPD:
2276 case ARM::STMDA_UPD:
2277 case ARM::STMDB_UPD:
2278 case ARM::STMIB_UPD:
2280 case ARM::tLDMIA_UPD:
2281 case ARM::tSTMIA_UPD:
2285 case ARM::t2LDMIA_RET:
2288 case ARM::t2LDMIA_UPD:
2289 case ARM::t2LDMDB_UPD:
2292 case ARM::t2STMIA_UPD:
2293 case ARM::t2STMDB_UPD: {
2294 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2295 if (Subtarget.isCortexA8()) {
2298 // 4 registers would be issued: 2, 2.
2299 // 5 registers would be issued: 2, 2, 1.
2300 int A8UOps = (NumRegs / 2);
2304 } else if (Subtarget.isCortexA9()) {
2305 int A9UOps = (NumRegs / 2);
2306 // If there are odd number of registers or if it's not 64-bit aligned,
2307 // then it takes an extra AGU (Address Generation Unit) cycle.
2308 if ((NumRegs % 2) ||
2309 !MI->hasOneMemOperand() ||
2310 (*MI->memoperands_begin())->getAlignment() < 8)
2314 // Assume the worst.
2322 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2323 const MCInstrDesc &DefMCID,
2325 unsigned DefIdx, unsigned DefAlign) const {
2326 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2328 // Def is the address writeback.
2329 return ItinData->getOperandCycle(DefClass, DefIdx);
2332 if (Subtarget.isCortexA8()) {
2333 // (regno / 2) + (regno % 2) + 1
2334 DefCycle = RegNo / 2 + 1;
2337 } else if (Subtarget.isCortexA9()) {
2339 bool isSLoad = false;
2341 switch (DefMCID.getOpcode()) {
2344 case ARM::VLDMSIA_UPD:
2345 case ARM::VLDMSDB_UPD:
2350 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2351 // then it takes an extra cycle.
2352 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2355 // Assume the worst.
2356 DefCycle = RegNo + 2;
2363 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2364 const MCInstrDesc &DefMCID,
2366 unsigned DefIdx, unsigned DefAlign) const {
2367 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2369 // Def is the address writeback.
2370 return ItinData->getOperandCycle(DefClass, DefIdx);
2373 if (Subtarget.isCortexA8()) {
2374 // 4 registers would be issued: 1, 2, 1.
2375 // 5 registers would be issued: 1, 2, 2.
2376 DefCycle = RegNo / 2;
2379 // Result latency is issue cycle + 2: E2.
2381 } else if (Subtarget.isCortexA9()) {
2382 DefCycle = (RegNo / 2);
2383 // If there are odd number of registers or if it's not 64-bit aligned,
2384 // then it takes an extra AGU (Address Generation Unit) cycle.
2385 if ((RegNo % 2) || DefAlign < 8)
2387 // Result latency is AGU cycles + 2.
2390 // Assume the worst.
2391 DefCycle = RegNo + 2;
2398 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2399 const MCInstrDesc &UseMCID,
2401 unsigned UseIdx, unsigned UseAlign) const {
2402 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2404 return ItinData->getOperandCycle(UseClass, UseIdx);
2407 if (Subtarget.isCortexA8()) {
2408 // (regno / 2) + (regno % 2) + 1
2409 UseCycle = RegNo / 2 + 1;
2412 } else if (Subtarget.isCortexA9()) {
2414 bool isSStore = false;
2416 switch (UseMCID.getOpcode()) {
2419 case ARM::VSTMSIA_UPD:
2420 case ARM::VSTMSDB_UPD:
2425 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2426 // then it takes an extra cycle.
2427 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2430 // Assume the worst.
2431 UseCycle = RegNo + 2;
2438 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2439 const MCInstrDesc &UseMCID,
2441 unsigned UseIdx, unsigned UseAlign) const {
2442 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2444 return ItinData->getOperandCycle(UseClass, UseIdx);
2447 if (Subtarget.isCortexA8()) {
2448 UseCycle = RegNo / 2;
2453 } else if (Subtarget.isCortexA9()) {
2454 UseCycle = (RegNo / 2);
2455 // If there are odd number of registers or if it's not 64-bit aligned,
2456 // then it takes an extra AGU (Address Generation Unit) cycle.
2457 if ((RegNo % 2) || UseAlign < 8)
2460 // Assume the worst.
2467 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2468 const MCInstrDesc &DefMCID,
2469 unsigned DefIdx, unsigned DefAlign,
2470 const MCInstrDesc &UseMCID,
2471 unsigned UseIdx, unsigned UseAlign) const {
2472 unsigned DefClass = DefMCID.getSchedClass();
2473 unsigned UseClass = UseMCID.getSchedClass();
2475 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2476 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2478 // This may be a def / use of a variable_ops instruction, the operand
2479 // latency might be determinable dynamically. Let the target try to
2482 bool LdmBypass = false;
2483 switch (DefMCID.getOpcode()) {
2485 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2489 case ARM::VLDMDIA_UPD:
2490 case ARM::VLDMDDB_UPD:
2492 case ARM::VLDMSIA_UPD:
2493 case ARM::VLDMSDB_UPD:
2494 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2497 case ARM::LDMIA_RET:
2502 case ARM::LDMIA_UPD:
2503 case ARM::LDMDA_UPD:
2504 case ARM::LDMDB_UPD:
2505 case ARM::LDMIB_UPD:
2507 case ARM::tLDMIA_UPD:
2509 case ARM::t2LDMIA_RET:
2512 case ARM::t2LDMIA_UPD:
2513 case ARM::t2LDMDB_UPD:
2515 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2520 // We can't seem to determine the result latency of the def, assume it's 2.
2524 switch (UseMCID.getOpcode()) {
2526 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2530 case ARM::VSTMDIA_UPD:
2531 case ARM::VSTMDDB_UPD:
2533 case ARM::VSTMSIA_UPD:
2534 case ARM::VSTMSDB_UPD:
2535 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2542 case ARM::STMIA_UPD:
2543 case ARM::STMDA_UPD:
2544 case ARM::STMDB_UPD:
2545 case ARM::STMIB_UPD:
2546 case ARM::tSTMIA_UPD:
2551 case ARM::t2STMIA_UPD:
2552 case ARM::t2STMDB_UPD:
2553 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2558 // Assume it's read in the first stage.
2561 UseCycle = DefCycle - UseCycle + 1;
2564 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2565 // first def operand.
2566 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2569 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2570 UseClass, UseIdx)) {
2578 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2579 const MachineInstr *MI, unsigned Reg,
2580 unsigned &DefIdx, unsigned &Dist) {
2583 MachineBasicBlock::const_iterator I = MI; ++I;
2584 MachineBasicBlock::const_instr_iterator II =
2585 llvm::prior(I.getInstrIterator());
2586 assert(II->isInsideBundle() && "Empty bundle?");
2589 while (II->isInsideBundle()) {
2590 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2597 assert(Idx != -1 && "Cannot find bundled definition!");
2602 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2603 const MachineInstr *MI, unsigned Reg,
2604 unsigned &UseIdx, unsigned &Dist) {
2607 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2608 assert(II->isInsideBundle() && "Empty bundle?");
2609 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2611 // FIXME: This doesn't properly handle multiple uses.
2613 while (II != E && II->isInsideBundle()) {
2614 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2617 if (II->getOpcode() != ARM::t2IT)
2631 /// Return the number of cycles to add to (or subtract from) the static
2632 /// itinerary based on the def opcode and alignment. The caller will ensure that
2633 /// adjusted latency is at least one cycle.
2634 static int adjustDefLatency(const ARMSubtarget &Subtarget,
2635 const MachineInstr *DefMI,
2636 const MCInstrDesc *DefMCID, unsigned DefAlign) {
2638 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) {
2639 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2640 // variants are one cycle cheaper.
2641 switch (DefMCID->getOpcode()) {
2645 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2646 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2648 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2655 case ARM::t2LDRSHs: {
2656 // Thumb2 mode: lsl only.
2657 unsigned ShAmt = DefMI->getOperand(3).getImm();
2658 if (ShAmt == 0 || ShAmt == 2)
2665 if (DefAlign < 8 && Subtarget.isCortexA9()) {
2666 switch (DefMCID->getOpcode()) {
2672 case ARM::VLD1q8wb_fixed:
2673 case ARM::VLD1q16wb_fixed:
2674 case ARM::VLD1q32wb_fixed:
2675 case ARM::VLD1q64wb_fixed:
2676 case ARM::VLD1q8wb_register:
2677 case ARM::VLD1q16wb_register:
2678 case ARM::VLD1q32wb_register:
2679 case ARM::VLD1q64wb_register:
2686 case ARM::VLD2d8wb_fixed:
2687 case ARM::VLD2d16wb_fixed:
2688 case ARM::VLD2d32wb_fixed:
2689 case ARM::VLD2q8wb_fixed:
2690 case ARM::VLD2q16wb_fixed:
2691 case ARM::VLD2q32wb_fixed:
2692 case ARM::VLD2d8wb_register:
2693 case ARM::VLD2d16wb_register:
2694 case ARM::VLD2d32wb_register:
2695 case ARM::VLD2q8wb_register:
2696 case ARM::VLD2q16wb_register:
2697 case ARM::VLD2q32wb_register:
2702 case ARM::VLD3d8_UPD:
2703 case ARM::VLD3d16_UPD:
2704 case ARM::VLD3d32_UPD:
2705 case ARM::VLD1d64Twb_fixed:
2706 case ARM::VLD1d64Twb_register:
2707 case ARM::VLD3q8_UPD:
2708 case ARM::VLD3q16_UPD:
2709 case ARM::VLD3q32_UPD:
2714 case ARM::VLD4d8_UPD:
2715 case ARM::VLD4d16_UPD:
2716 case ARM::VLD4d32_UPD:
2717 case ARM::VLD1d64Qwb_fixed:
2718 case ARM::VLD1d64Qwb_register:
2719 case ARM::VLD4q8_UPD:
2720 case ARM::VLD4q16_UPD:
2721 case ARM::VLD4q32_UPD:
2722 case ARM::VLD1DUPq8:
2723 case ARM::VLD1DUPq16:
2724 case ARM::VLD1DUPq32:
2725 case ARM::VLD1DUPq8wb_fixed:
2726 case ARM::VLD1DUPq16wb_fixed:
2727 case ARM::VLD1DUPq32wb_fixed:
2728 case ARM::VLD1DUPq8wb_register:
2729 case ARM::VLD1DUPq16wb_register:
2730 case ARM::VLD1DUPq32wb_register:
2731 case ARM::VLD2DUPd8:
2732 case ARM::VLD2DUPd16:
2733 case ARM::VLD2DUPd32:
2734 case ARM::VLD2DUPd8wb_fixed:
2735 case ARM::VLD2DUPd16wb_fixed:
2736 case ARM::VLD2DUPd32wb_fixed:
2737 case ARM::VLD2DUPd8wb_register:
2738 case ARM::VLD2DUPd16wb_register:
2739 case ARM::VLD2DUPd32wb_register:
2740 case ARM::VLD4DUPd8:
2741 case ARM::VLD4DUPd16:
2742 case ARM::VLD4DUPd32:
2743 case ARM::VLD4DUPd8_UPD:
2744 case ARM::VLD4DUPd16_UPD:
2745 case ARM::VLD4DUPd32_UPD:
2747 case ARM::VLD1LNd16:
2748 case ARM::VLD1LNd32:
2749 case ARM::VLD1LNd8_UPD:
2750 case ARM::VLD1LNd16_UPD:
2751 case ARM::VLD1LNd32_UPD:
2753 case ARM::VLD2LNd16:
2754 case ARM::VLD2LNd32:
2755 case ARM::VLD2LNq16:
2756 case ARM::VLD2LNq32:
2757 case ARM::VLD2LNd8_UPD:
2758 case ARM::VLD2LNd16_UPD:
2759 case ARM::VLD2LNd32_UPD:
2760 case ARM::VLD2LNq16_UPD:
2761 case ARM::VLD2LNq32_UPD:
2763 case ARM::VLD4LNd16:
2764 case ARM::VLD4LNd32:
2765 case ARM::VLD4LNq16:
2766 case ARM::VLD4LNq32:
2767 case ARM::VLD4LNd8_UPD:
2768 case ARM::VLD4LNd16_UPD:
2769 case ARM::VLD4LNd32_UPD:
2770 case ARM::VLD4LNq16_UPD:
2771 case ARM::VLD4LNq32_UPD:
2772 // If the address is not 64-bit aligned, the latencies of these
2773 // instructions increases by one.
2784 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2785 const MachineInstr *DefMI, unsigned DefIdx,
2786 const MachineInstr *UseMI,
2787 unsigned UseIdx) const {
2788 // No operand latency. The caller may fall back to getInstrLatency.
2789 if (!ItinData || ItinData->isEmpty())
2792 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2793 unsigned Reg = DefMO.getReg();
2794 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2795 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2797 unsigned DefAdj = 0;
2798 if (DefMI->isBundle()) {
2799 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2800 DefMCID = &DefMI->getDesc();
2802 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2803 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
2807 unsigned UseAdj = 0;
2808 if (UseMI->isBundle()) {
2810 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2811 Reg, NewUseIdx, UseAdj);
2817 UseMCID = &UseMI->getDesc();
2820 if (Reg == ARM::CPSR) {
2821 if (DefMI->getOpcode() == ARM::FMSTAT) {
2822 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2823 return Subtarget.isCortexA9() ? 1 : 20;
2826 // CPSR set and branch can be paired in the same cycle.
2827 if (UseMI->isBranch())
2830 // Otherwise it takes the instruction latency (generally one).
2831 unsigned Latency = getInstrLatency(ItinData, DefMI);
2833 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2834 // its uses. Instructions which are otherwise scheduled between them may
2835 // incur a code size penalty (not able to use the CPSR setting 16-bit
2837 if (Latency > 0 && Subtarget.isThumb2()) {
2838 const MachineFunction *MF = DefMI->getParent()->getParent();
2839 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2845 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
2848 unsigned DefAlign = DefMI->hasOneMemOperand()
2849 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2850 unsigned UseAlign = UseMI->hasOneMemOperand()
2851 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2853 // Get the itinerary's latency if possible, and handle variable_ops.
2854 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2855 *UseMCID, UseIdx, UseAlign);
2856 // Unable to find operand latency. The caller may resort to getInstrLatency.
2860 // Adjust for IT block position.
2861 int Adj = DefAdj + UseAdj;
2863 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
2864 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
2865 if (Adj >= 0 || (int)Latency > -Adj) {
2866 return Latency + Adj;
2868 // Return the itinerary latency, which may be zero but not less than zero.
2873 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2874 SDNode *DefNode, unsigned DefIdx,
2875 SDNode *UseNode, unsigned UseIdx) const {
2876 if (!DefNode->isMachineOpcode())
2879 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2881 if (isZeroCost(DefMCID.Opcode))
2884 if (!ItinData || ItinData->isEmpty())
2885 return DefMCID.mayLoad() ? 3 : 1;
2887 if (!UseNode->isMachineOpcode()) {
2888 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2889 if (Subtarget.isCortexA9())
2890 return Latency <= 2 ? 1 : Latency - 1;
2892 return Latency <= 3 ? 1 : Latency - 2;
2895 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2896 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2897 unsigned DefAlign = !DefMN->memoperands_empty()
2898 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2899 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2900 unsigned UseAlign = !UseMN->memoperands_empty()
2901 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2902 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2903 UseMCID, UseIdx, UseAlign);
2906 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2907 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2908 // variants are one cycle cheaper.
2909 switch (DefMCID.getOpcode()) {
2914 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2915 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2917 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2924 case ARM::t2LDRSHs: {
2925 // Thumb2 mode: lsl only.
2927 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2928 if (ShAmt == 0 || ShAmt == 2)
2935 if (DefAlign < 8 && Subtarget.isCortexA9())
2936 switch (DefMCID.getOpcode()) {
2942 case ARM::VLD1q8wb_register:
2943 case ARM::VLD1q16wb_register:
2944 case ARM::VLD1q32wb_register:
2945 case ARM::VLD1q64wb_register:
2946 case ARM::VLD1q8wb_fixed:
2947 case ARM::VLD1q16wb_fixed:
2948 case ARM::VLD1q32wb_fixed:
2949 case ARM::VLD1q64wb_fixed:
2953 case ARM::VLD2q8Pseudo:
2954 case ARM::VLD2q16Pseudo:
2955 case ARM::VLD2q32Pseudo:
2956 case ARM::VLD2d8wb_fixed:
2957 case ARM::VLD2d16wb_fixed:
2958 case ARM::VLD2d32wb_fixed:
2959 case ARM::VLD2q8PseudoWB_fixed:
2960 case ARM::VLD2q16PseudoWB_fixed:
2961 case ARM::VLD2q32PseudoWB_fixed:
2962 case ARM::VLD2d8wb_register:
2963 case ARM::VLD2d16wb_register:
2964 case ARM::VLD2d32wb_register:
2965 case ARM::VLD2q8PseudoWB_register:
2966 case ARM::VLD2q16PseudoWB_register:
2967 case ARM::VLD2q32PseudoWB_register:
2968 case ARM::VLD3d8Pseudo:
2969 case ARM::VLD3d16Pseudo:
2970 case ARM::VLD3d32Pseudo:
2971 case ARM::VLD1d64TPseudo:
2972 case ARM::VLD3d8Pseudo_UPD:
2973 case ARM::VLD3d16Pseudo_UPD:
2974 case ARM::VLD3d32Pseudo_UPD:
2975 case ARM::VLD3q8Pseudo_UPD:
2976 case ARM::VLD3q16Pseudo_UPD:
2977 case ARM::VLD3q32Pseudo_UPD:
2978 case ARM::VLD3q8oddPseudo:
2979 case ARM::VLD3q16oddPseudo:
2980 case ARM::VLD3q32oddPseudo:
2981 case ARM::VLD3q8oddPseudo_UPD:
2982 case ARM::VLD3q16oddPseudo_UPD:
2983 case ARM::VLD3q32oddPseudo_UPD:
2984 case ARM::VLD4d8Pseudo:
2985 case ARM::VLD4d16Pseudo:
2986 case ARM::VLD4d32Pseudo:
2987 case ARM::VLD1d64QPseudo:
2988 case ARM::VLD4d8Pseudo_UPD:
2989 case ARM::VLD4d16Pseudo_UPD:
2990 case ARM::VLD4d32Pseudo_UPD:
2991 case ARM::VLD4q8Pseudo_UPD:
2992 case ARM::VLD4q16Pseudo_UPD:
2993 case ARM::VLD4q32Pseudo_UPD:
2994 case ARM::VLD4q8oddPseudo:
2995 case ARM::VLD4q16oddPseudo:
2996 case ARM::VLD4q32oddPseudo:
2997 case ARM::VLD4q8oddPseudo_UPD:
2998 case ARM::VLD4q16oddPseudo_UPD:
2999 case ARM::VLD4q32oddPseudo_UPD:
3000 case ARM::VLD1DUPq8:
3001 case ARM::VLD1DUPq16:
3002 case ARM::VLD1DUPq32:
3003 case ARM::VLD1DUPq8wb_fixed:
3004 case ARM::VLD1DUPq16wb_fixed:
3005 case ARM::VLD1DUPq32wb_fixed:
3006 case ARM::VLD1DUPq8wb_register:
3007 case ARM::VLD1DUPq16wb_register:
3008 case ARM::VLD1DUPq32wb_register:
3009 case ARM::VLD2DUPd8:
3010 case ARM::VLD2DUPd16:
3011 case ARM::VLD2DUPd32:
3012 case ARM::VLD2DUPd8wb_fixed:
3013 case ARM::VLD2DUPd16wb_fixed:
3014 case ARM::VLD2DUPd32wb_fixed:
3015 case ARM::VLD2DUPd8wb_register:
3016 case ARM::VLD2DUPd16wb_register:
3017 case ARM::VLD2DUPd32wb_register:
3018 case ARM::VLD4DUPd8Pseudo:
3019 case ARM::VLD4DUPd16Pseudo:
3020 case ARM::VLD4DUPd32Pseudo:
3021 case ARM::VLD4DUPd8Pseudo_UPD:
3022 case ARM::VLD4DUPd16Pseudo_UPD:
3023 case ARM::VLD4DUPd32Pseudo_UPD:
3024 case ARM::VLD1LNq8Pseudo:
3025 case ARM::VLD1LNq16Pseudo:
3026 case ARM::VLD1LNq32Pseudo:
3027 case ARM::VLD1LNq8Pseudo_UPD:
3028 case ARM::VLD1LNq16Pseudo_UPD:
3029 case ARM::VLD1LNq32Pseudo_UPD:
3030 case ARM::VLD2LNd8Pseudo:
3031 case ARM::VLD2LNd16Pseudo:
3032 case ARM::VLD2LNd32Pseudo:
3033 case ARM::VLD2LNq16Pseudo:
3034 case ARM::VLD2LNq32Pseudo:
3035 case ARM::VLD2LNd8Pseudo_UPD:
3036 case ARM::VLD2LNd16Pseudo_UPD:
3037 case ARM::VLD2LNd32Pseudo_UPD:
3038 case ARM::VLD2LNq16Pseudo_UPD:
3039 case ARM::VLD2LNq32Pseudo_UPD:
3040 case ARM::VLD4LNd8Pseudo:
3041 case ARM::VLD4LNd16Pseudo:
3042 case ARM::VLD4LNd32Pseudo:
3043 case ARM::VLD4LNq16Pseudo:
3044 case ARM::VLD4LNq32Pseudo:
3045 case ARM::VLD4LNd8Pseudo_UPD:
3046 case ARM::VLD4LNd16Pseudo_UPD:
3047 case ARM::VLD4LNd32Pseudo_UPD:
3048 case ARM::VLD4LNq16Pseudo_UPD:
3049 case ARM::VLD4LNq32Pseudo_UPD:
3050 // If the address is not 64-bit aligned, the latencies of these
3051 // instructions increases by one.
3060 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
3061 const MachineInstr *DefMI, unsigned DefIdx,
3062 const MachineInstr *DepMI) const {
3063 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
3064 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
3067 // If the second MI is predicated, then there is an implicit use dependency.
3068 return getInstrLatency(ItinData, DefMI);
3071 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3072 const MachineInstr *MI,
3073 unsigned *PredCost) const {
3074 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3075 MI->isRegSequence() || MI->isImplicitDef())
3078 // An instruction scheduler typically runs on unbundled instructions, however
3079 // other passes may query the latency of a bundled instruction.
3080 if (MI->isBundle()) {
3081 unsigned Latency = 0;
3082 MachineBasicBlock::const_instr_iterator I = MI;
3083 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3084 while (++I != E && I->isInsideBundle()) {
3085 if (I->getOpcode() != ARM::t2IT)
3086 Latency += getInstrLatency(ItinData, I, PredCost);
3091 const MCInstrDesc &MCID = MI->getDesc();
3092 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3093 // When predicated, CPSR is an additional source operand for CPSR updating
3094 // instructions, this apparently increases their latencies.
3097 // Be sure to call getStageLatency for an empty itinerary in case it has a
3098 // valid MinLatency property.
3100 return MI->mayLoad() ? 3 : 1;
3102 unsigned Class = MCID.getSchedClass();
3104 // For instructions with variable uops, use uops as latency.
3105 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3106 return getNumMicroOps(ItinData, MI);
3108 // For the common case, fall back on the itinerary's latency.
3109 unsigned Latency = ItinData->getStageLatency(Class);
3111 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3112 unsigned DefAlign = MI->hasOneMemOperand()
3113 ? (*MI->memoperands_begin())->getAlignment() : 0;
3114 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3115 if (Adj >= 0 || (int)Latency > -Adj) {
3116 return Latency + Adj;
3121 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3122 SDNode *Node) const {
3123 if (!Node->isMachineOpcode())
3126 if (!ItinData || ItinData->isEmpty())
3129 unsigned Opcode = Node->getMachineOpcode();
3132 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3139 bool ARMBaseInstrInfo::
3140 hasHighOperandLatency(const InstrItineraryData *ItinData,
3141 const MachineRegisterInfo *MRI,
3142 const MachineInstr *DefMI, unsigned DefIdx,
3143 const MachineInstr *UseMI, unsigned UseIdx) const {
3144 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3145 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3146 if (Subtarget.isCortexA8() &&
3147 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3148 // CortexA8 VFP instructions are not pipelined.
3151 // Hoist VFP / NEON instructions with 4 or higher latency.
3152 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3155 Latency = getInstrLatency(ItinData, DefMI);
3158 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3159 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3162 bool ARMBaseInstrInfo::
3163 hasLowDefLatency(const InstrItineraryData *ItinData,
3164 const MachineInstr *DefMI, unsigned DefIdx) const {
3165 if (!ItinData || ItinData->isEmpty())
3168 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3169 if (DDomain == ARMII::DomainGeneral) {
3170 unsigned DefClass = DefMI->getDesc().getSchedClass();
3171 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3172 return (DefCycle != -1 && DefCycle <= 2);
3177 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3178 StringRef &ErrInfo) const {
3179 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3180 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3187 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3188 unsigned &AddSubOpc,
3189 bool &NegAcc, bool &HasLane) const {
3190 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3191 if (I == MLxEntryMap.end())
3194 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3195 MulOpc = Entry.MulOpc;
3196 AddSubOpc = Entry.AddSubOpc;
3197 NegAcc = Entry.NegAcc;
3198 HasLane = Entry.HasLane;
3202 //===----------------------------------------------------------------------===//
3203 // Execution domains.
3204 //===----------------------------------------------------------------------===//
3206 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3207 // and some can go down both. The vmov instructions go down the VFP pipeline,
3208 // but they can be changed to vorr equivalents that are executed by the NEON
3211 // We use the following execution domain numbering:
3219 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3221 std::pair<uint16_t, uint16_t>
3222 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3223 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
3225 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3226 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3228 // No other instructions can be swizzled, so just determine their domain.
3229 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3231 if (Domain & ARMII::DomainNEON)
3232 return std::make_pair(ExeNEON, 0);
3234 // Certain instructions can go either way on Cortex-A8.
3235 // Treat them as NEON instructions.
3236 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3237 return std::make_pair(ExeNEON, 0);
3239 if (Domain & ARMII::DomainVFP)
3240 return std::make_pair(ExeVFP, 0);
3242 return std::make_pair(ExeGeneric, 0);
3246 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3247 // We only know how to change VMOVD into VORR.
3248 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
3249 if (Domain != ExeNEON)
3252 // Zap the predicate operands.
3253 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3254 MI->RemoveOperand(3);
3255 MI->RemoveOperand(2);
3257 // Change to a VORRd which requires two identical use operands.
3258 MI->setDesc(get(ARM::VORRd));
3260 // Add the extra source operand and new predicates.
3261 // This will go before any implicit ops.
3262 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
3265 bool ARMBaseInstrInfo::hasNOP() const {
3266 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;