1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMGenInstrInfo.inc"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalValue.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
41 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
42 cl::desc("Enable ARM 2-addr to 3-addr conv"));
44 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
46 unsigned MLxOpc; // MLA / MLS opcode
47 unsigned MulOpc; // Expanded multiplication opcode
48 unsigned AddSubOpc; // Expanded add / sub opcode
49 bool NegAcc; // True if the acc is negated before the add / sub.
50 bool HasLane; // True if instruction has an extra "lane" operand.
53 static const ARM_MLxEntry ARM_MLxTable[] = {
54 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
56 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
57 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
58 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
59 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
60 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
61 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
62 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
63 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
66 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
67 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
68 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
69 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
70 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
71 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
72 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
73 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
76 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
77 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
79 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
80 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
81 assert(false && "Duplicated entries?");
82 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
83 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
87 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
88 // currently defaults to no prepass hazard recognizer.
89 ScheduleHazardRecognizer *ARMBaseInstrInfo::
90 CreateTargetHazardRecognizer(const TargetMachine *TM,
91 const ScheduleDAG *DAG) const {
92 if (usePreRAHazardRecognizer()) {
93 const InstrItineraryData *II = TM->getInstrItineraryData();
94 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
96 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
99 ScheduleHazardRecognizer *ARMBaseInstrInfo::
100 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
101 const ScheduleDAG *DAG) const {
102 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
103 return (ScheduleHazardRecognizer *)
104 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
105 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
109 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
110 MachineBasicBlock::iterator &MBBI,
111 LiveVariables *LV) const {
112 // FIXME: Thumb2 support.
117 MachineInstr *MI = MBBI;
118 MachineFunction &MF = *MI->getParent()->getParent();
119 uint64_t TSFlags = MI->getDesc().TSFlags;
121 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
122 default: return NULL;
123 case ARMII::IndexModePre:
126 case ARMII::IndexModePost:
130 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
132 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
136 MachineInstr *UpdateMI = NULL;
137 MachineInstr *MemMI = NULL;
138 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
139 const TargetInstrDesc &TID = MI->getDesc();
140 unsigned NumOps = TID.getNumOperands();
141 bool isLoad = !TID.mayStore();
142 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
143 const MachineOperand &Base = MI->getOperand(2);
144 const MachineOperand &Offset = MI->getOperand(NumOps-3);
145 unsigned WBReg = WB.getReg();
146 unsigned BaseReg = Base.getReg();
147 unsigned OffReg = Offset.getReg();
148 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
149 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
152 assert(false && "Unknown indexed op!");
154 case ARMII::AddrMode2: {
155 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
156 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
158 if (ARM_AM::getSOImmVal(Amt) == -1)
159 // Can't encode it in a so_imm operand. This transformation will
160 // add more than 1 instruction. Abandon!
162 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
163 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
164 .addReg(BaseReg).addImm(Amt)
165 .addImm(Pred).addReg(0).addReg(0);
166 } else if (Amt != 0) {
167 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
168 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
169 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
170 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
171 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
172 .addImm(Pred).addReg(0).addReg(0);
174 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
175 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
176 .addReg(BaseReg).addReg(OffReg)
177 .addImm(Pred).addReg(0).addReg(0);
180 case ARMII::AddrMode3 : {
181 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
182 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
184 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
187 .addReg(BaseReg).addImm(Amt)
188 .addImm(Pred).addReg(0).addReg(0);
190 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
191 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
192 .addReg(BaseReg).addReg(OffReg)
193 .addImm(Pred).addReg(0).addReg(0);
198 std::vector<MachineInstr*> NewMIs;
201 MemMI = BuildMI(MF, MI->getDebugLoc(),
202 get(MemOpc), MI->getOperand(0).getReg())
203 .addReg(WBReg).addImm(0).addImm(Pred);
205 MemMI = BuildMI(MF, MI->getDebugLoc(),
206 get(MemOpc)).addReg(MI->getOperand(1).getReg())
207 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
208 NewMIs.push_back(MemMI);
209 NewMIs.push_back(UpdateMI);
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(BaseReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
220 UpdateMI->getOperand(0).setIsDead();
221 NewMIs.push_back(UpdateMI);
222 NewMIs.push_back(MemMI);
225 // Transfer LiveVariables states, kill / dead info.
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
229 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
230 unsigned Reg = MO.getReg();
232 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
234 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
236 LV->addVirtualRegisterDead(Reg, NewMI);
238 if (MO.isUse() && MO.isKill()) {
239 for (unsigned j = 0; j < 2; ++j) {
240 // Look at the two new MI's in reverse order.
241 MachineInstr *NewMI = NewMIs[j];
242 if (!NewMI->readsRegister(Reg))
244 LV->addVirtualRegisterKilled(Reg, NewMI);
245 if (VI.removeKill(MI))
246 VI.Kills.push_back(NewMI);
254 MFI->insert(MBBI, NewMIs[1]);
255 MFI->insert(MBBI, NewMIs[0]);
261 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
262 MachineBasicBlock *&FBB,
263 SmallVectorImpl<MachineOperand> &Cond,
264 bool AllowModify) const {
265 // If the block has no terminators, it just falls into the block after it.
266 MachineBasicBlock::iterator I = MBB.end();
267 if (I == MBB.begin())
270 while (I->isDebugValue()) {
271 if (I == MBB.begin())
275 if (!isUnpredicatedTerminator(I))
278 // Get the last instruction in the block.
279 MachineInstr *LastInst = I;
281 // If there is only one terminator instruction, process it.
282 unsigned LastOpc = LastInst->getOpcode();
283 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
284 if (isUncondBranchOpcode(LastOpc)) {
285 TBB = LastInst->getOperand(0).getMBB();
288 if (isCondBranchOpcode(LastOpc)) {
289 // Block ends with fall-through condbranch.
290 TBB = LastInst->getOperand(0).getMBB();
291 Cond.push_back(LastInst->getOperand(1));
292 Cond.push_back(LastInst->getOperand(2));
295 return true; // Can't handle indirect branch.
298 // Get the instruction before it if it is a terminator.
299 MachineInstr *SecondLastInst = I;
300 unsigned SecondLastOpc = SecondLastInst->getOpcode();
302 // If AllowModify is true and the block ends with two or more unconditional
303 // branches, delete all but the first unconditional branch.
304 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
305 while (isUncondBranchOpcode(SecondLastOpc)) {
306 LastInst->eraseFromParent();
307 LastInst = SecondLastInst;
308 LastOpc = LastInst->getOpcode();
309 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
310 // Return now the only terminator is an unconditional branch.
311 TBB = LastInst->getOperand(0).getMBB();
315 SecondLastOpc = SecondLastInst->getOpcode();
320 // If there are three terminators, we don't know what sort of block this is.
321 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
324 // If the block ends with a B and a Bcc, handle it.
325 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
326 TBB = SecondLastInst->getOperand(0).getMBB();
327 Cond.push_back(SecondLastInst->getOperand(1));
328 Cond.push_back(SecondLastInst->getOperand(2));
329 FBB = LastInst->getOperand(0).getMBB();
333 // If the block ends with two unconditional branches, handle it. The second
334 // one is not executed, so remove it.
335 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
336 TBB = SecondLastInst->getOperand(0).getMBB();
339 I->eraseFromParent();
343 // ...likewise if it ends with a branch table followed by an unconditional
344 // branch. The branch folder can create these, and we must get rid of them for
345 // correctness of Thumb constant islands.
346 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
347 isIndirectBranchOpcode(SecondLastOpc)) &&
348 isUncondBranchOpcode(LastOpc)) {
351 I->eraseFromParent();
355 // Otherwise, can't handle this.
360 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
361 MachineBasicBlock::iterator I = MBB.end();
362 if (I == MBB.begin()) return 0;
364 while (I->isDebugValue()) {
365 if (I == MBB.begin())
369 if (!isUncondBranchOpcode(I->getOpcode()) &&
370 !isCondBranchOpcode(I->getOpcode()))
373 // Remove the branch.
374 I->eraseFromParent();
378 if (I == MBB.begin()) return 1;
380 if (!isCondBranchOpcode(I->getOpcode()))
383 // Remove the branch.
384 I->eraseFromParent();
389 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
390 MachineBasicBlock *FBB,
391 const SmallVectorImpl<MachineOperand> &Cond,
393 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
394 int BOpc = !AFI->isThumbFunction()
395 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
396 int BccOpc = !AFI->isThumbFunction()
397 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
399 // Shouldn't be a fall through.
400 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
401 assert((Cond.size() == 2 || Cond.size() == 0) &&
402 "ARM branch conditions have two components!");
405 if (Cond.empty()) // Unconditional branch?
406 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
408 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
409 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
413 // Two-way conditional branch.
414 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
415 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
420 bool ARMBaseInstrInfo::
421 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
422 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
423 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
427 bool ARMBaseInstrInfo::
428 PredicateInstruction(MachineInstr *MI,
429 const SmallVectorImpl<MachineOperand> &Pred) const {
430 unsigned Opc = MI->getOpcode();
431 if (isUncondBranchOpcode(Opc)) {
432 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
433 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
434 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
438 int PIdx = MI->findFirstPredOperandIdx();
440 MachineOperand &PMO = MI->getOperand(PIdx);
441 PMO.setImm(Pred[0].getImm());
442 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
448 bool ARMBaseInstrInfo::
449 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
450 const SmallVectorImpl<MachineOperand> &Pred2) const {
451 if (Pred1.size() > 2 || Pred2.size() > 2)
454 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
455 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
465 return CC2 == ARMCC::HI;
467 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
469 return CC2 == ARMCC::GT;
471 return CC2 == ARMCC::LT;
475 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
476 std::vector<MachineOperand> &Pred) const {
477 // FIXME: This confuses implicit_def with optional CPSR def.
478 const TargetInstrDesc &TID = MI->getDesc();
479 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
483 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
484 const MachineOperand &MO = MI->getOperand(i);
485 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
494 /// isPredicable - Return true if the specified instruction can be predicated.
495 /// By default, this returns true for every instruction with a
496 /// PredicateOperand.
497 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
498 const TargetInstrDesc &TID = MI->getDesc();
499 if (!TID.isPredicable())
502 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
503 ARMFunctionInfo *AFI =
504 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
505 return AFI->isThumb2Function();
510 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
511 LLVM_ATTRIBUTE_NOINLINE
512 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
514 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
516 assert(JTI < JT.size());
517 return JT[JTI].MBBs.size();
520 /// GetInstSize - Return the size of the specified MachineInstr.
522 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
523 const MachineBasicBlock &MBB = *MI->getParent();
524 const MachineFunction *MF = MBB.getParent();
525 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
527 // Basic size info comes from the TSFlags field.
528 const TargetInstrDesc &TID = MI->getDesc();
529 uint64_t TSFlags = TID.TSFlags;
531 unsigned Opc = MI->getOpcode();
532 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
534 // If this machine instr is an inline asm, measure it.
535 if (MI->getOpcode() == ARM::INLINEASM)
536 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
541 llvm_unreachable("Unknown or unset size field for instr!");
542 case TargetOpcode::IMPLICIT_DEF:
543 case TargetOpcode::KILL:
544 case TargetOpcode::PROLOG_LABEL:
545 case TargetOpcode::EH_LABEL:
546 case TargetOpcode::DBG_VALUE:
551 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
552 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
553 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
554 case ARMII::SizeSpecial: {
556 case ARM::MOVi16_pic_ga:
557 case ARM::MOVTi16_pic_ga:
558 case ARM::t2MOVi16_pic_ga:
559 case ARM::t2MOVTi16_pic_ga:
562 case ARM::t2MOVi32imm:
564 case ARM::CONSTPOOL_ENTRY:
565 // If this machine instr is a constant pool entry, its size is recorded as
567 return MI->getOperand(2).getImm();
568 case ARM::Int_eh_sjlj_longjmp:
570 case ARM::tInt_eh_sjlj_longjmp:
572 case ARM::Int_eh_sjlj_setjmp:
573 case ARM::Int_eh_sjlj_setjmp_nofp:
575 case ARM::tInt_eh_sjlj_setjmp:
576 case ARM::t2Int_eh_sjlj_setjmp:
577 case ARM::t2Int_eh_sjlj_setjmp_nofp:
585 case ARM::t2TBH_JT: {
586 // These are jumptable branches, i.e. a branch followed by an inlined
587 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
588 // entry is one byte; TBH two byte each.
589 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
590 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
591 unsigned NumOps = TID.getNumOperands();
592 MachineOperand JTOP =
593 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
594 unsigned JTI = JTOP.getIndex();
595 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
597 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
598 assert(JTI < JT.size());
599 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
600 // 4 aligned. The assembler / linker may add 2 byte padding just before
601 // the JT entries. The size does not include this padding; the
602 // constant islands pass does separate bookkeeping for it.
603 // FIXME: If we know the size of the function is less than (1 << 16) *2
604 // bytes, we can use 16-bit entries instead. Then there won't be an
606 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
607 unsigned NumEntries = getNumJTEntries(JT, JTI);
608 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
609 // Make sure the instruction that follows TBB is 2-byte aligned.
610 // FIXME: Constant island pass should insert an "ALIGN" instruction
613 return NumEntries * EntrySize + InstSize;
616 // Otherwise, pseudo-instruction sizes are zero.
621 return 0; // Not reached
624 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
625 MachineBasicBlock::iterator I, DebugLoc DL,
626 unsigned DestReg, unsigned SrcReg,
627 bool KillSrc) const {
628 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
629 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
631 if (GPRDest && GPRSrc) {
632 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
633 .addReg(SrcReg, getKillRegState(KillSrc))));
637 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
638 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
641 if (SPRDest && SPRSrc)
643 else if (GPRDest && SPRSrc)
645 else if (SPRDest && GPRSrc)
647 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
649 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
651 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
653 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
656 llvm_unreachable("Impossible reg-to-reg copy");
658 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
659 MIB.addReg(SrcReg, getKillRegState(KillSrc));
660 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
665 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
666 unsigned Reg, unsigned SubIdx, unsigned State,
667 const TargetRegisterInfo *TRI) {
669 return MIB.addReg(Reg, State);
671 if (TargetRegisterInfo::isPhysicalRegister(Reg))
672 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
673 return MIB.addReg(Reg, State, SubIdx);
676 void ARMBaseInstrInfo::
677 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
678 unsigned SrcReg, bool isKill, int FI,
679 const TargetRegisterClass *RC,
680 const TargetRegisterInfo *TRI) const {
682 if (I != MBB.end()) DL = I->getDebugLoc();
683 MachineFunction &MF = *MBB.getParent();
684 MachineFrameInfo &MFI = *MF.getFrameInfo();
685 unsigned Align = MFI.getObjectAlignment(FI);
687 MachineMemOperand *MMO =
688 MF.getMachineMemOperand(MachinePointerInfo(
689 PseudoSourceValue::getFixedStack(FI)),
690 MachineMemOperand::MOStore,
691 MFI.getObjectSize(FI),
694 // tGPR is used sometimes in ARM instructions that need to avoid using
695 // certain registers. Just treat it as GPR here. Likewise, rGPR.
696 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
697 || RC == ARM::rGPRRegisterClass)
698 RC = ARM::GPRRegisterClass;
700 switch (RC->getID()) {
701 case ARM::GPRRegClassID:
702 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
703 .addReg(SrcReg, getKillRegState(isKill))
704 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
706 case ARM::SPRRegClassID:
707 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
708 .addReg(SrcReg, getKillRegState(isKill))
709 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
711 case ARM::DPRRegClassID:
712 case ARM::DPR_VFP2RegClassID:
713 case ARM::DPR_8RegClassID:
714 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
715 .addReg(SrcReg, getKillRegState(isKill))
716 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
718 case ARM::QPRRegClassID:
719 case ARM::QPR_VFP2RegClassID:
720 case ARM::QPR_8RegClassID:
721 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
722 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
723 .addFrameIndex(FI).addImm(16)
724 .addReg(SrcReg, getKillRegState(isKill))
725 .addMemOperand(MMO));
727 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
728 .addReg(SrcReg, getKillRegState(isKill))
730 .addMemOperand(MMO));
733 case ARM::QQPRRegClassID:
734 case ARM::QQPR_VFP2RegClassID:
735 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
736 // FIXME: It's possible to only store part of the QQ register if the
737 // spilled def has a sub-register index.
738 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
739 .addFrameIndex(FI).addImm(16)
740 .addReg(SrcReg, getKillRegState(isKill))
741 .addMemOperand(MMO));
743 MachineInstrBuilder MIB =
744 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
747 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
748 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
749 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
750 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
753 case ARM::QQQQPRRegClassID: {
754 MachineInstrBuilder MIB =
755 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
758 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
759 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
760 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
761 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
762 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
763 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
764 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
765 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
769 llvm_unreachable("Unknown regclass!");
774 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
775 int &FrameIndex) const {
776 switch (MI->getOpcode()) {
779 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
780 if (MI->getOperand(1).isFI() &&
781 MI->getOperand(2).isReg() &&
782 MI->getOperand(3).isImm() &&
783 MI->getOperand(2).getReg() == 0 &&
784 MI->getOperand(3).getImm() == 0) {
785 FrameIndex = MI->getOperand(1).getIndex();
786 return MI->getOperand(0).getReg();
794 if (MI->getOperand(1).isFI() &&
795 MI->getOperand(2).isImm() &&
796 MI->getOperand(2).getImm() == 0) {
797 FrameIndex = MI->getOperand(1).getIndex();
798 return MI->getOperand(0).getReg();
801 case ARM::VST1q64Pseudo:
802 if (MI->getOperand(0).isFI() &&
803 MI->getOperand(2).getSubReg() == 0) {
804 FrameIndex = MI->getOperand(0).getIndex();
805 return MI->getOperand(2).getReg();
809 if (MI->getOperand(1).isFI() &&
810 MI->getOperand(0).getSubReg() == 0) {
811 FrameIndex = MI->getOperand(1).getIndex();
812 return MI->getOperand(0).getReg();
820 void ARMBaseInstrInfo::
821 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
822 unsigned DestReg, int FI,
823 const TargetRegisterClass *RC,
824 const TargetRegisterInfo *TRI) const {
826 if (I != MBB.end()) DL = I->getDebugLoc();
827 MachineFunction &MF = *MBB.getParent();
828 MachineFrameInfo &MFI = *MF.getFrameInfo();
829 unsigned Align = MFI.getObjectAlignment(FI);
830 MachineMemOperand *MMO =
831 MF.getMachineMemOperand(
832 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
833 MachineMemOperand::MOLoad,
834 MFI.getObjectSize(FI),
837 // tGPR is used sometimes in ARM instructions that need to avoid using
838 // certain registers. Just treat it as GPR here.
839 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass
840 || RC == ARM::rGPRRegisterClass)
841 RC = ARM::GPRRegisterClass;
843 switch (RC->getID()) {
844 case ARM::GPRRegClassID:
845 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
846 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
848 case ARM::SPRRegClassID:
849 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
850 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
852 case ARM::DPRRegClassID:
853 case ARM::DPR_VFP2RegClassID:
854 case ARM::DPR_8RegClassID:
855 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
856 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
858 case ARM::QPRRegClassID:
859 case ARM::QPR_VFP2RegClassID:
860 case ARM::QPR_8RegClassID:
861 if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
862 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
863 .addFrameIndex(FI).addImm(16)
864 .addMemOperand(MMO));
866 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
868 .addMemOperand(MMO));
871 case ARM::QQPRRegClassID:
872 case ARM::QQPR_VFP2RegClassID:
873 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
874 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
875 .addFrameIndex(FI).addImm(16)
876 .addMemOperand(MMO));
878 MachineInstrBuilder MIB =
879 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
882 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
883 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
884 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
885 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
888 case ARM::QQQQPRRegClassID: {
889 MachineInstrBuilder MIB =
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
893 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
894 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
895 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
896 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
897 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
898 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
899 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
900 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
904 llvm_unreachable("Unknown regclass!");
909 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
910 int &FrameIndex) const {
911 switch (MI->getOpcode()) {
914 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
915 if (MI->getOperand(1).isFI() &&
916 MI->getOperand(2).isReg() &&
917 MI->getOperand(3).isImm() &&
918 MI->getOperand(2).getReg() == 0 &&
919 MI->getOperand(3).getImm() == 0) {
920 FrameIndex = MI->getOperand(1).getIndex();
921 return MI->getOperand(0).getReg();
929 if (MI->getOperand(1).isFI() &&
930 MI->getOperand(2).isImm() &&
931 MI->getOperand(2).getImm() == 0) {
932 FrameIndex = MI->getOperand(1).getIndex();
933 return MI->getOperand(0).getReg();
936 case ARM::VLD1q64Pseudo:
937 if (MI->getOperand(1).isFI() &&
938 MI->getOperand(0).getSubReg() == 0) {
939 FrameIndex = MI->getOperand(1).getIndex();
940 return MI->getOperand(0).getReg();
944 if (MI->getOperand(1).isFI() &&
945 MI->getOperand(0).getSubReg() == 0) {
946 FrameIndex = MI->getOperand(1).getIndex();
947 return MI->getOperand(0).getReg();
956 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
957 int FrameIx, uint64_t Offset,
960 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
961 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
965 /// Create a copy of a const pool value. Update CPI to the new index and return
967 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
968 MachineConstantPool *MCP = MF.getConstantPool();
969 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
971 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
972 assert(MCPE.isMachineConstantPoolEntry() &&
973 "Expecting a machine constantpool entry!");
974 ARMConstantPoolValue *ACPV =
975 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
977 unsigned PCLabelId = AFI->createPICLabelUId();
978 ARMConstantPoolValue *NewCPV = 0;
979 // FIXME: The below assumes PIC relocation model and that the function
980 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
981 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
982 // instructions, so that's probably OK, but is PIC always correct when
984 if (ACPV->isGlobalValue())
985 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
987 else if (ACPV->isExtSymbol())
988 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
989 ACPV->getSymbol(), PCLabelId, 4);
990 else if (ACPV->isBlockAddress())
991 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
992 ARMCP::CPBlockAddress, 4);
993 else if (ACPV->isLSDA())
994 NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId,
997 llvm_unreachable("Unexpected ARM constantpool value type!!");
998 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1002 void ARMBaseInstrInfo::
1003 reMaterialize(MachineBasicBlock &MBB,
1004 MachineBasicBlock::iterator I,
1005 unsigned DestReg, unsigned SubIdx,
1006 const MachineInstr *Orig,
1007 const TargetRegisterInfo &TRI) const {
1008 unsigned Opcode = Orig->getOpcode();
1011 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1012 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1016 case ARM::tLDRpci_pic:
1017 case ARM::t2LDRpci_pic: {
1018 MachineFunction &MF = *MBB.getParent();
1019 unsigned CPI = Orig->getOperand(1).getIndex();
1020 unsigned PCLabelId = duplicateCPV(MF, CPI);
1021 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1023 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1024 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1031 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1032 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1033 switch(Orig->getOpcode()) {
1034 case ARM::tLDRpci_pic:
1035 case ARM::t2LDRpci_pic: {
1036 unsigned CPI = Orig->getOperand(1).getIndex();
1037 unsigned PCLabelId = duplicateCPV(MF, CPI);
1038 Orig->getOperand(1).setIndex(CPI);
1039 Orig->getOperand(2).setImm(PCLabelId);
1046 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1047 const MachineInstr *MI1,
1048 const MachineRegisterInfo *MRI) const {
1049 int Opcode = MI0->getOpcode();
1050 if (Opcode == ARM::t2LDRpci ||
1051 Opcode == ARM::t2LDRpci_pic ||
1052 Opcode == ARM::tLDRpci ||
1053 Opcode == ARM::tLDRpci_pic ||
1054 Opcode == ARM::MOV_pic_ga_add_pc ||
1055 Opcode == ARM::t2MOV_pic_ga_add_pc) {
1056 if (MI1->getOpcode() != Opcode)
1058 if (MI0->getNumOperands() != MI1->getNumOperands())
1061 const MachineOperand &MO0 = MI0->getOperand(1);
1062 const MachineOperand &MO1 = MI1->getOperand(1);
1063 if (MO0.getOffset() != MO1.getOffset())
1066 if (Opcode == ARM::MOV_pic_ga_add_pc ||
1067 Opcode == ARM::t2MOV_pic_ga_add_pc)
1068 // Ignore the PC labels.
1069 return MO0.getGlobal() == MO1.getGlobal();
1071 const MachineFunction *MF = MI0->getParent()->getParent();
1072 const MachineConstantPool *MCP = MF->getConstantPool();
1073 int CPI0 = MO0.getIndex();
1074 int CPI1 = MO1.getIndex();
1075 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1076 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1077 ARMConstantPoolValue *ACPV0 =
1078 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1079 ARMConstantPoolValue *ACPV1 =
1080 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1081 return ACPV0->hasSameValue(ACPV1);
1082 } else if (Opcode == ARM::PICLDR) {
1083 if (MI1->getOpcode() != Opcode)
1085 if (MI0->getNumOperands() != MI1->getNumOperands())
1088 unsigned Addr0 = MI0->getOperand(1).getReg();
1089 unsigned Addr1 = MI1->getOperand(1).getReg();
1090 if (Addr0 != Addr1) {
1092 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1093 !TargetRegisterInfo::isVirtualRegister(Addr1))
1096 // This assumes SSA form.
1097 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1098 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1099 // Check if the loaded value, e.g. a constantpool of a global address, are
1101 if (!produceSameValue(Def0, Def1, MRI))
1105 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1106 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1107 const MachineOperand &MO0 = MI0->getOperand(i);
1108 const MachineOperand &MO1 = MI1->getOperand(i);
1109 if (!MO0.isIdenticalTo(MO1))
1115 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1118 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1119 /// determine if two loads are loading from the same base address. It should
1120 /// only return true if the base pointers are the same and the only differences
1121 /// between the two addresses is the offset. It also returns the offsets by
1123 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1125 int64_t &Offset2) const {
1126 // Don't worry about Thumb: just ARM and Thumb2.
1127 if (Subtarget.isThumb1Only()) return false;
1129 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1132 switch (Load1->getMachineOpcode()) {
1145 case ARM::t2LDRSHi8:
1147 case ARM::t2LDRSHi12:
1151 switch (Load2->getMachineOpcode()) {
1164 case ARM::t2LDRSHi8:
1166 case ARM::t2LDRSHi12:
1170 // Check if base addresses and chain operands match.
1171 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1172 Load1->getOperand(4) != Load2->getOperand(4))
1175 // Index should be Reg0.
1176 if (Load1->getOperand(3) != Load2->getOperand(3))
1179 // Determine the offsets.
1180 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1181 isa<ConstantSDNode>(Load2->getOperand(1))) {
1182 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1183 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1190 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1191 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1192 /// be scheduled togther. On some targets if two loads are loading from
1193 /// addresses in the same cache line, it's better if they are scheduled
1194 /// together. This function takes two integers that represent the load offsets
1195 /// from the common base address. It returns true if it decides it's desirable
1196 /// to schedule the two loads together. "NumLoads" is the number of loads that
1197 /// have already been scheduled after Load1.
1198 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1199 int64_t Offset1, int64_t Offset2,
1200 unsigned NumLoads) const {
1201 // Don't worry about Thumb: just ARM and Thumb2.
1202 if (Subtarget.isThumb1Only()) return false;
1204 assert(Offset2 > Offset1);
1206 if ((Offset2 - Offset1) / 8 > 64)
1209 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1210 return false; // FIXME: overly conservative?
1212 // Four loads in a row should be sufficient.
1219 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1220 const MachineBasicBlock *MBB,
1221 const MachineFunction &MF) const {
1222 // Debug info is never a scheduling boundary. It's necessary to be explicit
1223 // due to the special treatment of IT instructions below, otherwise a
1224 // dbg_value followed by an IT will result in the IT instruction being
1225 // considered a scheduling hazard, which is wrong. It should be the actual
1226 // instruction preceding the dbg_value instruction(s), just like it is
1227 // when debug info is not present.
1228 if (MI->isDebugValue())
1231 // Terminators and labels can't be scheduled around.
1232 if (MI->getDesc().isTerminator() || MI->isLabel())
1235 // Treat the start of the IT block as a scheduling boundary, but schedule
1236 // t2IT along with all instructions following it.
1237 // FIXME: This is a big hammer. But the alternative is to add all potential
1238 // true and anti dependencies to IT block instructions as implicit operands
1239 // to the t2IT instruction. The added compile time and complexity does not
1241 MachineBasicBlock::const_iterator I = MI;
1242 // Make sure to skip any dbg_value instructions
1243 while (++I != MBB->end() && I->isDebugValue())
1245 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1248 // Don't attempt to schedule around any instruction that defines
1249 // a stack-oriented pointer, as it's unlikely to be profitable. This
1250 // saves compile time, because it doesn't require every single
1251 // stack slot reference to depend on the instruction that does the
1253 if (MI->definesRegister(ARM::SP))
1259 bool ARMBaseInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
1261 unsigned ExtraPredCycles,
1263 float Confidence) const {
1267 // Attempt to estimate the relative costs of predication versus branching.
1268 float UnpredCost = Probability * NumCyles;
1269 UnpredCost += 1.0; // The branch itself
1270 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1272 return (float)(NumCyles + ExtraPredCycles) < UnpredCost;
1275 bool ARMBaseInstrInfo::
1276 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1277 unsigned TCycles, unsigned TExtra,
1278 MachineBasicBlock &FMBB,
1279 unsigned FCycles, unsigned FExtra,
1280 float Probability, float Confidence) const {
1281 if (!TCycles || !FCycles)
1284 // Attempt to estimate the relative costs of predication versus branching.
1285 float UnpredCost = Probability * TCycles + (1.0 - Probability) * FCycles;
1286 UnpredCost += 1.0; // The branch itself
1287 UnpredCost += (1.0 - Confidence) * Subtarget.getMispredictionPenalty();
1289 return (float)(TCycles + FCycles + TExtra + FExtra) < UnpredCost;
1292 /// getInstrPredicate - If instruction is predicated, returns its predicate
1293 /// condition, otherwise returns AL. It also returns the condition code
1294 /// register by reference.
1296 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1297 int PIdx = MI->findFirstPredOperandIdx();
1303 PredReg = MI->getOperand(PIdx+1).getReg();
1304 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1308 int llvm::getMatchingCondBranchOpcode(int Opc) {
1311 else if (Opc == ARM::tB)
1313 else if (Opc == ARM::t2B)
1316 llvm_unreachable("Unknown unconditional branch opcode!");
1321 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1322 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1323 unsigned DestReg, unsigned BaseReg, int NumBytes,
1324 ARMCC::CondCodes Pred, unsigned PredReg,
1325 const ARMBaseInstrInfo &TII) {
1326 bool isSub = NumBytes < 0;
1327 if (isSub) NumBytes = -NumBytes;
1330 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1331 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1332 assert(ThisVal && "Didn't extract field correctly");
1334 // We will handle these bits from offset, clear them.
1335 NumBytes &= ~ThisVal;
1337 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1339 // Build the new ADD / SUB.
1340 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1341 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1342 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1343 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1348 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1349 unsigned FrameReg, int &Offset,
1350 const ARMBaseInstrInfo &TII) {
1351 unsigned Opcode = MI.getOpcode();
1352 const TargetInstrDesc &Desc = MI.getDesc();
1353 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1356 // Memory operands in inline assembly always use AddrMode2.
1357 if (Opcode == ARM::INLINEASM)
1358 AddrMode = ARMII::AddrMode2;
1360 if (Opcode == ARM::ADDri) {
1361 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1363 // Turn it into a move.
1364 MI.setDesc(TII.get(ARM::MOVr));
1365 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1366 MI.RemoveOperand(FrameRegIdx+1);
1369 } else if (Offset < 0) {
1372 MI.setDesc(TII.get(ARM::SUBri));
1375 // Common case: small offset, fits into instruction.
1376 if (ARM_AM::getSOImmVal(Offset) != -1) {
1377 // Replace the FrameIndex with sp / fp
1378 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1379 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1384 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1386 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1387 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1389 // We will handle these bits from offset, clear them.
1390 Offset &= ~ThisImmVal;
1392 // Get the properly encoded SOImmVal field.
1393 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1394 "Bit extraction didn't work?");
1395 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1397 unsigned ImmIdx = 0;
1399 unsigned NumBits = 0;
1402 case ARMII::AddrMode_i12: {
1403 ImmIdx = FrameRegIdx + 1;
1404 InstrOffs = MI.getOperand(ImmIdx).getImm();
1408 case ARMII::AddrMode2: {
1409 ImmIdx = FrameRegIdx+2;
1410 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1411 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1416 case ARMII::AddrMode3: {
1417 ImmIdx = FrameRegIdx+2;
1418 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1419 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1424 case ARMII::AddrMode4:
1425 case ARMII::AddrMode6:
1426 // Can't fold any offset even if it's zero.
1428 case ARMII::AddrMode5: {
1429 ImmIdx = FrameRegIdx+1;
1430 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1431 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1438 llvm_unreachable("Unsupported addressing mode!");
1442 Offset += InstrOffs * Scale;
1443 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1449 // Attempt to fold address comp. if opcode has offset bits
1451 // Common case: small offset, fits into instruction.
1452 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1453 int ImmedOffset = Offset / Scale;
1454 unsigned Mask = (1 << NumBits) - 1;
1455 if ((unsigned)Offset <= Mask * Scale) {
1456 // Replace the FrameIndex with sp
1457 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1458 // FIXME: When addrmode2 goes away, this will simplify (like the
1459 // T2 version), as the LDR.i12 versions don't need the encoding
1460 // tricks for the offset value.
1462 if (AddrMode == ARMII::AddrMode_i12)
1463 ImmedOffset = -ImmedOffset;
1465 ImmedOffset |= 1 << NumBits;
1467 ImmOp.ChangeToImmediate(ImmedOffset);
1472 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1473 ImmedOffset = ImmedOffset & Mask;
1475 if (AddrMode == ARMII::AddrMode_i12)
1476 ImmedOffset = -ImmedOffset;
1478 ImmedOffset |= 1 << NumBits;
1480 ImmOp.ChangeToImmediate(ImmedOffset);
1481 Offset &= ~(Mask*Scale);
1485 Offset = (isSub) ? -Offset : Offset;
1489 bool ARMBaseInstrInfo::
1490 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1491 int &CmpValue) const {
1492 switch (MI->getOpcode()) {
1496 SrcReg = MI->getOperand(0).getReg();
1498 CmpValue = MI->getOperand(1).getImm();
1502 SrcReg = MI->getOperand(0).getReg();
1503 CmpMask = MI->getOperand(1).getImm();
1511 /// isSuitableForMask - Identify a suitable 'and' instruction that
1512 /// operates on the given source register and applies the same mask
1513 /// as a 'tst' instruction. Provide a limited look-through for copies.
1514 /// When successful, MI will hold the found instruction.
1515 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1516 int CmpMask, bool CommonUse) {
1517 switch (MI->getOpcode()) {
1520 if (CmpMask != MI->getOperand(2).getImm())
1522 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1526 // Walk down one instruction which is potentially an 'and'.
1527 const MachineInstr &Copy = *MI;
1528 MachineBasicBlock::iterator AND(
1529 llvm::next(MachineBasicBlock::iterator(MI)));
1530 if (AND == MI->getParent()->end()) return false;
1532 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1540 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1541 /// comparison into one that sets the zero bit in the flags register.
1542 bool ARMBaseInstrInfo::
1543 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1544 int CmpValue, const MachineRegisterInfo *MRI) const {
1548 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1549 if (llvm::next(DI) != MRI->def_end())
1550 // Only support one definition.
1553 MachineInstr *MI = &*DI;
1555 // Masked compares sometimes use the same register as the corresponding 'and'.
1556 if (CmpMask != ~0) {
1557 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1559 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1560 UE = MRI->use_end(); UI != UE; ++UI) {
1561 if (UI->getParent() != CmpInstr->getParent()) continue;
1562 MachineInstr *PotentialAND = &*UI;
1563 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1568 if (!MI) return false;
1572 // Conservatively refuse to convert an instruction which isn't in the same BB
1573 // as the comparison.
1574 if (MI->getParent() != CmpInstr->getParent())
1577 // Check that CPSR isn't set between the comparison instruction and the one we
1579 MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
1580 B = MI->getParent()->begin();
1582 // Early exit if CmpInstr is at the beginning of the BB.
1583 if (I == B) return false;
1586 for (; I != E; --I) {
1587 const MachineInstr &Instr = *I;
1589 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1590 const MachineOperand &MO = Instr.getOperand(IO);
1591 if (!MO.isReg()) continue;
1593 // This instruction modifies or uses CPSR after the one we want to
1594 // change. We can't do this transformation.
1595 if (MO.getReg() == ARM::CPSR)
1600 // The 'and' is below the comparison instruction.
1604 // Set the "zero" bit in CPSR.
1605 switch (MI->getOpcode()) {
1613 // Toggle the optional operand to CPSR.
1614 MI->getOperand(5).setReg(ARM::CPSR);
1615 MI->getOperand(5).setIsDef(true);
1616 CmpInstr->eraseFromParent();
1623 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1624 MachineInstr *DefMI, unsigned Reg,
1625 MachineRegisterInfo *MRI) const {
1626 // Fold large immediates into add, sub, or, xor.
1627 unsigned DefOpc = DefMI->getOpcode();
1628 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1630 if (!DefMI->getOperand(1).isImm())
1631 // Could be t2MOVi32imm <ga:xx>
1634 if (!MRI->hasOneNonDBGUse(Reg))
1637 unsigned UseOpc = UseMI->getOpcode();
1638 unsigned NewUseOpc = 0;
1639 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1640 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1641 bool Commute = false;
1643 default: return false;
1651 case ARM::t2EORrr: {
1652 Commute = UseMI->getOperand(2).getReg() != Reg;
1659 NewUseOpc = ARM::SUBri;
1665 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1667 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1668 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1671 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1672 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1673 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1677 case ARM::t2SUBrr: {
1681 NewUseOpc = ARM::t2SUBri;
1686 case ARM::t2EORrr: {
1687 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1689 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1690 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1693 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1694 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1695 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1703 unsigned OpIdx = Commute ? 2 : 1;
1704 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1705 bool isKill = UseMI->getOperand(OpIdx).isKill();
1706 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1707 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1708 *UseMI, UseMI->getDebugLoc(),
1709 get(NewUseOpc), NewReg)
1710 .addReg(Reg1, getKillRegState(isKill))
1711 .addImm(SOImmValV1)));
1712 UseMI->setDesc(get(NewUseOpc));
1713 UseMI->getOperand(1).setReg(NewReg);
1714 UseMI->getOperand(1).setIsKill();
1715 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1716 DefMI->eraseFromParent();
1721 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
1722 const MachineInstr *MI) const {
1723 if (!ItinData || ItinData->isEmpty())
1726 const TargetInstrDesc &Desc = MI->getDesc();
1727 unsigned Class = Desc.getSchedClass();
1728 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
1732 unsigned Opc = MI->getOpcode();
1735 llvm_unreachable("Unexpected multi-uops instruction!");
1743 // The number of uOps for load / store multiple are determined by the number
1746 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
1747 // same cycle. The scheduling for the first load / store must be done
1748 // separately by assuming the the address is not 64-bit aligned.
1750 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
1751 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
1752 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
1755 case ARM::VLDMDIA_UPD:
1756 case ARM::VLDMDDB_UPD:
1759 case ARM::VLDMSIA_UPD:
1760 case ARM::VLDMSDB_UPD:
1763 case ARM::VSTMDIA_UPD:
1764 case ARM::VSTMDDB_UPD:
1767 case ARM::VSTMSIA_UPD:
1768 case ARM::VSTMSDB_UPD: {
1769 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
1770 return (NumRegs / 2) + (NumRegs % 2) + 1;
1773 case ARM::LDMIA_RET:
1778 case ARM::LDMIA_UPD:
1779 case ARM::LDMDA_UPD:
1780 case ARM::LDMDB_UPD:
1781 case ARM::LDMIB_UPD:
1786 case ARM::STMIA_UPD:
1787 case ARM::STMDA_UPD:
1788 case ARM::STMDB_UPD:
1789 case ARM::STMIB_UPD:
1791 case ARM::tLDMIA_UPD:
1793 case ARM::tSTMIA_UPD:
1797 case ARM::t2LDMIA_RET:
1800 case ARM::t2LDMIA_UPD:
1801 case ARM::t2LDMDB_UPD:
1804 case ARM::t2STMIA_UPD:
1805 case ARM::t2STMDB_UPD: {
1806 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
1807 if (Subtarget.isCortexA8()) {
1810 // 4 registers would be issued: 2, 2.
1811 // 5 registers would be issued: 2, 2, 1.
1812 UOps = (NumRegs / 2);
1816 } else if (Subtarget.isCortexA9()) {
1817 UOps = (NumRegs / 2);
1818 // If there are odd number of registers or if it's not 64-bit aligned,
1819 // then it takes an extra AGU (Address Generation Unit) cycle.
1820 if ((NumRegs % 2) ||
1821 !MI->hasOneMemOperand() ||
1822 (*MI->memoperands_begin())->getAlignment() < 8)
1826 // Assume the worst.
1834 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
1835 const TargetInstrDesc &DefTID,
1837 unsigned DefIdx, unsigned DefAlign) const {
1838 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1840 // Def is the address writeback.
1841 return ItinData->getOperandCycle(DefClass, DefIdx);
1844 if (Subtarget.isCortexA8()) {
1845 // (regno / 2) + (regno % 2) + 1
1846 DefCycle = RegNo / 2 + 1;
1849 } else if (Subtarget.isCortexA9()) {
1851 bool isSLoad = false;
1853 switch (DefTID.getOpcode()) {
1857 case ARM::VLDMSIA_UPD:
1858 case ARM::VLDMSDB_UPD:
1863 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1864 // then it takes an extra cycle.
1865 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
1868 // Assume the worst.
1869 DefCycle = RegNo + 2;
1876 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
1877 const TargetInstrDesc &DefTID,
1879 unsigned DefIdx, unsigned DefAlign) const {
1880 int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1;
1882 // Def is the address writeback.
1883 return ItinData->getOperandCycle(DefClass, DefIdx);
1886 if (Subtarget.isCortexA8()) {
1887 // 4 registers would be issued: 1, 2, 1.
1888 // 5 registers would be issued: 1, 2, 2.
1889 DefCycle = RegNo / 2;
1892 // Result latency is issue cycle + 2: E2.
1894 } else if (Subtarget.isCortexA9()) {
1895 DefCycle = (RegNo / 2);
1896 // If there are odd number of registers or if it's not 64-bit aligned,
1897 // then it takes an extra AGU (Address Generation Unit) cycle.
1898 if ((RegNo % 2) || DefAlign < 8)
1900 // Result latency is AGU cycles + 2.
1903 // Assume the worst.
1904 DefCycle = RegNo + 2;
1911 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
1912 const TargetInstrDesc &UseTID,
1914 unsigned UseIdx, unsigned UseAlign) const {
1915 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1917 return ItinData->getOperandCycle(UseClass, UseIdx);
1920 if (Subtarget.isCortexA8()) {
1921 // (regno / 2) + (regno % 2) + 1
1922 UseCycle = RegNo / 2 + 1;
1925 } else if (Subtarget.isCortexA9()) {
1927 bool isSStore = false;
1929 switch (UseTID.getOpcode()) {
1933 case ARM::VSTMSIA_UPD:
1934 case ARM::VSTMSDB_UPD:
1939 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
1940 // then it takes an extra cycle.
1941 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
1944 // Assume the worst.
1945 UseCycle = RegNo + 2;
1952 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
1953 const TargetInstrDesc &UseTID,
1955 unsigned UseIdx, unsigned UseAlign) const {
1956 int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1;
1958 return ItinData->getOperandCycle(UseClass, UseIdx);
1961 if (Subtarget.isCortexA8()) {
1962 UseCycle = RegNo / 2;
1967 } else if (Subtarget.isCortexA9()) {
1968 UseCycle = (RegNo / 2);
1969 // If there are odd number of registers or if it's not 64-bit aligned,
1970 // then it takes an extra AGU (Address Generation Unit) cycle.
1971 if ((RegNo % 2) || UseAlign < 8)
1974 // Assume the worst.
1981 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
1982 const TargetInstrDesc &DefTID,
1983 unsigned DefIdx, unsigned DefAlign,
1984 const TargetInstrDesc &UseTID,
1985 unsigned UseIdx, unsigned UseAlign) const {
1986 unsigned DefClass = DefTID.getSchedClass();
1987 unsigned UseClass = UseTID.getSchedClass();
1989 if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands())
1990 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
1992 // This may be a def / use of a variable_ops instruction, the operand
1993 // latency might be determinable dynamically. Let the target try to
1996 bool LdmBypass = false;
1997 switch (DefTID.getOpcode()) {
1999 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2004 case ARM::VLDMDIA_UPD:
2005 case ARM::VLDMDDB_UPD:
2008 case ARM::VLDMSIA_UPD:
2009 case ARM::VLDMSDB_UPD:
2010 DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2013 case ARM::LDMIA_RET:
2018 case ARM::LDMIA_UPD:
2019 case ARM::LDMDA_UPD:
2020 case ARM::LDMDB_UPD:
2021 case ARM::LDMIB_UPD:
2023 case ARM::tLDMIA_UPD:
2025 case ARM::t2LDMIA_RET:
2028 case ARM::t2LDMIA_UPD:
2029 case ARM::t2LDMDB_UPD:
2031 DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign);
2036 // We can't seem to determine the result latency of the def, assume it's 2.
2040 switch (UseTID.getOpcode()) {
2042 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2047 case ARM::VSTMDIA_UPD:
2048 case ARM::VSTMDDB_UPD:
2051 case ARM::VSTMSIA_UPD:
2052 case ARM::VSTMSDB_UPD:
2053 UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2060 case ARM::STMIA_UPD:
2061 case ARM::STMDA_UPD:
2062 case ARM::STMDB_UPD:
2063 case ARM::STMIB_UPD:
2065 case ARM::tSTMIA_UPD:
2070 case ARM::t2STMIA_UPD:
2071 case ARM::t2STMDB_UPD:
2072 UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign);
2077 // Assume it's read in the first stage.
2080 UseCycle = DefCycle - UseCycle + 1;
2083 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2084 // first def operand.
2085 if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1,
2088 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2089 UseClass, UseIdx)) {
2098 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2099 const MachineInstr *DefMI, unsigned DefIdx,
2100 const MachineInstr *UseMI, unsigned UseIdx) const {
2101 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2102 DefMI->isRegSequence() || DefMI->isImplicitDef())
2105 const TargetInstrDesc &DefTID = DefMI->getDesc();
2106 if (!ItinData || ItinData->isEmpty())
2107 return DefTID.mayLoad() ? 3 : 1;
2109 const TargetInstrDesc &UseTID = UseMI->getDesc();
2110 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2111 if (DefMO.getReg() == ARM::CPSR) {
2112 if (DefMI->getOpcode() == ARM::FMSTAT) {
2113 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2114 return Subtarget.isCortexA9() ? 1 : 20;
2117 // CPSR set and branch can be paired in the same cycle.
2118 if (UseTID.isBranch())
2122 unsigned DefAlign = DefMI->hasOneMemOperand()
2123 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2124 unsigned UseAlign = UseMI->hasOneMemOperand()
2125 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2126 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2127 UseTID, UseIdx, UseAlign);
2130 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2131 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2132 // variants are one cycle cheaper.
2133 switch (DefTID.getOpcode()) {
2137 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2138 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2140 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2147 case ARM::t2LDRSHs: {
2148 // Thumb2 mode: lsl only.
2149 unsigned ShAmt = DefMI->getOperand(3).getImm();
2150 if (ShAmt == 0 || ShAmt == 2)
2161 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2162 SDNode *DefNode, unsigned DefIdx,
2163 SDNode *UseNode, unsigned UseIdx) const {
2164 if (!DefNode->isMachineOpcode())
2167 const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode());
2169 if (isZeroCost(DefTID.Opcode))
2172 if (!ItinData || ItinData->isEmpty())
2173 return DefTID.mayLoad() ? 3 : 1;
2175 if (!UseNode->isMachineOpcode()) {
2176 int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx);
2177 if (Subtarget.isCortexA9())
2178 return Latency <= 2 ? 1 : Latency - 1;
2180 return Latency <= 3 ? 1 : Latency - 2;
2183 const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode());
2184 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2185 unsigned DefAlign = !DefMN->memoperands_empty()
2186 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2187 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2188 unsigned UseAlign = !UseMN->memoperands_empty()
2189 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2190 int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign,
2191 UseTID, UseIdx, UseAlign);
2194 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2195 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2196 // variants are one cycle cheaper.
2197 switch (DefTID.getOpcode()) {
2202 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2203 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2205 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2212 case ARM::t2LDRSHs: {
2213 // Thumb2 mode: lsl only.
2215 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2216 if (ShAmt == 0 || ShAmt == 2)
2226 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2227 const MachineInstr *MI,
2228 unsigned *PredCost) const {
2229 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2230 MI->isRegSequence() || MI->isImplicitDef())
2233 if (!ItinData || ItinData->isEmpty())
2236 const TargetInstrDesc &TID = MI->getDesc();
2237 unsigned Class = TID.getSchedClass();
2238 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2239 if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR))
2240 // When predicated, CPSR is an additional source operand for CPSR updating
2241 // instructions, this apparently increases their latencies.
2244 return ItinData->getStageLatency(Class);
2245 return getNumMicroOps(ItinData, MI);
2248 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2249 SDNode *Node) const {
2250 if (!Node->isMachineOpcode())
2253 if (!ItinData || ItinData->isEmpty())
2256 unsigned Opcode = Node->getMachineOpcode();
2259 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2268 bool ARMBaseInstrInfo::
2269 hasHighOperandLatency(const InstrItineraryData *ItinData,
2270 const MachineRegisterInfo *MRI,
2271 const MachineInstr *DefMI, unsigned DefIdx,
2272 const MachineInstr *UseMI, unsigned UseIdx) const {
2273 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2274 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2275 if (Subtarget.isCortexA8() &&
2276 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2277 // CortexA8 VFP instructions are not pipelined.
2280 // Hoist VFP / NEON instructions with 4 or higher latency.
2281 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2284 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2285 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2288 bool ARMBaseInstrInfo::
2289 hasLowDefLatency(const InstrItineraryData *ItinData,
2290 const MachineInstr *DefMI, unsigned DefIdx) const {
2291 if (!ItinData || ItinData->isEmpty())
2294 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2295 if (DDomain == ARMII::DomainGeneral) {
2296 unsigned DefClass = DefMI->getDesc().getSchedClass();
2297 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2298 return (DefCycle != -1 && DefCycle <= 2);
2304 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2305 unsigned &AddSubOpc,
2306 bool &NegAcc, bool &HasLane) const {
2307 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2308 if (I == MLxEntryMap.end())
2311 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2312 MulOpc = Entry.MulOpc;
2313 AddSubOpc = Entry.AddSubOpc;
2314 NegAcc = Entry.NegAcc;
2315 HasLane = Entry.HasLane;