1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
159 default: llvm_unreachable("Unknown indexed op!");
160 case ARMII::AddrMode2: {
161 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
162 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
164 if (ARM_AM::getSOImmVal(Amt) == -1)
165 // Can't encode it in a so_imm operand. This transformation will
166 // add more than 1 instruction. Abandon!
168 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
169 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
170 .addReg(BaseReg).addImm(Amt)
171 .addImm(Pred).addReg(0).addReg(0);
172 } else if (Amt != 0) {
173 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
174 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
175 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
176 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
178 .addImm(Pred).addReg(0).addReg(0);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
182 .addReg(BaseReg).addReg(OffReg)
183 .addImm(Pred).addReg(0).addReg(0);
186 case ARMII::AddrMode3 : {
187 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
188 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
190 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg).addImm(Amt)
194 .addImm(Pred).addReg(0).addReg(0);
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
198 .addReg(BaseReg).addReg(OffReg)
199 .addImm(Pred).addReg(0).addReg(0);
204 std::vector<MachineInstr*> NewMIs;
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc), MI->getOperand(0).getReg())
209 .addReg(WBReg).addImm(0).addImm(Pred);
211 MemMI = BuildMI(MF, MI->getDebugLoc(),
212 get(MemOpc)).addReg(MI->getOperand(1).getReg())
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
214 NewMIs.push_back(MemMI);
215 NewMIs.push_back(UpdateMI);
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(BaseReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
226 UpdateMI->getOperand(0).setIsDead();
227 NewMIs.push_back(UpdateMI);
228 NewMIs.push_back(MemMI);
231 // Transfer LiveVariables states, kill / dead info.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 MachineOperand &MO = MI->getOperand(i);
235 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
236 unsigned Reg = MO.getReg();
238 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
240 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
242 LV->addVirtualRegisterDead(Reg, NewMI);
244 if (MO.isUse() && MO.isKill()) {
245 for (unsigned j = 0; j < 2; ++j) {
246 // Look at the two new MI's in reverse order.
247 MachineInstr *NewMI = NewMIs[j];
248 if (!NewMI->readsRegister(Reg))
250 LV->addVirtualRegisterKilled(Reg, NewMI);
251 if (VI.removeKill(MI))
252 VI.Kills.push_back(NewMI);
260 MFI->insert(MBBI, NewMIs[1]);
261 MFI->insert(MBBI, NewMIs[0]);
267 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
268 MachineBasicBlock *&FBB,
269 SmallVectorImpl<MachineOperand> &Cond,
270 bool AllowModify) const {
271 // If the block has no terminators, it just falls into the block after it.
272 MachineBasicBlock::iterator I = MBB.end();
273 if (I == MBB.begin())
276 while (I->isDebugValue()) {
277 if (I == MBB.begin())
281 if (!isUnpredicatedTerminator(I))
284 // Get the last instruction in the block.
285 MachineInstr *LastInst = I;
287 // If there is only one terminator instruction, process it.
288 unsigned LastOpc = LastInst->getOpcode();
289 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
290 if (isUncondBranchOpcode(LastOpc)) {
291 TBB = LastInst->getOperand(0).getMBB();
294 if (isCondBranchOpcode(LastOpc)) {
295 // Block ends with fall-through condbranch.
296 TBB = LastInst->getOperand(0).getMBB();
297 Cond.push_back(LastInst->getOperand(1));
298 Cond.push_back(LastInst->getOperand(2));
301 return true; // Can't handle indirect branch.
304 // Get the instruction before it if it is a terminator.
305 MachineInstr *SecondLastInst = I;
306 unsigned SecondLastOpc = SecondLastInst->getOpcode();
308 // If AllowModify is true and the block ends with two or more unconditional
309 // branches, delete all but the first unconditional branch.
310 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
311 while (isUncondBranchOpcode(SecondLastOpc)) {
312 LastInst->eraseFromParent();
313 LastInst = SecondLastInst;
314 LastOpc = LastInst->getOpcode();
315 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
316 // Return now the only terminator is an unconditional branch.
317 TBB = LastInst->getOperand(0).getMBB();
321 SecondLastOpc = SecondLastInst->getOpcode();
326 // If there are three terminators, we don't know what sort of block this is.
327 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
330 // If the block ends with a B and a Bcc, handle it.
331 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
332 TBB = SecondLastInst->getOperand(0).getMBB();
333 Cond.push_back(SecondLastInst->getOperand(1));
334 Cond.push_back(SecondLastInst->getOperand(2));
335 FBB = LastInst->getOperand(0).getMBB();
339 // If the block ends with two unconditional branches, handle it. The second
340 // one is not executed, so remove it.
341 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
342 TBB = SecondLastInst->getOperand(0).getMBB();
345 I->eraseFromParent();
349 // ...likewise if it ends with a branch table followed by an unconditional
350 // branch. The branch folder can create these, and we must get rid of them for
351 // correctness of Thumb constant islands.
352 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
353 isIndirectBranchOpcode(SecondLastOpc)) &&
354 isUncondBranchOpcode(LastOpc)) {
357 I->eraseFromParent();
361 // Otherwise, can't handle this.
366 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 MachineBasicBlock::iterator I = MBB.end();
368 if (I == MBB.begin()) return 0;
370 while (I->isDebugValue()) {
371 if (I == MBB.begin())
375 if (!isUncondBranchOpcode(I->getOpcode()) &&
376 !isCondBranchOpcode(I->getOpcode()))
379 // Remove the branch.
380 I->eraseFromParent();
384 if (I == MBB.begin()) return 1;
386 if (!isCondBranchOpcode(I->getOpcode()))
389 // Remove the branch.
390 I->eraseFromParent();
395 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
396 MachineBasicBlock *FBB,
397 const SmallVectorImpl<MachineOperand> &Cond,
399 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
400 int BOpc = !AFI->isThumbFunction()
401 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
402 int BccOpc = !AFI->isThumbFunction()
403 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
404 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
406 // Shouldn't be a fall through.
407 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
408 assert((Cond.size() == 2 || Cond.size() == 0) &&
409 "ARM branch conditions have two components!");
412 if (Cond.empty()) { // Unconditional branch?
414 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
418 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
419 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
423 // Two-way conditional branch.
424 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
425 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
427 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
433 bool ARMBaseInstrInfo::
434 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
435 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
436 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
440 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
441 if (MI->isBundle()) {
442 MachineBasicBlock::const_instr_iterator I = MI;
443 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
444 while (++I != E && I->isInsideBundle()) {
445 int PIdx = I->findFirstPredOperandIdx();
446 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
452 int PIdx = MI->findFirstPredOperandIdx();
453 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
456 bool ARMBaseInstrInfo::
457 PredicateInstruction(MachineInstr *MI,
458 const SmallVectorImpl<MachineOperand> &Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
463 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
467 int PIdx = MI->findFirstPredOperandIdx();
469 MachineOperand &PMO = MI->getOperand(PIdx);
470 PMO.setImm(Pred[0].getImm());
471 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
477 bool ARMBaseInstrInfo::
478 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
479 const SmallVectorImpl<MachineOperand> &Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 /// isPredicable - Return true if the specified instruction can be predicated.
520 /// By default, this returns true for every instruction with a
521 /// PredicateOperand.
522 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
523 if (!MI->isPredicable())
526 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
527 ARMFunctionInfo *AFI =
528 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return AFI->isThumb2Function();
534 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
535 LLVM_ATTRIBUTE_NOINLINE
536 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
538 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
540 assert(JTI < JT.size());
541 return JT[JTI].MBBs.size();
544 /// GetInstSize - Return the size of the specified MachineInstr.
546 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
547 const MachineBasicBlock &MBB = *MI->getParent();
548 const MachineFunction *MF = MBB.getParent();
549 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
551 const MCInstrDesc &MCID = MI->getDesc();
553 return MCID.getSize();
555 // If this machine instr is an inline asm, measure it.
556 if (MI->getOpcode() == ARM::INLINEASM)
557 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
560 unsigned Opc = MI->getOpcode();
562 case TargetOpcode::IMPLICIT_DEF:
563 case TargetOpcode::KILL:
564 case TargetOpcode::PROLOG_LABEL:
565 case TargetOpcode::EH_LABEL:
566 case TargetOpcode::DBG_VALUE:
568 case TargetOpcode::BUNDLE:
569 return getInstBundleLength(MI);
570 case ARM::MOVi16_ga_pcrel:
571 case ARM::MOVTi16_ga_pcrel:
572 case ARM::t2MOVi16_ga_pcrel:
573 case ARM::t2MOVTi16_ga_pcrel:
576 case ARM::t2MOVi32imm:
578 case ARM::CONSTPOOL_ENTRY:
579 // If this machine instr is a constant pool entry, its size is recorded as
581 return MI->getOperand(2).getImm();
582 case ARM::Int_eh_sjlj_longjmp:
584 case ARM::tInt_eh_sjlj_longjmp:
586 case ARM::Int_eh_sjlj_setjmp:
587 case ARM::Int_eh_sjlj_setjmp_nofp:
589 case ARM::tInt_eh_sjlj_setjmp:
590 case ARM::t2Int_eh_sjlj_setjmp:
591 case ARM::t2Int_eh_sjlj_setjmp_nofp:
599 case ARM::t2TBH_JT: {
600 // These are jumptable branches, i.e. a branch followed by an inlined
601 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
602 // entry is one byte; TBH two byte each.
603 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
604 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
605 unsigned NumOps = MCID.getNumOperands();
606 MachineOperand JTOP =
607 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
608 unsigned JTI = JTOP.getIndex();
609 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
611 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
612 assert(JTI < JT.size());
613 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
614 // 4 aligned. The assembler / linker may add 2 byte padding just before
615 // the JT entries. The size does not include this padding; the
616 // constant islands pass does separate bookkeeping for it.
617 // FIXME: If we know the size of the function is less than (1 << 16) *2
618 // bytes, we can use 16-bit entries instead. Then there won't be an
620 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
621 unsigned NumEntries = getNumJTEntries(JT, JTI);
622 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
623 // Make sure the instruction that follows TBB is 2-byte aligned.
624 // FIXME: Constant island pass should insert an "ALIGN" instruction
627 return NumEntries * EntrySize + InstSize;
630 // Otherwise, pseudo-instruction sizes are zero.
635 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
637 MachineBasicBlock::const_instr_iterator I = MI;
638 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
639 while (++I != E && I->isInsideBundle()) {
640 assert(!I->isBundle() && "No nested bundle!");
641 Size += GetInstSizeInBytes(&*I);
646 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
647 MachineBasicBlock::iterator I, DebugLoc DL,
648 unsigned DestReg, unsigned SrcReg,
649 bool KillSrc) const {
650 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
653 if (GPRDest && GPRSrc) {
654 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
655 .addReg(SrcReg, getKillRegState(KillSrc))));
659 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
663 if (SPRDest && SPRSrc)
665 else if (GPRDest && SPRSrc)
667 else if (SPRDest && GPRSrc)
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
675 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
676 MIB.addReg(SrcReg, getKillRegState(KillSrc));
677 if (Opc == ARM::VORRq)
678 MIB.addReg(SrcReg, getKillRegState(KillSrc));
683 // Handle register classes that require multiple instructions.
684 unsigned BeginIdx = 0;
685 unsigned SubRegs = 0;
686 unsigned Spacing = 1;
688 // Use VORRq when possible.
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
693 // Fall back to VMOVD.
694 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
696 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
698 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
701 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
709 const TargetRegisterInfo *TRI = &getRegisterInfo();
710 MachineInstrBuilder Mov;
711 for (unsigned i = 0; i != SubRegs; ++i) {
712 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
713 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
714 assert(Dst && Src && "Bad sub-register");
715 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
717 // VORR takes two source operands.
718 if (Opc == ARM::VORRq)
720 Mov = AddDefaultPred(Mov);
722 // Add implicit super-register defs and kills to the last instruction.
723 Mov->addRegisterDefined(DestReg, TRI);
725 Mov->addRegisterKilled(SrcReg, TRI);
729 llvm_unreachable("Impossible reg-to-reg copy");
733 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
734 unsigned Reg, unsigned SubIdx, unsigned State,
735 const TargetRegisterInfo *TRI) {
737 return MIB.addReg(Reg, State);
739 if (TargetRegisterInfo::isPhysicalRegister(Reg))
740 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
741 return MIB.addReg(Reg, State, SubIdx);
744 void ARMBaseInstrInfo::
745 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
746 unsigned SrcReg, bool isKill, int FI,
747 const TargetRegisterClass *RC,
748 const TargetRegisterInfo *TRI) const {
750 if (I != MBB.end()) DL = I->getDebugLoc();
751 MachineFunction &MF = *MBB.getParent();
752 MachineFrameInfo &MFI = *MF.getFrameInfo();
753 unsigned Align = MFI.getObjectAlignment(FI);
755 MachineMemOperand *MMO =
756 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
757 MachineMemOperand::MOStore,
758 MFI.getObjectSize(FI),
761 switch (RC->getSize()) {
763 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
764 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
765 .addReg(SrcReg, getKillRegState(isKill))
766 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
767 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
768 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
769 .addReg(SrcReg, getKillRegState(isKill))
770 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
772 llvm_unreachable("Unknown reg class!");
775 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
776 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
777 .addReg(SrcReg, getKillRegState(isKill))
778 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
780 llvm_unreachable("Unknown reg class!");
783 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
784 // Use aligned spills if the stack can be realigned.
785 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
786 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
787 .addFrameIndex(FI).addImm(16)
788 .addReg(SrcReg, getKillRegState(isKill))
789 .addMemOperand(MMO));
791 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
792 .addReg(SrcReg, getKillRegState(isKill))
794 .addMemOperand(MMO));
797 llvm_unreachable("Unknown reg class!");
800 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
801 // Use aligned spills if the stack can be realigned.
802 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
804 .addFrameIndex(FI).addImm(16)
805 .addReg(SrcReg, getKillRegState(isKill))
806 .addMemOperand(MMO));
808 MachineInstrBuilder MIB =
809 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
814 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
817 llvm_unreachable("Unknown reg class!");
820 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
821 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
822 // FIXME: It's possible to only store part of the QQ register if the
823 // spilled def has a sub-register index.
824 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
825 .addFrameIndex(FI).addImm(16)
826 .addReg(SrcReg, getKillRegState(isKill))
827 .addMemOperand(MMO));
829 MachineInstrBuilder MIB =
830 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
833 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
834 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
835 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
836 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
839 llvm_unreachable("Unknown reg class!");
842 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
843 MachineInstrBuilder MIB =
844 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
847 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
850 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
851 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
852 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
853 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
854 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
856 llvm_unreachable("Unknown reg class!");
859 llvm_unreachable("Unknown reg class!");
864 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
865 int &FrameIndex) const {
866 switch (MI->getOpcode()) {
869 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
870 if (MI->getOperand(1).isFI() &&
871 MI->getOperand(2).isReg() &&
872 MI->getOperand(3).isImm() &&
873 MI->getOperand(2).getReg() == 0 &&
874 MI->getOperand(3).getImm() == 0) {
875 FrameIndex = MI->getOperand(1).getIndex();
876 return MI->getOperand(0).getReg();
884 if (MI->getOperand(1).isFI() &&
885 MI->getOperand(2).isImm() &&
886 MI->getOperand(2).getImm() == 0) {
887 FrameIndex = MI->getOperand(1).getIndex();
888 return MI->getOperand(0).getReg();
892 case ARM::VST1d64TPseudo:
893 case ARM::VST1d64QPseudo:
894 if (MI->getOperand(0).isFI() &&
895 MI->getOperand(2).getSubReg() == 0) {
896 FrameIndex = MI->getOperand(0).getIndex();
897 return MI->getOperand(2).getReg();
901 if (MI->getOperand(1).isFI() &&
902 MI->getOperand(0).getSubReg() == 0) {
903 FrameIndex = MI->getOperand(1).getIndex();
904 return MI->getOperand(0).getReg();
912 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
913 int &FrameIndex) const {
914 const MachineMemOperand *Dummy;
915 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
918 void ARMBaseInstrInfo::
919 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
920 unsigned DestReg, int FI,
921 const TargetRegisterClass *RC,
922 const TargetRegisterInfo *TRI) const {
924 if (I != MBB.end()) DL = I->getDebugLoc();
925 MachineFunction &MF = *MBB.getParent();
926 MachineFrameInfo &MFI = *MF.getFrameInfo();
927 unsigned Align = MFI.getObjectAlignment(FI);
928 MachineMemOperand *MMO =
929 MF.getMachineMemOperand(
930 MachinePointerInfo::getFixedStack(FI),
931 MachineMemOperand::MOLoad,
932 MFI.getObjectSize(FI),
935 switch (RC->getSize()) {
937 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
938 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
939 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
941 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
942 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
943 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
945 llvm_unreachable("Unknown reg class!");
948 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
949 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
950 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
952 llvm_unreachable("Unknown reg class!");
955 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
956 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
957 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
958 .addFrameIndex(FI).addImm(16)
959 .addMemOperand(MMO));
961 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
963 .addMemOperand(MMO));
966 llvm_unreachable("Unknown reg class!");
969 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
970 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
971 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
972 .addFrameIndex(FI).addImm(16)
973 .addMemOperand(MMO));
975 MachineInstrBuilder MIB =
976 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
978 .addMemOperand(MMO));
979 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
980 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
981 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
982 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
983 MIB.addReg(DestReg, RegState::ImplicitDefine);
986 llvm_unreachable("Unknown reg class!");
989 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
990 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
991 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
992 .addFrameIndex(FI).addImm(16)
993 .addMemOperand(MMO));
995 MachineInstrBuilder MIB =
996 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
999 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1000 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1001 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1002 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1003 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1004 MIB.addReg(DestReg, RegState::ImplicitDefine);
1007 llvm_unreachable("Unknown reg class!");
1010 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1011 MachineInstrBuilder MIB =
1012 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1014 .addMemOperand(MMO);
1015 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1016 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1017 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1018 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1019 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1020 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1021 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1022 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1023 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1024 MIB.addReg(DestReg, RegState::ImplicitDefine);
1026 llvm_unreachable("Unknown reg class!");
1029 llvm_unreachable("Unknown regclass!");
1034 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1035 int &FrameIndex) const {
1036 switch (MI->getOpcode()) {
1039 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1040 if (MI->getOperand(1).isFI() &&
1041 MI->getOperand(2).isReg() &&
1042 MI->getOperand(3).isImm() &&
1043 MI->getOperand(2).getReg() == 0 &&
1044 MI->getOperand(3).getImm() == 0) {
1045 FrameIndex = MI->getOperand(1).getIndex();
1046 return MI->getOperand(0).getReg();
1054 if (MI->getOperand(1).isFI() &&
1055 MI->getOperand(2).isImm() &&
1056 MI->getOperand(2).getImm() == 0) {
1057 FrameIndex = MI->getOperand(1).getIndex();
1058 return MI->getOperand(0).getReg();
1062 case ARM::VLD1d64TPseudo:
1063 case ARM::VLD1d64QPseudo:
1064 if (MI->getOperand(1).isFI() &&
1065 MI->getOperand(0).getSubReg() == 0) {
1066 FrameIndex = MI->getOperand(1).getIndex();
1067 return MI->getOperand(0).getReg();
1071 if (MI->getOperand(1).isFI() &&
1072 MI->getOperand(0).getSubReg() == 0) {
1073 FrameIndex = MI->getOperand(1).getIndex();
1074 return MI->getOperand(0).getReg();
1082 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1083 int &FrameIndex) const {
1084 const MachineMemOperand *Dummy;
1085 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1088 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1089 // This hook gets to expand COPY instructions before they become
1090 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1091 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1092 // changed into a VORR that can go down the NEON pipeline.
1093 if (!WidenVMOVS || !MI->isCopy())
1096 // Look for a copy between even S-registers. That is where we keep floats
1097 // when using NEON v2f32 instructions for f32 arithmetic.
1098 unsigned DstRegS = MI->getOperand(0).getReg();
1099 unsigned SrcRegS = MI->getOperand(1).getReg();
1100 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1103 const TargetRegisterInfo *TRI = &getRegisterInfo();
1104 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1106 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1108 if (!DstRegD || !SrcRegD)
1111 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1112 // legal if the COPY already defines the full DstRegD, and it isn't a
1113 // sub-register insertion.
1114 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1117 // A dead copy shouldn't show up here, but reject it just in case.
1118 if (MI->getOperand(0).isDead())
1121 // All clear, widen the COPY.
1122 DEBUG(dbgs() << "widening: " << *MI);
1124 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1125 // or some other super-register.
1126 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1127 if (ImpDefIdx != -1)
1128 MI->RemoveOperand(ImpDefIdx);
1130 // Change the opcode and operands.
1131 MI->setDesc(get(ARM::VMOVD));
1132 MI->getOperand(0).setReg(DstRegD);
1133 MI->getOperand(1).setReg(SrcRegD);
1134 AddDefaultPred(MachineInstrBuilder(MI));
1136 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1137 // register scavenger and machine verifier, so we need to indicate that we
1138 // are reading an undefined value from SrcRegD, but a proper value from
1140 MI->getOperand(1).setIsUndef();
1141 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1143 // SrcRegD may actually contain an unrelated value in the ssub_1
1144 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1145 if (MI->getOperand(1).isKill()) {
1146 MI->getOperand(1).setIsKill(false);
1147 MI->addRegisterKilled(SrcRegS, TRI, true);
1150 DEBUG(dbgs() << "replaced by: " << *MI);
1155 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1156 int FrameIx, uint64_t Offset,
1157 const MDNode *MDPtr,
1158 DebugLoc DL) const {
1159 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1160 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1164 /// Create a copy of a const pool value. Update CPI to the new index and return
1166 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1167 MachineConstantPool *MCP = MF.getConstantPool();
1168 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1170 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1171 assert(MCPE.isMachineConstantPoolEntry() &&
1172 "Expecting a machine constantpool entry!");
1173 ARMConstantPoolValue *ACPV =
1174 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1176 unsigned PCLabelId = AFI->createPICLabelUId();
1177 ARMConstantPoolValue *NewCPV = 0;
1178 // FIXME: The below assumes PIC relocation model and that the function
1179 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1180 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1181 // instructions, so that's probably OK, but is PIC always correct when
1183 if (ACPV->isGlobalValue())
1184 NewCPV = ARMConstantPoolConstant::
1185 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1187 else if (ACPV->isExtSymbol())
1188 NewCPV = ARMConstantPoolSymbol::
1189 Create(MF.getFunction()->getContext(),
1190 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1191 else if (ACPV->isBlockAddress())
1192 NewCPV = ARMConstantPoolConstant::
1193 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1194 ARMCP::CPBlockAddress, 4);
1195 else if (ACPV->isLSDA())
1196 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1198 else if (ACPV->isMachineBasicBlock())
1199 NewCPV = ARMConstantPoolMBB::
1200 Create(MF.getFunction()->getContext(),
1201 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1203 llvm_unreachable("Unexpected ARM constantpool value type!!");
1204 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1208 void ARMBaseInstrInfo::
1209 reMaterialize(MachineBasicBlock &MBB,
1210 MachineBasicBlock::iterator I,
1211 unsigned DestReg, unsigned SubIdx,
1212 const MachineInstr *Orig,
1213 const TargetRegisterInfo &TRI) const {
1214 unsigned Opcode = Orig->getOpcode();
1217 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1218 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1222 case ARM::tLDRpci_pic:
1223 case ARM::t2LDRpci_pic: {
1224 MachineFunction &MF = *MBB.getParent();
1225 unsigned CPI = Orig->getOperand(1).getIndex();
1226 unsigned PCLabelId = duplicateCPV(MF, CPI);
1227 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1229 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1230 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1237 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1238 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1239 switch(Orig->getOpcode()) {
1240 case ARM::tLDRpci_pic:
1241 case ARM::t2LDRpci_pic: {
1242 unsigned CPI = Orig->getOperand(1).getIndex();
1243 unsigned PCLabelId = duplicateCPV(MF, CPI);
1244 Orig->getOperand(1).setIndex(CPI);
1245 Orig->getOperand(2).setImm(PCLabelId);
1252 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1253 const MachineInstr *MI1,
1254 const MachineRegisterInfo *MRI) const {
1255 int Opcode = MI0->getOpcode();
1256 if (Opcode == ARM::t2LDRpci ||
1257 Opcode == ARM::t2LDRpci_pic ||
1258 Opcode == ARM::tLDRpci ||
1259 Opcode == ARM::tLDRpci_pic ||
1260 Opcode == ARM::MOV_ga_dyn ||
1261 Opcode == ARM::MOV_ga_pcrel ||
1262 Opcode == ARM::MOV_ga_pcrel_ldr ||
1263 Opcode == ARM::t2MOV_ga_dyn ||
1264 Opcode == ARM::t2MOV_ga_pcrel) {
1265 if (MI1->getOpcode() != Opcode)
1267 if (MI0->getNumOperands() != MI1->getNumOperands())
1270 const MachineOperand &MO0 = MI0->getOperand(1);
1271 const MachineOperand &MO1 = MI1->getOperand(1);
1272 if (MO0.getOffset() != MO1.getOffset())
1275 if (Opcode == ARM::MOV_ga_dyn ||
1276 Opcode == ARM::MOV_ga_pcrel ||
1277 Opcode == ARM::MOV_ga_pcrel_ldr ||
1278 Opcode == ARM::t2MOV_ga_dyn ||
1279 Opcode == ARM::t2MOV_ga_pcrel)
1280 // Ignore the PC labels.
1281 return MO0.getGlobal() == MO1.getGlobal();
1283 const MachineFunction *MF = MI0->getParent()->getParent();
1284 const MachineConstantPool *MCP = MF->getConstantPool();
1285 int CPI0 = MO0.getIndex();
1286 int CPI1 = MO1.getIndex();
1287 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1288 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1289 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1290 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1291 if (isARMCP0 && isARMCP1) {
1292 ARMConstantPoolValue *ACPV0 =
1293 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1294 ARMConstantPoolValue *ACPV1 =
1295 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1296 return ACPV0->hasSameValue(ACPV1);
1297 } else if (!isARMCP0 && !isARMCP1) {
1298 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1301 } else if (Opcode == ARM::PICLDR) {
1302 if (MI1->getOpcode() != Opcode)
1304 if (MI0->getNumOperands() != MI1->getNumOperands())
1307 unsigned Addr0 = MI0->getOperand(1).getReg();
1308 unsigned Addr1 = MI1->getOperand(1).getReg();
1309 if (Addr0 != Addr1) {
1311 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1312 !TargetRegisterInfo::isVirtualRegister(Addr1))
1315 // This assumes SSA form.
1316 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1317 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1318 // Check if the loaded value, e.g. a constantpool of a global address, are
1320 if (!produceSameValue(Def0, Def1, MRI))
1324 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1325 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1326 const MachineOperand &MO0 = MI0->getOperand(i);
1327 const MachineOperand &MO1 = MI1->getOperand(i);
1328 if (!MO0.isIdenticalTo(MO1))
1334 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1337 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1338 /// determine if two loads are loading from the same base address. It should
1339 /// only return true if the base pointers are the same and the only differences
1340 /// between the two addresses is the offset. It also returns the offsets by
1342 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1344 int64_t &Offset2) const {
1345 // Don't worry about Thumb: just ARM and Thumb2.
1346 if (Subtarget.isThumb1Only()) return false;
1348 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1351 switch (Load1->getMachineOpcode()) {
1364 case ARM::t2LDRSHi8:
1366 case ARM::t2LDRSHi12:
1370 switch (Load2->getMachineOpcode()) {
1383 case ARM::t2LDRSHi8:
1385 case ARM::t2LDRSHi12:
1389 // Check if base addresses and chain operands match.
1390 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1391 Load1->getOperand(4) != Load2->getOperand(4))
1394 // Index should be Reg0.
1395 if (Load1->getOperand(3) != Load2->getOperand(3))
1398 // Determine the offsets.
1399 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1400 isa<ConstantSDNode>(Load2->getOperand(1))) {
1401 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1402 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1409 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1410 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1411 /// be scheduled togther. On some targets if two loads are loading from
1412 /// addresses in the same cache line, it's better if they are scheduled
1413 /// together. This function takes two integers that represent the load offsets
1414 /// from the common base address. It returns true if it decides it's desirable
1415 /// to schedule the two loads together. "NumLoads" is the number of loads that
1416 /// have already been scheduled after Load1.
1417 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1418 int64_t Offset1, int64_t Offset2,
1419 unsigned NumLoads) const {
1420 // Don't worry about Thumb: just ARM and Thumb2.
1421 if (Subtarget.isThumb1Only()) return false;
1423 assert(Offset2 > Offset1);
1425 if ((Offset2 - Offset1) / 8 > 64)
1428 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1429 return false; // FIXME: overly conservative?
1431 // Four loads in a row should be sufficient.
1438 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1439 const MachineBasicBlock *MBB,
1440 const MachineFunction &MF) const {
1441 // Debug info is never a scheduling boundary. It's necessary to be explicit
1442 // due to the special treatment of IT instructions below, otherwise a
1443 // dbg_value followed by an IT will result in the IT instruction being
1444 // considered a scheduling hazard, which is wrong. It should be the actual
1445 // instruction preceding the dbg_value instruction(s), just like it is
1446 // when debug info is not present.
1447 if (MI->isDebugValue())
1450 // Terminators and labels can't be scheduled around.
1451 if (MI->isTerminator() || MI->isLabel())
1454 // Treat the start of the IT block as a scheduling boundary, but schedule
1455 // t2IT along with all instructions following it.
1456 // FIXME: This is a big hammer. But the alternative is to add all potential
1457 // true and anti dependencies to IT block instructions as implicit operands
1458 // to the t2IT instruction. The added compile time and complexity does not
1460 MachineBasicBlock::const_iterator I = MI;
1461 // Make sure to skip any dbg_value instructions
1462 while (++I != MBB->end() && I->isDebugValue())
1464 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1467 // Don't attempt to schedule around any instruction that defines
1468 // a stack-oriented pointer, as it's unlikely to be profitable. This
1469 // saves compile time, because it doesn't require every single
1470 // stack slot reference to depend on the instruction that does the
1472 // Calls don't actually change the stack pointer, even if they have imp-defs.
1473 // No ARM calling conventions change the stack pointer. (X86 calling
1474 // conventions sometimes do).
1475 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1481 bool ARMBaseInstrInfo::
1482 isProfitableToIfCvt(MachineBasicBlock &MBB,
1483 unsigned NumCycles, unsigned ExtraPredCycles,
1484 const BranchProbability &Probability) const {
1488 // Attempt to estimate the relative costs of predication versus branching.
1489 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1490 UnpredCost /= Probability.getDenominator();
1491 UnpredCost += 1; // The branch itself
1492 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1494 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1497 bool ARMBaseInstrInfo::
1498 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1499 unsigned TCycles, unsigned TExtra,
1500 MachineBasicBlock &FMBB,
1501 unsigned FCycles, unsigned FExtra,
1502 const BranchProbability &Probability) const {
1503 if (!TCycles || !FCycles)
1506 // Attempt to estimate the relative costs of predication versus branching.
1507 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1508 TUnpredCost /= Probability.getDenominator();
1510 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1511 unsigned FUnpredCost = Comp * FCycles;
1512 FUnpredCost /= Probability.getDenominator();
1514 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1515 UnpredCost += 1; // The branch itself
1516 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1518 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1521 /// getInstrPredicate - If instruction is predicated, returns its predicate
1522 /// condition, otherwise returns AL. It also returns the condition code
1523 /// register by reference.
1525 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1526 int PIdx = MI->findFirstPredOperandIdx();
1532 PredReg = MI->getOperand(PIdx+1).getReg();
1533 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1537 int llvm::getMatchingCondBranchOpcode(int Opc) {
1542 if (Opc == ARM::t2B)
1545 llvm_unreachable("Unknown unconditional branch opcode!");
1548 /// commuteInstruction - Handle commutable instructions.
1550 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1551 switch (MI->getOpcode()) {
1553 case ARM::t2MOVCCr: {
1554 // MOVCC can be commuted by inverting the condition.
1555 unsigned PredReg = 0;
1556 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1557 // MOVCC AL can't be inverted. Shouldn't happen.
1558 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1560 MI = TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1563 // After swapping the MOVCC operands, also invert the condition.
1564 MI->getOperand(MI->findFirstPredOperandIdx())
1565 .setImm(ARMCC::getOppositeCondition(CC));
1569 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1572 /// Identify instructions that can be folded into a MOVCC instruction, and
1573 /// return the corresponding opcode for the predicated pseudo-instruction.
1574 static unsigned canFoldIntoMOVCC(unsigned Reg, MachineInstr *&MI,
1575 const MachineRegisterInfo &MRI) {
1576 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1578 if (!MRI.hasOneNonDBGUse(Reg))
1580 MI = MRI.getVRegDef(Reg);
1583 // Check if MI has any non-dead defs or physreg uses. This also detects
1584 // predicated instructions which will be reading CPSR.
1585 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1586 const MachineOperand &MO = MI->getOperand(i);
1587 // Reject frame index operands, PEI can't handle the predicated pseudos.
1588 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1592 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1594 if (MO.isDef() && !MO.isDead())
1597 switch (MI->getOpcode()) {
1599 case ARM::ANDri: return ARM::ANDCCri;
1600 case ARM::ANDrr: return ARM::ANDCCrr;
1601 case ARM::ANDrsi: return ARM::ANDCCrsi;
1602 case ARM::ANDrsr: return ARM::ANDCCrsr;
1603 case ARM::t2ANDri: return ARM::t2ANDCCri;
1604 case ARM::t2ANDrr: return ARM::t2ANDCCrr;
1605 case ARM::t2ANDrs: return ARM::t2ANDCCrs;
1606 case ARM::EORri: return ARM::EORCCri;
1607 case ARM::EORrr: return ARM::EORCCrr;
1608 case ARM::EORrsi: return ARM::EORCCrsi;
1609 case ARM::EORrsr: return ARM::EORCCrsr;
1610 case ARM::t2EORri: return ARM::t2EORCCri;
1611 case ARM::t2EORrr: return ARM::t2EORCCrr;
1612 case ARM::t2EORrs: return ARM::t2EORCCrs;
1613 case ARM::ORRri: return ARM::ORRCCri;
1614 case ARM::ORRrr: return ARM::ORRCCrr;
1615 case ARM::ORRrsi: return ARM::ORRCCrsi;
1616 case ARM::ORRrsr: return ARM::ORRCCrsr;
1617 case ARM::t2ORRri: return ARM::t2ORRCCri;
1618 case ARM::t2ORRrr: return ARM::t2ORRCCrr;
1619 case ARM::t2ORRrs: return ARM::t2ORRCCrs;
1622 case ARM::ADDri: return ARM::ADDCCri;
1623 case ARM::ADDrr: return ARM::ADDCCrr;
1624 case ARM::ADDrsi: return ARM::ADDCCrsi;
1625 case ARM::ADDrsr: return ARM::ADDCCrsr;
1626 case ARM::SUBri: return ARM::SUBCCri;
1627 case ARM::SUBrr: return ARM::SUBCCrr;
1628 case ARM::SUBrsi: return ARM::SUBCCrsi;
1629 case ARM::SUBrsr: return ARM::SUBCCrsr;
1632 case ARM::t2ADDri: return ARM::t2ADDCCri;
1633 case ARM::t2ADDri12: return ARM::t2ADDCCri12;
1634 case ARM::t2ADDrr: return ARM::t2ADDCCrr;
1635 case ARM::t2ADDrs: return ARM::t2ADDCCrs;
1636 case ARM::t2SUBri: return ARM::t2SUBCCri;
1637 case ARM::t2SUBri12: return ARM::t2SUBCCri12;
1638 case ARM::t2SUBrr: return ARM::t2SUBCCrr;
1639 case ARM::t2SUBrs: return ARM::t2SUBCCrs;
1643 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1644 SmallVectorImpl<MachineOperand> &Cond,
1645 unsigned &TrueOp, unsigned &FalseOp,
1646 bool &Optimizable) const {
1647 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1648 "Unknown select instruction");
1653 // 3: Condition code.
1657 Cond.push_back(MI->getOperand(3));
1658 Cond.push_back(MI->getOperand(4));
1659 // We can always fold a def.
1664 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1665 bool PreferFalse) const {
1666 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1667 "Unknown select instruction");
1668 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1669 MachineInstr *DefMI = 0;
1670 unsigned Opc = canFoldIntoMOVCC(MI->getOperand(2).getReg(), DefMI, MRI);
1673 Opc = canFoldIntoMOVCC(MI->getOperand(1).getReg(), DefMI, MRI);
1677 // Create a new predicated version of DefMI.
1678 // Rfalse is the first use.
1679 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1680 get(Opc), MI->getOperand(0).getReg())
1681 .addOperand(MI->getOperand(Invert ? 2 : 1));
1683 // Copy all the DefMI operands, excluding its (null) predicate.
1684 const MCInstrDesc &DefDesc = DefMI->getDesc();
1685 for (unsigned i = 1, e = DefDesc.getNumOperands();
1686 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1687 NewMI.addOperand(DefMI->getOperand(i));
1689 unsigned CondCode = MI->getOperand(3).getImm();
1691 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1693 NewMI.addImm(CondCode);
1694 NewMI.addOperand(MI->getOperand(4));
1696 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1697 if (NewMI->hasOptionalDef())
1698 AddDefaultCC(NewMI);
1700 // The caller will erase MI, but not DefMI.
1701 DefMI->eraseFromParent();
1705 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1706 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1709 /// This will go away once we can teach tblgen how to set the optional CPSR def
1711 struct AddSubFlagsOpcodePair {
1713 uint16_t MachineOpc;
1716 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1717 {ARM::ADDSri, ARM::ADDri},
1718 {ARM::ADDSrr, ARM::ADDrr},
1719 {ARM::ADDSrsi, ARM::ADDrsi},
1720 {ARM::ADDSrsr, ARM::ADDrsr},
1722 {ARM::SUBSri, ARM::SUBri},
1723 {ARM::SUBSrr, ARM::SUBrr},
1724 {ARM::SUBSrsi, ARM::SUBrsi},
1725 {ARM::SUBSrsr, ARM::SUBrsr},
1727 {ARM::RSBSri, ARM::RSBri},
1728 {ARM::RSBSrsi, ARM::RSBrsi},
1729 {ARM::RSBSrsr, ARM::RSBrsr},
1731 {ARM::t2ADDSri, ARM::t2ADDri},
1732 {ARM::t2ADDSrr, ARM::t2ADDrr},
1733 {ARM::t2ADDSrs, ARM::t2ADDrs},
1735 {ARM::t2SUBSri, ARM::t2SUBri},
1736 {ARM::t2SUBSrr, ARM::t2SUBrr},
1737 {ARM::t2SUBSrs, ARM::t2SUBrs},
1739 {ARM::t2RSBSri, ARM::t2RSBri},
1740 {ARM::t2RSBSrs, ARM::t2RSBrs},
1743 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1744 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1745 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1746 return AddSubFlagsOpcodeMap[i].MachineOpc;
1750 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1751 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1752 unsigned DestReg, unsigned BaseReg, int NumBytes,
1753 ARMCC::CondCodes Pred, unsigned PredReg,
1754 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1755 bool isSub = NumBytes < 0;
1756 if (isSub) NumBytes = -NumBytes;
1759 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1760 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1761 assert(ThisVal && "Didn't extract field correctly");
1763 // We will handle these bits from offset, clear them.
1764 NumBytes &= ~ThisVal;
1766 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1768 // Build the new ADD / SUB.
1769 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1770 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1771 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1772 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1773 .setMIFlags(MIFlags);
1778 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1779 unsigned FrameReg, int &Offset,
1780 const ARMBaseInstrInfo &TII) {
1781 unsigned Opcode = MI.getOpcode();
1782 const MCInstrDesc &Desc = MI.getDesc();
1783 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1786 // Memory operands in inline assembly always use AddrMode2.
1787 if (Opcode == ARM::INLINEASM)
1788 AddrMode = ARMII::AddrMode2;
1790 if (Opcode == ARM::ADDri) {
1791 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1793 // Turn it into a move.
1794 MI.setDesc(TII.get(ARM::MOVr));
1795 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1796 MI.RemoveOperand(FrameRegIdx+1);
1799 } else if (Offset < 0) {
1802 MI.setDesc(TII.get(ARM::SUBri));
1805 // Common case: small offset, fits into instruction.
1806 if (ARM_AM::getSOImmVal(Offset) != -1) {
1807 // Replace the FrameIndex with sp / fp
1808 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1809 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1814 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1816 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1817 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1819 // We will handle these bits from offset, clear them.
1820 Offset &= ~ThisImmVal;
1822 // Get the properly encoded SOImmVal field.
1823 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1824 "Bit extraction didn't work?");
1825 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1827 unsigned ImmIdx = 0;
1829 unsigned NumBits = 0;
1832 case ARMII::AddrMode_i12: {
1833 ImmIdx = FrameRegIdx + 1;
1834 InstrOffs = MI.getOperand(ImmIdx).getImm();
1838 case ARMII::AddrMode2: {
1839 ImmIdx = FrameRegIdx+2;
1840 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1841 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1846 case ARMII::AddrMode3: {
1847 ImmIdx = FrameRegIdx+2;
1848 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1849 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1854 case ARMII::AddrMode4:
1855 case ARMII::AddrMode6:
1856 // Can't fold any offset even if it's zero.
1858 case ARMII::AddrMode5: {
1859 ImmIdx = FrameRegIdx+1;
1860 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1861 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1868 llvm_unreachable("Unsupported addressing mode!");
1871 Offset += InstrOffs * Scale;
1872 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1878 // Attempt to fold address comp. if opcode has offset bits
1880 // Common case: small offset, fits into instruction.
1881 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1882 int ImmedOffset = Offset / Scale;
1883 unsigned Mask = (1 << NumBits) - 1;
1884 if ((unsigned)Offset <= Mask * Scale) {
1885 // Replace the FrameIndex with sp
1886 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1887 // FIXME: When addrmode2 goes away, this will simplify (like the
1888 // T2 version), as the LDR.i12 versions don't need the encoding
1889 // tricks for the offset value.
1891 if (AddrMode == ARMII::AddrMode_i12)
1892 ImmedOffset = -ImmedOffset;
1894 ImmedOffset |= 1 << NumBits;
1896 ImmOp.ChangeToImmediate(ImmedOffset);
1901 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1902 ImmedOffset = ImmedOffset & Mask;
1904 if (AddrMode == ARMII::AddrMode_i12)
1905 ImmedOffset = -ImmedOffset;
1907 ImmedOffset |= 1 << NumBits;
1909 ImmOp.ChangeToImmediate(ImmedOffset);
1910 Offset &= ~(Mask*Scale);
1914 Offset = (isSub) ? -Offset : Offset;
1918 /// analyzeCompare - For a comparison instruction, return the source registers
1919 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1920 /// compares against in CmpValue. Return true if the comparison instruction
1921 /// can be analyzed.
1922 bool ARMBaseInstrInfo::
1923 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1924 int &CmpMask, int &CmpValue) const {
1925 switch (MI->getOpcode()) {
1929 SrcReg = MI->getOperand(0).getReg();
1932 CmpValue = MI->getOperand(1).getImm();
1936 SrcReg = MI->getOperand(0).getReg();
1937 SrcReg2 = MI->getOperand(1).getReg();
1943 SrcReg = MI->getOperand(0).getReg();
1945 CmpMask = MI->getOperand(1).getImm();
1953 /// isSuitableForMask - Identify a suitable 'and' instruction that
1954 /// operates on the given source register and applies the same mask
1955 /// as a 'tst' instruction. Provide a limited look-through for copies.
1956 /// When successful, MI will hold the found instruction.
1957 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1958 int CmpMask, bool CommonUse) {
1959 switch (MI->getOpcode()) {
1962 if (CmpMask != MI->getOperand(2).getImm())
1964 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1968 // Walk down one instruction which is potentially an 'and'.
1969 const MachineInstr &Copy = *MI;
1970 MachineBasicBlock::iterator AND(
1971 llvm::next(MachineBasicBlock::iterator(MI)));
1972 if (AND == MI->getParent()->end()) return false;
1974 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1982 /// getSwappedCondition - assume the flags are set by MI(a,b), return
1983 /// the condition code if we modify the instructions such that flags are
1985 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
1987 default: return ARMCC::AL;
1988 case ARMCC::EQ: return ARMCC::EQ;
1989 case ARMCC::NE: return ARMCC::NE;
1990 case ARMCC::HS: return ARMCC::LS;
1991 case ARMCC::LO: return ARMCC::HI;
1992 case ARMCC::HI: return ARMCC::LO;
1993 case ARMCC::LS: return ARMCC::HS;
1994 case ARMCC::GE: return ARMCC::LE;
1995 case ARMCC::LT: return ARMCC::GT;
1996 case ARMCC::GT: return ARMCC::LT;
1997 case ARMCC::LE: return ARMCC::GE;
2001 /// isRedundantFlagInstr - check whether the first instruction, whose only
2002 /// purpose is to update flags, can be made redundant.
2003 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2004 /// CMPri can be made redundant by SUBri if the operands are the same.
2005 /// This function can be extended later on.
2006 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2007 unsigned SrcReg2, int ImmValue,
2009 if ((CmpI->getOpcode() == ARM::CMPrr ||
2010 CmpI->getOpcode() == ARM::t2CMPrr) &&
2011 (OI->getOpcode() == ARM::SUBrr ||
2012 OI->getOpcode() == ARM::t2SUBrr) &&
2013 ((OI->getOperand(1).getReg() == SrcReg &&
2014 OI->getOperand(2).getReg() == SrcReg2) ||
2015 (OI->getOperand(1).getReg() == SrcReg2 &&
2016 OI->getOperand(2).getReg() == SrcReg)))
2019 if ((CmpI->getOpcode() == ARM::CMPri ||
2020 CmpI->getOpcode() == ARM::t2CMPri) &&
2021 (OI->getOpcode() == ARM::SUBri ||
2022 OI->getOpcode() == ARM::t2SUBri) &&
2023 OI->getOperand(1).getReg() == SrcReg &&
2024 OI->getOperand(2).getImm() == ImmValue)
2029 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2030 /// comparison into one that sets the zero bit in the flags register;
2031 /// Remove a redundant Compare instruction if an earlier instruction can set the
2032 /// flags in the same way as Compare.
2033 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2034 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2035 /// condition code of instructions which use the flags.
2036 bool ARMBaseInstrInfo::
2037 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2038 int CmpMask, int CmpValue,
2039 const MachineRegisterInfo *MRI) const {
2040 // Get the unique definition of SrcReg.
2041 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2042 if (!MI) return false;
2044 // Masked compares sometimes use the same register as the corresponding 'and'.
2045 if (CmpMask != ~0) {
2046 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
2048 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2049 UE = MRI->use_end(); UI != UE; ++UI) {
2050 if (UI->getParent() != CmpInstr->getParent()) continue;
2051 MachineInstr *PotentialAND = &*UI;
2052 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
2057 if (!MI) return false;
2061 // Get ready to iterate backward from CmpInstr.
2062 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2063 B = CmpInstr->getParent()->begin();
2065 // Early exit if CmpInstr is at the beginning of the BB.
2066 if (I == B) return false;
2068 // There are two possible candidates which can be changed to set CPSR:
2069 // One is MI, the other is a SUB instruction.
2070 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2071 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2072 MachineInstr *Sub = NULL;
2074 // MI is not a candidate for CMPrr.
2076 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2077 // Conservatively refuse to convert an instruction which isn't in the same
2078 // BB as the comparison.
2079 // For CMPri, we need to check Sub, thus we can't return here.
2080 if (CmpInstr->getOpcode() == ARM::CMPri ||
2081 CmpInstr->getOpcode() == ARM::t2CMPri)
2087 // Check that CPSR isn't set between the comparison instruction and the one we
2088 // want to change. At the same time, search for Sub.
2089 const TargetRegisterInfo *TRI = &getRegisterInfo();
2091 for (; I != E; --I) {
2092 const MachineInstr &Instr = *I;
2094 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2095 Instr.readsRegister(ARM::CPSR, TRI))
2096 // This instruction modifies or uses CPSR after the one we want to
2097 // change. We can't do this transformation.
2100 // Check whether CmpInstr can be made redundant by the current instruction.
2101 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2107 // The 'and' is below the comparison instruction.
2111 // Return false if no candidates exist.
2115 // The single candidate is called MI.
2118 switch (MI->getOpcode()) {
2152 case ARM::t2EORri: {
2153 // Scan forward for the use of CPSR
2154 // When checking against MI: if it's a conditional code requires
2155 // checking of V bit, then this is not safe to do.
2156 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2157 // If we are done with the basic block, we need to check whether CPSR is
2159 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2161 bool isSafe = false;
2163 E = CmpInstr->getParent()->end();
2164 while (!isSafe && ++I != E) {
2165 const MachineInstr &Instr = *I;
2166 for (unsigned IO = 0, EO = Instr.getNumOperands();
2167 !isSafe && IO != EO; ++IO) {
2168 const MachineOperand &MO = Instr.getOperand(IO);
2169 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2173 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2179 // Condition code is after the operand before CPSR.
2180 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2182 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2183 if (NewCC == ARMCC::AL)
2185 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2186 // on CMP needs to be updated to be based on SUB.
2187 // Push the condition code operands to OperandsToUpdate.
2188 // If it is safe to remove CmpInstr, the condition code of these
2189 // operands will be modified.
2190 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2191 Sub->getOperand(2).getReg() == SrcReg)
2192 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2198 // CPSR can be used multiple times, we should continue.
2211 // If CPSR is not killed nor re-defined, we should check whether it is
2212 // live-out. If it is live-out, do not optimize.
2214 MachineBasicBlock *MBB = CmpInstr->getParent();
2215 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2216 SE = MBB->succ_end(); SI != SE; ++SI)
2217 if ((*SI)->isLiveIn(ARM::CPSR))
2221 // Toggle the optional operand to CPSR.
2222 MI->getOperand(5).setReg(ARM::CPSR);
2223 MI->getOperand(5).setIsDef(true);
2224 CmpInstr->eraseFromParent();
2226 // Modify the condition code of operands in OperandsToUpdate.
2227 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2228 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2229 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2230 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2238 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2239 MachineInstr *DefMI, unsigned Reg,
2240 MachineRegisterInfo *MRI) const {
2241 // Fold large immediates into add, sub, or, xor.
2242 unsigned DefOpc = DefMI->getOpcode();
2243 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2245 if (!DefMI->getOperand(1).isImm())
2246 // Could be t2MOVi32imm <ga:xx>
2249 if (!MRI->hasOneNonDBGUse(Reg))
2252 const MCInstrDesc &DefMCID = DefMI->getDesc();
2253 if (DefMCID.hasOptionalDef()) {
2254 unsigned NumOps = DefMCID.getNumOperands();
2255 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2256 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2257 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2262 const MCInstrDesc &UseMCID = UseMI->getDesc();
2263 if (UseMCID.hasOptionalDef()) {
2264 unsigned NumOps = UseMCID.getNumOperands();
2265 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2266 // If the instruction sets the flag, do not attempt this optimization
2267 // since it may change the semantics of the code.
2271 unsigned UseOpc = UseMI->getOpcode();
2272 unsigned NewUseOpc = 0;
2273 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2274 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2275 bool Commute = false;
2277 default: return false;
2285 case ARM::t2EORrr: {
2286 Commute = UseMI->getOperand(2).getReg() != Reg;
2293 NewUseOpc = ARM::SUBri;
2299 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2301 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2302 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2305 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2306 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2307 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2311 case ARM::t2SUBrr: {
2315 NewUseOpc = ARM::t2SUBri;
2320 case ARM::t2EORrr: {
2321 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2323 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2324 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2327 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2328 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2329 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2337 unsigned OpIdx = Commute ? 2 : 1;
2338 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2339 bool isKill = UseMI->getOperand(OpIdx).isKill();
2340 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2341 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2342 UseMI, UseMI->getDebugLoc(),
2343 get(NewUseOpc), NewReg)
2344 .addReg(Reg1, getKillRegState(isKill))
2345 .addImm(SOImmValV1)));
2346 UseMI->setDesc(get(NewUseOpc));
2347 UseMI->getOperand(1).setReg(NewReg);
2348 UseMI->getOperand(1).setIsKill();
2349 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2350 DefMI->eraseFromParent();
2355 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2356 const MachineInstr *MI) const {
2357 if (!ItinData || ItinData->isEmpty())
2360 const MCInstrDesc &Desc = MI->getDesc();
2361 unsigned Class = Desc.getSchedClass();
2362 int ItinUOps = ItinData->getNumMicroOps(Class);
2366 unsigned Opc = MI->getOpcode();
2369 llvm_unreachable("Unexpected multi-uops instruction!");
2374 // The number of uOps for load / store multiple are determined by the number
2377 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2378 // same cycle. The scheduling for the first load / store must be done
2379 // separately by assuming the address is not 64-bit aligned.
2381 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2382 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2383 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2385 case ARM::VLDMDIA_UPD:
2386 case ARM::VLDMDDB_UPD:
2388 case ARM::VLDMSIA_UPD:
2389 case ARM::VLDMSDB_UPD:
2391 case ARM::VSTMDIA_UPD:
2392 case ARM::VSTMDDB_UPD:
2394 case ARM::VSTMSIA_UPD:
2395 case ARM::VSTMSDB_UPD: {
2396 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2397 return (NumRegs / 2) + (NumRegs % 2) + 1;
2400 case ARM::LDMIA_RET:
2405 case ARM::LDMIA_UPD:
2406 case ARM::LDMDA_UPD:
2407 case ARM::LDMDB_UPD:
2408 case ARM::LDMIB_UPD:
2413 case ARM::STMIA_UPD:
2414 case ARM::STMDA_UPD:
2415 case ARM::STMDB_UPD:
2416 case ARM::STMIB_UPD:
2418 case ARM::tLDMIA_UPD:
2419 case ARM::tSTMIA_UPD:
2423 case ARM::t2LDMIA_RET:
2426 case ARM::t2LDMIA_UPD:
2427 case ARM::t2LDMDB_UPD:
2430 case ARM::t2STMIA_UPD:
2431 case ARM::t2STMDB_UPD: {
2432 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2433 if (Subtarget.isCortexA8()) {
2436 // 4 registers would be issued: 2, 2.
2437 // 5 registers would be issued: 2, 2, 1.
2438 int A8UOps = (NumRegs / 2);
2442 } else if (Subtarget.isCortexA9()) {
2443 int A9UOps = (NumRegs / 2);
2444 // If there are odd number of registers or if it's not 64-bit aligned,
2445 // then it takes an extra AGU (Address Generation Unit) cycle.
2446 if ((NumRegs % 2) ||
2447 !MI->hasOneMemOperand() ||
2448 (*MI->memoperands_begin())->getAlignment() < 8)
2452 // Assume the worst.
2460 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2461 const MCInstrDesc &DefMCID,
2463 unsigned DefIdx, unsigned DefAlign) const {
2464 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2466 // Def is the address writeback.
2467 return ItinData->getOperandCycle(DefClass, DefIdx);
2470 if (Subtarget.isCortexA8()) {
2471 // (regno / 2) + (regno % 2) + 1
2472 DefCycle = RegNo / 2 + 1;
2475 } else if (Subtarget.isCortexA9()) {
2477 bool isSLoad = false;
2479 switch (DefMCID.getOpcode()) {
2482 case ARM::VLDMSIA_UPD:
2483 case ARM::VLDMSDB_UPD:
2488 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2489 // then it takes an extra cycle.
2490 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2493 // Assume the worst.
2494 DefCycle = RegNo + 2;
2501 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2502 const MCInstrDesc &DefMCID,
2504 unsigned DefIdx, unsigned DefAlign) const {
2505 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2507 // Def is the address writeback.
2508 return ItinData->getOperandCycle(DefClass, DefIdx);
2511 if (Subtarget.isCortexA8()) {
2512 // 4 registers would be issued: 1, 2, 1.
2513 // 5 registers would be issued: 1, 2, 2.
2514 DefCycle = RegNo / 2;
2517 // Result latency is issue cycle + 2: E2.
2519 } else if (Subtarget.isCortexA9()) {
2520 DefCycle = (RegNo / 2);
2521 // If there are odd number of registers or if it's not 64-bit aligned,
2522 // then it takes an extra AGU (Address Generation Unit) cycle.
2523 if ((RegNo % 2) || DefAlign < 8)
2525 // Result latency is AGU cycles + 2.
2528 // Assume the worst.
2529 DefCycle = RegNo + 2;
2536 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2537 const MCInstrDesc &UseMCID,
2539 unsigned UseIdx, unsigned UseAlign) const {
2540 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2542 return ItinData->getOperandCycle(UseClass, UseIdx);
2545 if (Subtarget.isCortexA8()) {
2546 // (regno / 2) + (regno % 2) + 1
2547 UseCycle = RegNo / 2 + 1;
2550 } else if (Subtarget.isCortexA9()) {
2552 bool isSStore = false;
2554 switch (UseMCID.getOpcode()) {
2557 case ARM::VSTMSIA_UPD:
2558 case ARM::VSTMSDB_UPD:
2563 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2564 // then it takes an extra cycle.
2565 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2568 // Assume the worst.
2569 UseCycle = RegNo + 2;
2576 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2577 const MCInstrDesc &UseMCID,
2579 unsigned UseIdx, unsigned UseAlign) const {
2580 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2582 return ItinData->getOperandCycle(UseClass, UseIdx);
2585 if (Subtarget.isCortexA8()) {
2586 UseCycle = RegNo / 2;
2591 } else if (Subtarget.isCortexA9()) {
2592 UseCycle = (RegNo / 2);
2593 // If there are odd number of registers or if it's not 64-bit aligned,
2594 // then it takes an extra AGU (Address Generation Unit) cycle.
2595 if ((RegNo % 2) || UseAlign < 8)
2598 // Assume the worst.
2605 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2606 const MCInstrDesc &DefMCID,
2607 unsigned DefIdx, unsigned DefAlign,
2608 const MCInstrDesc &UseMCID,
2609 unsigned UseIdx, unsigned UseAlign) const {
2610 unsigned DefClass = DefMCID.getSchedClass();
2611 unsigned UseClass = UseMCID.getSchedClass();
2613 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2614 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2616 // This may be a def / use of a variable_ops instruction, the operand
2617 // latency might be determinable dynamically. Let the target try to
2620 bool LdmBypass = false;
2621 switch (DefMCID.getOpcode()) {
2623 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2627 case ARM::VLDMDIA_UPD:
2628 case ARM::VLDMDDB_UPD:
2630 case ARM::VLDMSIA_UPD:
2631 case ARM::VLDMSDB_UPD:
2632 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2635 case ARM::LDMIA_RET:
2640 case ARM::LDMIA_UPD:
2641 case ARM::LDMDA_UPD:
2642 case ARM::LDMDB_UPD:
2643 case ARM::LDMIB_UPD:
2645 case ARM::tLDMIA_UPD:
2647 case ARM::t2LDMIA_RET:
2650 case ARM::t2LDMIA_UPD:
2651 case ARM::t2LDMDB_UPD:
2653 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2658 // We can't seem to determine the result latency of the def, assume it's 2.
2662 switch (UseMCID.getOpcode()) {
2664 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2668 case ARM::VSTMDIA_UPD:
2669 case ARM::VSTMDDB_UPD:
2671 case ARM::VSTMSIA_UPD:
2672 case ARM::VSTMSDB_UPD:
2673 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2680 case ARM::STMIA_UPD:
2681 case ARM::STMDA_UPD:
2682 case ARM::STMDB_UPD:
2683 case ARM::STMIB_UPD:
2684 case ARM::tSTMIA_UPD:
2689 case ARM::t2STMIA_UPD:
2690 case ARM::t2STMDB_UPD:
2691 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2696 // Assume it's read in the first stage.
2699 UseCycle = DefCycle - UseCycle + 1;
2702 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2703 // first def operand.
2704 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2707 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2708 UseClass, UseIdx)) {
2716 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2717 const MachineInstr *MI, unsigned Reg,
2718 unsigned &DefIdx, unsigned &Dist) {
2721 MachineBasicBlock::const_iterator I = MI; ++I;
2722 MachineBasicBlock::const_instr_iterator II =
2723 llvm::prior(I.getInstrIterator());
2724 assert(II->isInsideBundle() && "Empty bundle?");
2727 while (II->isInsideBundle()) {
2728 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2735 assert(Idx != -1 && "Cannot find bundled definition!");
2740 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2741 const MachineInstr *MI, unsigned Reg,
2742 unsigned &UseIdx, unsigned &Dist) {
2745 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2746 assert(II->isInsideBundle() && "Empty bundle?");
2747 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2749 // FIXME: This doesn't properly handle multiple uses.
2751 while (II != E && II->isInsideBundle()) {
2752 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2755 if (II->getOpcode() != ARM::t2IT)
2769 /// Return the number of cycles to add to (or subtract from) the static
2770 /// itinerary based on the def opcode and alignment. The caller will ensure that
2771 /// adjusted latency is at least one cycle.
2772 static int adjustDefLatency(const ARMSubtarget &Subtarget,
2773 const MachineInstr *DefMI,
2774 const MCInstrDesc *DefMCID, unsigned DefAlign) {
2776 if (Subtarget.isCortexA8() || Subtarget.isCortexA9()) {
2777 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2778 // variants are one cycle cheaper.
2779 switch (DefMCID->getOpcode()) {
2783 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2784 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2786 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2793 case ARM::t2LDRSHs: {
2794 // Thumb2 mode: lsl only.
2795 unsigned ShAmt = DefMI->getOperand(3).getImm();
2796 if (ShAmt == 0 || ShAmt == 2)
2803 if (DefAlign < 8 && Subtarget.isCortexA9()) {
2804 switch (DefMCID->getOpcode()) {
2810 case ARM::VLD1q8wb_fixed:
2811 case ARM::VLD1q16wb_fixed:
2812 case ARM::VLD1q32wb_fixed:
2813 case ARM::VLD1q64wb_fixed:
2814 case ARM::VLD1q8wb_register:
2815 case ARM::VLD1q16wb_register:
2816 case ARM::VLD1q32wb_register:
2817 case ARM::VLD1q64wb_register:
2824 case ARM::VLD2d8wb_fixed:
2825 case ARM::VLD2d16wb_fixed:
2826 case ARM::VLD2d32wb_fixed:
2827 case ARM::VLD2q8wb_fixed:
2828 case ARM::VLD2q16wb_fixed:
2829 case ARM::VLD2q32wb_fixed:
2830 case ARM::VLD2d8wb_register:
2831 case ARM::VLD2d16wb_register:
2832 case ARM::VLD2d32wb_register:
2833 case ARM::VLD2q8wb_register:
2834 case ARM::VLD2q16wb_register:
2835 case ARM::VLD2q32wb_register:
2840 case ARM::VLD3d8_UPD:
2841 case ARM::VLD3d16_UPD:
2842 case ARM::VLD3d32_UPD:
2843 case ARM::VLD1d64Twb_fixed:
2844 case ARM::VLD1d64Twb_register:
2845 case ARM::VLD3q8_UPD:
2846 case ARM::VLD3q16_UPD:
2847 case ARM::VLD3q32_UPD:
2852 case ARM::VLD4d8_UPD:
2853 case ARM::VLD4d16_UPD:
2854 case ARM::VLD4d32_UPD:
2855 case ARM::VLD1d64Qwb_fixed:
2856 case ARM::VLD1d64Qwb_register:
2857 case ARM::VLD4q8_UPD:
2858 case ARM::VLD4q16_UPD:
2859 case ARM::VLD4q32_UPD:
2860 case ARM::VLD1DUPq8:
2861 case ARM::VLD1DUPq16:
2862 case ARM::VLD1DUPq32:
2863 case ARM::VLD1DUPq8wb_fixed:
2864 case ARM::VLD1DUPq16wb_fixed:
2865 case ARM::VLD1DUPq32wb_fixed:
2866 case ARM::VLD1DUPq8wb_register:
2867 case ARM::VLD1DUPq16wb_register:
2868 case ARM::VLD1DUPq32wb_register:
2869 case ARM::VLD2DUPd8:
2870 case ARM::VLD2DUPd16:
2871 case ARM::VLD2DUPd32:
2872 case ARM::VLD2DUPd8wb_fixed:
2873 case ARM::VLD2DUPd16wb_fixed:
2874 case ARM::VLD2DUPd32wb_fixed:
2875 case ARM::VLD2DUPd8wb_register:
2876 case ARM::VLD2DUPd16wb_register:
2877 case ARM::VLD2DUPd32wb_register:
2878 case ARM::VLD4DUPd8:
2879 case ARM::VLD4DUPd16:
2880 case ARM::VLD4DUPd32:
2881 case ARM::VLD4DUPd8_UPD:
2882 case ARM::VLD4DUPd16_UPD:
2883 case ARM::VLD4DUPd32_UPD:
2885 case ARM::VLD1LNd16:
2886 case ARM::VLD1LNd32:
2887 case ARM::VLD1LNd8_UPD:
2888 case ARM::VLD1LNd16_UPD:
2889 case ARM::VLD1LNd32_UPD:
2891 case ARM::VLD2LNd16:
2892 case ARM::VLD2LNd32:
2893 case ARM::VLD2LNq16:
2894 case ARM::VLD2LNq32:
2895 case ARM::VLD2LNd8_UPD:
2896 case ARM::VLD2LNd16_UPD:
2897 case ARM::VLD2LNd32_UPD:
2898 case ARM::VLD2LNq16_UPD:
2899 case ARM::VLD2LNq32_UPD:
2901 case ARM::VLD4LNd16:
2902 case ARM::VLD4LNd32:
2903 case ARM::VLD4LNq16:
2904 case ARM::VLD4LNq32:
2905 case ARM::VLD4LNd8_UPD:
2906 case ARM::VLD4LNd16_UPD:
2907 case ARM::VLD4LNd32_UPD:
2908 case ARM::VLD4LNq16_UPD:
2909 case ARM::VLD4LNq32_UPD:
2910 // If the address is not 64-bit aligned, the latencies of these
2911 // instructions increases by one.
2922 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2923 const MachineInstr *DefMI, unsigned DefIdx,
2924 const MachineInstr *UseMI,
2925 unsigned UseIdx) const {
2926 // No operand latency. The caller may fall back to getInstrLatency.
2927 if (!ItinData || ItinData->isEmpty())
2930 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2931 unsigned Reg = DefMO.getReg();
2932 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2933 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2935 unsigned DefAdj = 0;
2936 if (DefMI->isBundle()) {
2937 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2938 DefMCID = &DefMI->getDesc();
2940 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2941 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
2945 unsigned UseAdj = 0;
2946 if (UseMI->isBundle()) {
2948 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2949 Reg, NewUseIdx, UseAdj);
2955 UseMCID = &UseMI->getDesc();
2958 if (Reg == ARM::CPSR) {
2959 if (DefMI->getOpcode() == ARM::FMSTAT) {
2960 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2961 return Subtarget.isCortexA9() ? 1 : 20;
2964 // CPSR set and branch can be paired in the same cycle.
2965 if (UseMI->isBranch())
2968 // Otherwise it takes the instruction latency (generally one).
2969 unsigned Latency = getInstrLatency(ItinData, DefMI);
2971 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2972 // its uses. Instructions which are otherwise scheduled between them may
2973 // incur a code size penalty (not able to use the CPSR setting 16-bit
2975 if (Latency > 0 && Subtarget.isThumb2()) {
2976 const MachineFunction *MF = DefMI->getParent()->getParent();
2977 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2983 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
2986 unsigned DefAlign = DefMI->hasOneMemOperand()
2987 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2988 unsigned UseAlign = UseMI->hasOneMemOperand()
2989 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2991 // Get the itinerary's latency if possible, and handle variable_ops.
2992 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2993 *UseMCID, UseIdx, UseAlign);
2994 // Unable to find operand latency. The caller may resort to getInstrLatency.
2998 // Adjust for IT block position.
2999 int Adj = DefAdj + UseAdj;
3001 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3002 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3003 if (Adj >= 0 || (int)Latency > -Adj) {
3004 return Latency + Adj;
3006 // Return the itinerary latency, which may be zero but not less than zero.
3011 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3012 SDNode *DefNode, unsigned DefIdx,
3013 SDNode *UseNode, unsigned UseIdx) const {
3014 if (!DefNode->isMachineOpcode())
3017 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3019 if (isZeroCost(DefMCID.Opcode))
3022 if (!ItinData || ItinData->isEmpty())
3023 return DefMCID.mayLoad() ? 3 : 1;
3025 if (!UseNode->isMachineOpcode()) {
3026 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3027 if (Subtarget.isCortexA9())
3028 return Latency <= 2 ? 1 : Latency - 1;
3030 return Latency <= 3 ? 1 : Latency - 2;
3033 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3034 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3035 unsigned DefAlign = !DefMN->memoperands_empty()
3036 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3037 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3038 unsigned UseAlign = !UseMN->memoperands_empty()
3039 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3040 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3041 UseMCID, UseIdx, UseAlign);
3044 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
3045 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3046 // variants are one cycle cheaper.
3047 switch (DefMCID.getOpcode()) {
3052 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3053 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3055 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3062 case ARM::t2LDRSHs: {
3063 // Thumb2 mode: lsl only.
3065 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3066 if (ShAmt == 0 || ShAmt == 2)
3073 if (DefAlign < 8 && Subtarget.isCortexA9())
3074 switch (DefMCID.getOpcode()) {
3080 case ARM::VLD1q8wb_register:
3081 case ARM::VLD1q16wb_register:
3082 case ARM::VLD1q32wb_register:
3083 case ARM::VLD1q64wb_register:
3084 case ARM::VLD1q8wb_fixed:
3085 case ARM::VLD1q16wb_fixed:
3086 case ARM::VLD1q32wb_fixed:
3087 case ARM::VLD1q64wb_fixed:
3091 case ARM::VLD2q8Pseudo:
3092 case ARM::VLD2q16Pseudo:
3093 case ARM::VLD2q32Pseudo:
3094 case ARM::VLD2d8wb_fixed:
3095 case ARM::VLD2d16wb_fixed:
3096 case ARM::VLD2d32wb_fixed:
3097 case ARM::VLD2q8PseudoWB_fixed:
3098 case ARM::VLD2q16PseudoWB_fixed:
3099 case ARM::VLD2q32PseudoWB_fixed:
3100 case ARM::VLD2d8wb_register:
3101 case ARM::VLD2d16wb_register:
3102 case ARM::VLD2d32wb_register:
3103 case ARM::VLD2q8PseudoWB_register:
3104 case ARM::VLD2q16PseudoWB_register:
3105 case ARM::VLD2q32PseudoWB_register:
3106 case ARM::VLD3d8Pseudo:
3107 case ARM::VLD3d16Pseudo:
3108 case ARM::VLD3d32Pseudo:
3109 case ARM::VLD1d64TPseudo:
3110 case ARM::VLD3d8Pseudo_UPD:
3111 case ARM::VLD3d16Pseudo_UPD:
3112 case ARM::VLD3d32Pseudo_UPD:
3113 case ARM::VLD3q8Pseudo_UPD:
3114 case ARM::VLD3q16Pseudo_UPD:
3115 case ARM::VLD3q32Pseudo_UPD:
3116 case ARM::VLD3q8oddPseudo:
3117 case ARM::VLD3q16oddPseudo:
3118 case ARM::VLD3q32oddPseudo:
3119 case ARM::VLD3q8oddPseudo_UPD:
3120 case ARM::VLD3q16oddPseudo_UPD:
3121 case ARM::VLD3q32oddPseudo_UPD:
3122 case ARM::VLD4d8Pseudo:
3123 case ARM::VLD4d16Pseudo:
3124 case ARM::VLD4d32Pseudo:
3125 case ARM::VLD1d64QPseudo:
3126 case ARM::VLD4d8Pseudo_UPD:
3127 case ARM::VLD4d16Pseudo_UPD:
3128 case ARM::VLD4d32Pseudo_UPD:
3129 case ARM::VLD4q8Pseudo_UPD:
3130 case ARM::VLD4q16Pseudo_UPD:
3131 case ARM::VLD4q32Pseudo_UPD:
3132 case ARM::VLD4q8oddPseudo:
3133 case ARM::VLD4q16oddPseudo:
3134 case ARM::VLD4q32oddPseudo:
3135 case ARM::VLD4q8oddPseudo_UPD:
3136 case ARM::VLD4q16oddPseudo_UPD:
3137 case ARM::VLD4q32oddPseudo_UPD:
3138 case ARM::VLD1DUPq8:
3139 case ARM::VLD1DUPq16:
3140 case ARM::VLD1DUPq32:
3141 case ARM::VLD1DUPq8wb_fixed:
3142 case ARM::VLD1DUPq16wb_fixed:
3143 case ARM::VLD1DUPq32wb_fixed:
3144 case ARM::VLD1DUPq8wb_register:
3145 case ARM::VLD1DUPq16wb_register:
3146 case ARM::VLD1DUPq32wb_register:
3147 case ARM::VLD2DUPd8:
3148 case ARM::VLD2DUPd16:
3149 case ARM::VLD2DUPd32:
3150 case ARM::VLD2DUPd8wb_fixed:
3151 case ARM::VLD2DUPd16wb_fixed:
3152 case ARM::VLD2DUPd32wb_fixed:
3153 case ARM::VLD2DUPd8wb_register:
3154 case ARM::VLD2DUPd16wb_register:
3155 case ARM::VLD2DUPd32wb_register:
3156 case ARM::VLD4DUPd8Pseudo:
3157 case ARM::VLD4DUPd16Pseudo:
3158 case ARM::VLD4DUPd32Pseudo:
3159 case ARM::VLD4DUPd8Pseudo_UPD:
3160 case ARM::VLD4DUPd16Pseudo_UPD:
3161 case ARM::VLD4DUPd32Pseudo_UPD:
3162 case ARM::VLD1LNq8Pseudo:
3163 case ARM::VLD1LNq16Pseudo:
3164 case ARM::VLD1LNq32Pseudo:
3165 case ARM::VLD1LNq8Pseudo_UPD:
3166 case ARM::VLD1LNq16Pseudo_UPD:
3167 case ARM::VLD1LNq32Pseudo_UPD:
3168 case ARM::VLD2LNd8Pseudo:
3169 case ARM::VLD2LNd16Pseudo:
3170 case ARM::VLD2LNd32Pseudo:
3171 case ARM::VLD2LNq16Pseudo:
3172 case ARM::VLD2LNq32Pseudo:
3173 case ARM::VLD2LNd8Pseudo_UPD:
3174 case ARM::VLD2LNd16Pseudo_UPD:
3175 case ARM::VLD2LNd32Pseudo_UPD:
3176 case ARM::VLD2LNq16Pseudo_UPD:
3177 case ARM::VLD2LNq32Pseudo_UPD:
3178 case ARM::VLD4LNd8Pseudo:
3179 case ARM::VLD4LNd16Pseudo:
3180 case ARM::VLD4LNd32Pseudo:
3181 case ARM::VLD4LNq16Pseudo:
3182 case ARM::VLD4LNq32Pseudo:
3183 case ARM::VLD4LNd8Pseudo_UPD:
3184 case ARM::VLD4LNd16Pseudo_UPD:
3185 case ARM::VLD4LNd32Pseudo_UPD:
3186 case ARM::VLD4LNq16Pseudo_UPD:
3187 case ARM::VLD4LNq32Pseudo_UPD:
3188 // If the address is not 64-bit aligned, the latencies of these
3189 // instructions increases by one.
3198 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
3199 const MachineInstr *DefMI, unsigned DefIdx,
3200 const MachineInstr *DepMI) const {
3201 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
3202 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
3205 // If the second MI is predicated, then there is an implicit use dependency.
3206 return getInstrLatency(ItinData, DefMI);
3209 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3210 const MachineInstr *MI,
3211 unsigned *PredCost) const {
3212 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3213 MI->isRegSequence() || MI->isImplicitDef())
3216 // An instruction scheduler typically runs on unbundled instructions, however
3217 // other passes may query the latency of a bundled instruction.
3218 if (MI->isBundle()) {
3219 unsigned Latency = 0;
3220 MachineBasicBlock::const_instr_iterator I = MI;
3221 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3222 while (++I != E && I->isInsideBundle()) {
3223 if (I->getOpcode() != ARM::t2IT)
3224 Latency += getInstrLatency(ItinData, I, PredCost);
3229 const MCInstrDesc &MCID = MI->getDesc();
3230 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3231 // When predicated, CPSR is an additional source operand for CPSR updating
3232 // instructions, this apparently increases their latencies.
3235 // Be sure to call getStageLatency for an empty itinerary in case it has a
3236 // valid MinLatency property.
3238 return MI->mayLoad() ? 3 : 1;
3240 unsigned Class = MCID.getSchedClass();
3242 // For instructions with variable uops, use uops as latency.
3243 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3244 return getNumMicroOps(ItinData, MI);
3246 // For the common case, fall back on the itinerary's latency.
3247 unsigned Latency = ItinData->getStageLatency(Class);
3249 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3250 unsigned DefAlign = MI->hasOneMemOperand()
3251 ? (*MI->memoperands_begin())->getAlignment() : 0;
3252 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3253 if (Adj >= 0 || (int)Latency > -Adj) {
3254 return Latency + Adj;
3259 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3260 SDNode *Node) const {
3261 if (!Node->isMachineOpcode())
3264 if (!ItinData || ItinData->isEmpty())
3267 unsigned Opcode = Node->getMachineOpcode();
3270 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3277 bool ARMBaseInstrInfo::
3278 hasHighOperandLatency(const InstrItineraryData *ItinData,
3279 const MachineRegisterInfo *MRI,
3280 const MachineInstr *DefMI, unsigned DefIdx,
3281 const MachineInstr *UseMI, unsigned UseIdx) const {
3282 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3283 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3284 if (Subtarget.isCortexA8() &&
3285 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3286 // CortexA8 VFP instructions are not pipelined.
3289 // Hoist VFP / NEON instructions with 4 or higher latency.
3290 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx,
3293 Latency = getInstrLatency(ItinData, DefMI);
3296 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3297 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3300 bool ARMBaseInstrInfo::
3301 hasLowDefLatency(const InstrItineraryData *ItinData,
3302 const MachineInstr *DefMI, unsigned DefIdx) const {
3303 if (!ItinData || ItinData->isEmpty())
3306 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3307 if (DDomain == ARMII::DomainGeneral) {
3308 unsigned DefClass = DefMI->getDesc().getSchedClass();
3309 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3310 return (DefCycle != -1 && DefCycle <= 2);
3315 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3316 StringRef &ErrInfo) const {
3317 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3318 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3325 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3326 unsigned &AddSubOpc,
3327 bool &NegAcc, bool &HasLane) const {
3328 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3329 if (I == MLxEntryMap.end())
3332 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3333 MulOpc = Entry.MulOpc;
3334 AddSubOpc = Entry.AddSubOpc;
3335 NegAcc = Entry.NegAcc;
3336 HasLane = Entry.HasLane;
3340 //===----------------------------------------------------------------------===//
3341 // Execution domains.
3342 //===----------------------------------------------------------------------===//
3344 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3345 // and some can go down both. The vmov instructions go down the VFP pipeline,
3346 // but they can be changed to vorr equivalents that are executed by the NEON
3349 // We use the following execution domain numbering:
3357 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3359 std::pair<uint16_t, uint16_t>
3360 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3361 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3362 // if they are not predicated.
3363 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3364 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3366 // Cortex-A9 is particularly picky about mixing the two and wants these
3368 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3369 (MI->getOpcode() == ARM::VMOVRS ||
3370 MI->getOpcode() == ARM::VMOVSR))
3371 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3373 // No other instructions can be swizzled, so just determine their domain.
3374 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3376 if (Domain & ARMII::DomainNEON)
3377 return std::make_pair(ExeNEON, 0);
3379 // Certain instructions can go either way on Cortex-A8.
3380 // Treat them as NEON instructions.
3381 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3382 return std::make_pair(ExeNEON, 0);
3384 if (Domain & ARMII::DomainVFP)
3385 return std::make_pair(ExeVFP, 0);
3387 return std::make_pair(ExeGeneric, 0);
3391 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3392 unsigned DstReg, SrcReg, DReg;
3394 MachineInstrBuilder MIB(MI);
3395 const TargetRegisterInfo *TRI = &getRegisterInfo();
3397 switch (MI->getOpcode()) {
3399 llvm_unreachable("cannot handle opcode!");
3402 if (Domain != ExeNEON)
3405 // Zap the predicate operands.
3406 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3407 MI->RemoveOperand(3);
3408 MI->RemoveOperand(2);
3410 // Change to a VORRd which requires two identical use operands.
3411 MI->setDesc(get(ARM::VORRd));
3413 // Add the extra source operand and new predicates.
3414 // This will go before any implicit ops.
3415 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));
3418 if (Domain != ExeNEON)
3420 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3422 DstReg = MI->getOperand(0).getReg();
3423 SrcReg = MI->getOperand(1).getReg();
3425 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_0, &ARM::DPRRegClass);
3427 if (DReg == ARM::NoRegister) {
3428 DReg = TRI->getMatchingSuperReg(SrcReg, ARM::ssub_1, &ARM::DPRRegClass);
3430 assert(DReg && "S-register with no D super-register?");
3433 MI->RemoveOperand(3);
3434 MI->RemoveOperand(2);
3435 MI->RemoveOperand(1);
3437 MI->setDesc(get(ARM::VGETLNi32));
3441 MIB->getOperand(1).setIsUndef();
3442 MIB.addReg(SrcReg, RegState::Implicit);
3444 AddDefaultPred(MIB);
3447 if (Domain != ExeNEON)
3449 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3451 DstReg = MI->getOperand(0).getReg();
3452 SrcReg = MI->getOperand(1).getReg();
3453 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_0, &ARM::DPRRegClass);
3455 if (DReg == ARM::NoRegister) {
3456 DReg = TRI->getMatchingSuperReg(DstReg, ARM::ssub_1, &ARM::DPRRegClass);
3458 assert(DReg && "S-register with no D super-register?");
3460 isKill = MI->getOperand(0).isKill();
3462 MI->RemoveOperand(3);
3463 MI->RemoveOperand(2);
3464 MI->RemoveOperand(1);
3465 MI->RemoveOperand(0);
3467 MI->setDesc(get(ARM::VSETLNi32));
3468 MIB.addReg(DReg, RegState::Define);
3469 MIB.addReg(DReg, RegState::Undef);
3474 MIB->addRegisterKilled(DstReg, TRI, true);
3475 MIB->addRegisterDefined(DstReg, TRI);
3477 AddDefaultPred(MIB);
3483 bool ARMBaseInstrInfo::hasNOP() const {
3484 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;