1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/ErrorHandling.h"
32 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
33 cl::desc("Enable ARM 2-addr to 3-addr conv"));
35 ARMBaseInstrInfo::ARMBaseInstrInfo()
36 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
40 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
41 MachineBasicBlock::iterator &MBBI,
42 LiveVariables *LV) const {
43 // FIXME: Thumb2 support.
48 MachineInstr *MI = MBBI;
49 MachineFunction &MF = *MI->getParent()->getParent();
50 unsigned TSFlags = MI->getDesc().TSFlags;
52 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
54 case ARMII::IndexModePre:
57 case ARMII::IndexModePost:
61 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
63 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
67 MachineInstr *UpdateMI = NULL;
68 MachineInstr *MemMI = NULL;
69 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
70 const TargetInstrDesc &TID = MI->getDesc();
71 unsigned NumOps = TID.getNumOperands();
72 bool isLoad = !TID.mayStore();
73 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
74 const MachineOperand &Base = MI->getOperand(2);
75 const MachineOperand &Offset = MI->getOperand(NumOps-3);
76 unsigned WBReg = WB.getReg();
77 unsigned BaseReg = Base.getReg();
78 unsigned OffReg = Offset.getReg();
79 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
80 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
83 assert(false && "Unknown indexed op!");
85 case ARMII::AddrMode2: {
86 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
87 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
89 if (ARM_AM::getSOImmVal(Amt) == -1)
90 // Can't encode it in a so_imm operand. This transformation will
91 // add more than 1 instruction. Abandon!
93 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
94 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
95 .addReg(BaseReg).addImm(Amt)
96 .addImm(Pred).addReg(0).addReg(0);
97 } else if (Amt != 0) {
98 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
99 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
100 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
101 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
102 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
103 .addImm(Pred).addReg(0).addReg(0);
105 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
106 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
107 .addReg(BaseReg).addReg(OffReg)
108 .addImm(Pred).addReg(0).addReg(0);
111 case ARMII::AddrMode3 : {
112 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
113 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
115 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
116 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
117 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
118 .addReg(BaseReg).addImm(Amt)
119 .addImm(Pred).addReg(0).addReg(0);
121 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
122 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
123 .addReg(BaseReg).addReg(OffReg)
124 .addImm(Pred).addReg(0).addReg(0);
129 std::vector<MachineInstr*> NewMIs;
132 MemMI = BuildMI(MF, MI->getDebugLoc(),
133 get(MemOpc), MI->getOperand(0).getReg())
134 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
136 MemMI = BuildMI(MF, MI->getDebugLoc(),
137 get(MemOpc)).addReg(MI->getOperand(1).getReg())
138 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
139 NewMIs.push_back(MemMI);
140 NewMIs.push_back(UpdateMI);
143 MemMI = BuildMI(MF, MI->getDebugLoc(),
144 get(MemOpc), MI->getOperand(0).getReg())
145 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
147 MemMI = BuildMI(MF, MI->getDebugLoc(),
148 get(MemOpc)).addReg(MI->getOperand(1).getReg())
149 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
151 UpdateMI->getOperand(0).setIsDead();
152 NewMIs.push_back(UpdateMI);
153 NewMIs.push_back(MemMI);
156 // Transfer LiveVariables states, kill / dead info.
158 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
159 MachineOperand &MO = MI->getOperand(i);
160 if (MO.isReg() && MO.getReg() &&
161 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
162 unsigned Reg = MO.getReg();
164 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
166 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
168 LV->addVirtualRegisterDead(Reg, NewMI);
170 if (MO.isUse() && MO.isKill()) {
171 for (unsigned j = 0; j < 2; ++j) {
172 // Look at the two new MI's in reverse order.
173 MachineInstr *NewMI = NewMIs[j];
174 if (!NewMI->readsRegister(Reg))
176 LV->addVirtualRegisterKilled(Reg, NewMI);
177 if (VI.removeKill(MI))
178 VI.Kills.push_back(NewMI);
186 MFI->insert(MBBI, NewMIs[1]);
187 MFI->insert(MBBI, NewMIs[0]);
193 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
194 MachineBasicBlock *&FBB,
195 SmallVectorImpl<MachineOperand> &Cond,
196 bool AllowModify) const {
197 // If the block has no terminators, it just falls into the block after it.
198 MachineBasicBlock::iterator I = MBB.end();
199 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
202 // Get the last instruction in the block.
203 MachineInstr *LastInst = I;
205 // If there is only one terminator instruction, process it.
206 unsigned LastOpc = LastInst->getOpcode();
207 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
208 if (isUncondBranchOpcode(LastOpc)) {
209 TBB = LastInst->getOperand(0).getMBB();
212 if (isCondBranchOpcode(LastOpc)) {
213 // Block ends with fall-through condbranch.
214 TBB = LastInst->getOperand(0).getMBB();
215 Cond.push_back(LastInst->getOperand(1));
216 Cond.push_back(LastInst->getOperand(2));
219 return true; // Can't handle indirect branch.
222 // Get the instruction before it if it is a terminator.
223 MachineInstr *SecondLastInst = I;
225 // If there are three terminators, we don't know what sort of block this is.
226 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
229 // If the block ends with a B and a Bcc, handle it.
230 unsigned SecondLastOpc = SecondLastInst->getOpcode();
231 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
232 TBB = SecondLastInst->getOperand(0).getMBB();
233 Cond.push_back(SecondLastInst->getOperand(1));
234 Cond.push_back(SecondLastInst->getOperand(2));
235 FBB = LastInst->getOperand(0).getMBB();
239 // If the block ends with two unconditional branches, handle it. The second
240 // one is not executed, so remove it.
241 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
242 TBB = SecondLastInst->getOperand(0).getMBB();
245 I->eraseFromParent();
249 // ...likewise if it ends with a branch table followed by an unconditional
250 // branch. The branch folder can create these, and we must get rid of them for
251 // correctness of Thumb constant islands.
252 if (isJumpTableBranchOpcode(SecondLastOpc) &&
253 isUncondBranchOpcode(LastOpc)) {
256 I->eraseFromParent();
260 // Otherwise, can't handle this.
265 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
266 MachineBasicBlock::iterator I = MBB.end();
267 if (I == MBB.begin()) return 0;
269 if (!isUncondBranchOpcode(I->getOpcode()) &&
270 !isCondBranchOpcode(I->getOpcode()))
273 // Remove the branch.
274 I->eraseFromParent();
278 if (I == MBB.begin()) return 1;
280 if (!isCondBranchOpcode(I->getOpcode()))
283 // Remove the branch.
284 I->eraseFromParent();
289 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
290 MachineBasicBlock *FBB,
291 const SmallVectorImpl<MachineOperand> &Cond) const {
292 // FIXME this should probably have a DebugLoc argument
293 DebugLoc dl = DebugLoc::getUnknownLoc();
295 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
296 int BOpc = !AFI->isThumbFunction()
297 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
298 int BccOpc = !AFI->isThumbFunction()
299 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
301 // Shouldn't be a fall through.
302 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
303 assert((Cond.size() == 2 || Cond.size() == 0) &&
304 "ARM branch conditions have two components!");
307 if (Cond.empty()) // Unconditional branch?
308 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
310 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
311 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
315 // Two-way conditional branch.
316 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
317 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
318 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
322 bool ARMBaseInstrInfo::
323 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
324 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
325 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
329 bool ARMBaseInstrInfo::
330 PredicateInstruction(MachineInstr *MI,
331 const SmallVectorImpl<MachineOperand> &Pred) const {
332 unsigned Opc = MI->getOpcode();
333 if (isUncondBranchOpcode(Opc)) {
334 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
335 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
336 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
340 int PIdx = MI->findFirstPredOperandIdx();
342 MachineOperand &PMO = MI->getOperand(PIdx);
343 PMO.setImm(Pred[0].getImm());
344 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
350 bool ARMBaseInstrInfo::
351 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
352 const SmallVectorImpl<MachineOperand> &Pred2) const {
353 if (Pred1.size() > 2 || Pred2.size() > 2)
356 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
357 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
367 return CC2 == ARMCC::HI;
369 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
371 return CC2 == ARMCC::GT;
373 return CC2 == ARMCC::LT;
377 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
378 std::vector<MachineOperand> &Pred) const {
379 // FIXME: This confuses implicit_def with optional CPSR def.
380 const TargetInstrDesc &TID = MI->getDesc();
381 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
385 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
386 const MachineOperand &MO = MI->getOperand(i);
387 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
397 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
398 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
399 unsigned JTI) DISABLE_INLINE;
400 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
402 return JT[JTI].MBBs.size();
405 /// GetInstSize - Return the size of the specified MachineInstr.
407 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
408 const MachineBasicBlock &MBB = *MI->getParent();
409 const MachineFunction *MF = MBB.getParent();
410 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
412 // Basic size info comes from the TSFlags field.
413 const TargetInstrDesc &TID = MI->getDesc();
414 unsigned TSFlags = TID.TSFlags;
416 unsigned Opc = MI->getOpcode();
417 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
419 // If this machine instr is an inline asm, measure it.
420 if (MI->getOpcode() == ARM::INLINEASM)
421 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
426 llvm_unreachable("Unknown or unset size field for instr!");
427 case TargetInstrInfo::IMPLICIT_DEF:
428 case TargetInstrInfo::KILL:
429 case TargetInstrInfo::DBG_LABEL:
430 case TargetInstrInfo::EH_LABEL:
435 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
436 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
437 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
438 case ARMII::SizeSpecial: {
440 case ARM::CONSTPOOL_ENTRY:
441 // If this machine instr is a constant pool entry, its size is recorded as
443 return MI->getOperand(2).getImm();
444 case ARM::Int_eh_sjlj_setjmp:
446 case ARM::t2Int_eh_sjlj_setjmp:
455 // These are jumptable branches, i.e. a branch followed by an inlined
456 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
457 // entry is one byte; TBH two byte each.
458 unsigned EntrySize = (Opc == ARM::t2TBB)
459 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
460 unsigned NumOps = TID.getNumOperands();
461 MachineOperand JTOP =
462 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
463 unsigned JTI = JTOP.getIndex();
464 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
465 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
466 assert(JTI < JT.size());
467 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
468 // 4 aligned. The assembler / linker may add 2 byte padding just before
469 // the JT entries. The size does not include this padding; the
470 // constant islands pass does separate bookkeeping for it.
471 // FIXME: If we know the size of the function is less than (1 << 16) *2
472 // bytes, we can use 16-bit entries instead. Then there won't be an
474 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
475 unsigned NumEntries = getNumJTEntries(JT, JTI);
476 if (Opc == ARM::t2TBB && (NumEntries & 1))
477 // Make sure the instruction that follows TBB is 2-byte aligned.
478 // FIXME: Constant island pass should insert an "ALIGN" instruction
481 return NumEntries * EntrySize + InstSize;
484 // Otherwise, pseudo-instruction sizes are zero.
489 return 0; // Not reached
492 /// Return true if the instruction is a register to register move and
493 /// leave the source and dest operands in the passed parameters.
496 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
497 unsigned &SrcReg, unsigned &DstReg,
498 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
499 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
501 switch (MI.getOpcode()) {
507 SrcReg = MI.getOperand(1).getReg();
508 DstReg = MI.getOperand(0).getReg();
513 case ARM::tMOVgpr2tgpr:
514 case ARM::tMOVtgpr2gpr:
515 case ARM::tMOVgpr2gpr:
517 assert(MI.getDesc().getNumOperands() >= 2 &&
518 MI.getOperand(0).isReg() &&
519 MI.getOperand(1).isReg() &&
520 "Invalid ARM MOV instruction");
521 SrcReg = MI.getOperand(1).getReg();
522 DstReg = MI.getOperand(0).getReg();
531 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
532 int &FrameIndex) const {
533 switch (MI->getOpcode()) {
536 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
537 if (MI->getOperand(1).isFI() &&
538 MI->getOperand(2).isReg() &&
539 MI->getOperand(3).isImm() &&
540 MI->getOperand(2).getReg() == 0 &&
541 MI->getOperand(3).getImm() == 0) {
542 FrameIndex = MI->getOperand(1).getIndex();
543 return MI->getOperand(0).getReg();
548 if (MI->getOperand(1).isFI() &&
549 MI->getOperand(2).isImm() &&
550 MI->getOperand(2).getImm() == 0) {
551 FrameIndex = MI->getOperand(1).getIndex();
552 return MI->getOperand(0).getReg();
557 if (MI->getOperand(1).isFI() &&
558 MI->getOperand(2).isImm() &&
559 MI->getOperand(2).getImm() == 0) {
560 FrameIndex = MI->getOperand(1).getIndex();
561 return MI->getOperand(0).getReg();
570 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
571 int &FrameIndex) const {
572 switch (MI->getOpcode()) {
575 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
576 if (MI->getOperand(1).isFI() &&
577 MI->getOperand(2).isReg() &&
578 MI->getOperand(3).isImm() &&
579 MI->getOperand(2).getReg() == 0 &&
580 MI->getOperand(3).getImm() == 0) {
581 FrameIndex = MI->getOperand(1).getIndex();
582 return MI->getOperand(0).getReg();
587 if (MI->getOperand(1).isFI() &&
588 MI->getOperand(2).isImm() &&
589 MI->getOperand(2).getImm() == 0) {
590 FrameIndex = MI->getOperand(1).getIndex();
591 return MI->getOperand(0).getReg();
596 if (MI->getOperand(1).isFI() &&
597 MI->getOperand(2).isImm() &&
598 MI->getOperand(2).getImm() == 0) {
599 FrameIndex = MI->getOperand(1).getIndex();
600 return MI->getOperand(0).getReg();
609 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
610 MachineBasicBlock::iterator I,
611 unsigned DestReg, unsigned SrcReg,
612 const TargetRegisterClass *DestRC,
613 const TargetRegisterClass *SrcRC) const {
614 DebugLoc DL = DebugLoc::getUnknownLoc();
615 if (I != MBB.end()) DL = I->getDebugLoc();
617 if (DestRC != SrcRC) {
618 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
619 // Allow QPR / QPR_VFP2 cross-class copies
620 if (DestRC == ARM::DPRRegisterClass) {
621 if (SrcRC == ARM::DPR_VFP2RegisterClass ||
622 SrcRC == ARM::DPR_8RegisterClass) {
625 } else if (DestRC == ARM::DPR_VFP2RegisterClass) {
626 if (SrcRC == ARM::DPRRegisterClass ||
627 SrcRC == ARM::DPR_8RegisterClass) {
630 } else if (DestRC == ARM::DPR_8RegisterClass) {
631 if (SrcRC == ARM::DPRRegisterClass ||
632 SrcRC == ARM::DPR_VFP2RegisterClass) {
635 } else if ((DestRC == ARM::QPRRegisterClass &&
636 SrcRC == ARM::QPR_VFP2RegisterClass) ||
637 (DestRC == ARM::QPR_VFP2RegisterClass &&
638 SrcRC == ARM::QPRRegisterClass)) {
643 if (DestRC == ARM::GPRRegisterClass) {
644 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
645 DestReg).addReg(SrcReg)));
646 } else if (DestRC == ARM::SPRRegisterClass) {
647 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
649 } else if ((DestRC == ARM::DPRRegisterClass) ||
650 (DestRC == ARM::DPR_VFP2RegisterClass) ||
651 (DestRC == ARM::DPR_8RegisterClass)) {
652 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
654 } else if (DestRC == ARM::QPRRegisterClass ||
655 DestRC == ARM::QPR_VFP2RegisterClass) {
656 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
664 void ARMBaseInstrInfo::
665 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
666 unsigned SrcReg, bool isKill, int FI,
667 const TargetRegisterClass *RC) const {
668 DebugLoc DL = DebugLoc::getUnknownLoc();
669 if (I != MBB.end()) DL = I->getDebugLoc();
670 MachineFunction &MF = *MBB.getParent();
671 MachineFrameInfo &MFI = *MF.getFrameInfo();
673 MachineMemOperand *MMO =
674 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
675 MachineMemOperand::MOStore, 0,
676 MFI.getObjectSize(FI),
677 MFI.getObjectAlignment(FI));
679 if (RC == ARM::GPRRegisterClass) {
680 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
681 .addReg(SrcReg, getKillRegState(isKill))
682 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
683 } else if (RC == ARM::DPRRegisterClass ||
684 RC == ARM::DPR_VFP2RegisterClass ||
685 RC == ARM::DPR_8RegisterClass) {
686 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
687 .addReg(SrcReg, getKillRegState(isKill))
688 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
689 } else if (RC == ARM::SPRRegisterClass) {
690 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
691 .addReg(SrcReg, getKillRegState(isKill))
692 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
694 assert((RC == ARM::QPRRegisterClass ||
695 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
696 // FIXME: Neon instructions should support predicates
697 BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
698 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
702 void ARMBaseInstrInfo::
703 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
704 unsigned DestReg, int FI,
705 const TargetRegisterClass *RC) const {
706 DebugLoc DL = DebugLoc::getUnknownLoc();
707 if (I != MBB.end()) DL = I->getDebugLoc();
708 MachineFunction &MF = *MBB.getParent();
709 MachineFrameInfo &MFI = *MF.getFrameInfo();
711 MachineMemOperand *MMO =
712 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
713 MachineMemOperand::MOLoad, 0,
714 MFI.getObjectSize(FI),
715 MFI.getObjectAlignment(FI));
717 if (RC == ARM::GPRRegisterClass) {
718 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
719 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
720 } else if (RC == ARM::DPRRegisterClass ||
721 RC == ARM::DPR_VFP2RegisterClass ||
722 RC == ARM::DPR_8RegisterClass) {
723 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
724 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
725 } else if (RC == ARM::SPRRegisterClass) {
726 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
727 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
729 assert((RC == ARM::QPRRegisterClass ||
730 RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
731 // FIXME: Neon instructions should support predicates
732 BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
737 MachineInstr *ARMBaseInstrInfo::
738 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
739 const SmallVectorImpl<unsigned> &Ops, int FI) const {
740 if (Ops.size() != 1) return NULL;
742 unsigned OpNum = Ops[0];
743 unsigned Opc = MI->getOpcode();
744 MachineInstr *NewMI = NULL;
745 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
746 // If it is updating CPSR, then it cannot be folded.
747 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
749 unsigned Pred = MI->getOperand(2).getImm();
750 unsigned PredReg = MI->getOperand(3).getReg();
751 if (OpNum == 0) { // move -> store
752 unsigned SrcReg = MI->getOperand(1).getReg();
753 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
754 bool isKill = MI->getOperand(1).isKill();
755 bool isUndef = MI->getOperand(1).isUndef();
756 if (Opc == ARM::MOVr)
757 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
759 getKillRegState(isKill) | getUndefRegState(isUndef),
761 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
763 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
765 getKillRegState(isKill) | getUndefRegState(isUndef),
767 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
768 } else { // move -> load
769 unsigned DstReg = MI->getOperand(0).getReg();
770 unsigned DstSubReg = MI->getOperand(0).getSubReg();
771 bool isDead = MI->getOperand(0).isDead();
772 bool isUndef = MI->getOperand(0).isUndef();
773 if (Opc == ARM::MOVr)
774 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
777 getDeadRegState(isDead) |
778 getUndefRegState(isUndef), DstSubReg)
779 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
781 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
784 getDeadRegState(isDead) |
785 getUndefRegState(isUndef), DstSubReg)
786 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
788 } else if (Opc == ARM::tMOVgpr2gpr ||
789 Opc == ARM::tMOVtgpr2gpr ||
790 Opc == ARM::tMOVgpr2tgpr) {
791 if (OpNum == 0) { // move -> store
792 unsigned SrcReg = MI->getOperand(1).getReg();
793 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
794 bool isKill = MI->getOperand(1).isKill();
795 bool isUndef = MI->getOperand(1).isUndef();
796 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
798 getKillRegState(isKill) | getUndefRegState(isUndef),
800 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
801 } else { // move -> load
802 unsigned DstReg = MI->getOperand(0).getReg();
803 unsigned DstSubReg = MI->getOperand(0).getSubReg();
804 bool isDead = MI->getOperand(0).isDead();
805 bool isUndef = MI->getOperand(0).isUndef();
806 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
809 getDeadRegState(isDead) |
810 getUndefRegState(isUndef),
812 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
814 } else if (Opc == ARM::FCPYS) {
815 unsigned Pred = MI->getOperand(2).getImm();
816 unsigned PredReg = MI->getOperand(3).getReg();
817 if (OpNum == 0) { // move -> store
818 unsigned SrcReg = MI->getOperand(1).getReg();
819 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
820 bool isKill = MI->getOperand(1).isKill();
821 bool isUndef = MI->getOperand(1).isUndef();
822 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
823 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
826 .addImm(0).addImm(Pred).addReg(PredReg);
827 } else { // move -> load
828 unsigned DstReg = MI->getOperand(0).getReg();
829 unsigned DstSubReg = MI->getOperand(0).getSubReg();
830 bool isDead = MI->getOperand(0).isDead();
831 bool isUndef = MI->getOperand(0).isUndef();
832 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
835 getDeadRegState(isDead) |
836 getUndefRegState(isUndef),
838 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
841 else if (Opc == ARM::FCPYD) {
842 unsigned Pred = MI->getOperand(2).getImm();
843 unsigned PredReg = MI->getOperand(3).getReg();
844 if (OpNum == 0) { // move -> store
845 unsigned SrcReg = MI->getOperand(1).getReg();
846 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
847 bool isKill = MI->getOperand(1).isKill();
848 bool isUndef = MI->getOperand(1).isUndef();
849 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
851 getKillRegState(isKill) | getUndefRegState(isUndef),
853 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
854 } else { // move -> load
855 unsigned DstReg = MI->getOperand(0).getReg();
856 unsigned DstSubReg = MI->getOperand(0).getSubReg();
857 bool isDead = MI->getOperand(0).isDead();
858 bool isUndef = MI->getOperand(0).isUndef();
859 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
862 getDeadRegState(isDead) |
863 getUndefRegState(isUndef),
865 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
873 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
875 const SmallVectorImpl<unsigned> &Ops,
876 MachineInstr* LoadMI) const {
882 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
883 const SmallVectorImpl<unsigned> &Ops) const {
884 if (Ops.size() != 1) return false;
886 unsigned Opc = MI->getOpcode();
887 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
888 // If it is updating CPSR, then it cannot be folded.
889 return MI->getOperand(4).getReg() != ARM::CPSR ||
890 MI->getOperand(4).isDead();
891 } else if (Opc == ARM::tMOVgpr2gpr ||
892 Opc == ARM::tMOVtgpr2gpr ||
893 Opc == ARM::tMOVgpr2tgpr) {
895 } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) {
897 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) {
898 return false; // FIXME
904 /// getInstrPredicate - If instruction is predicated, returns its predicate
905 /// condition, otherwise returns AL. It also returns the condition code
906 /// register by reference.
908 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
909 int PIdx = MI->findFirstPredOperandIdx();
915 PredReg = MI->getOperand(PIdx+1).getReg();
916 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
920 int llvm::getMatchingCondBranchOpcode(int Opc) {
923 else if (Opc == ARM::tB)
925 else if (Opc == ARM::t2B)
928 llvm_unreachable("Unknown unconditional branch opcode!");
933 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
934 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
935 unsigned DestReg, unsigned BaseReg, int NumBytes,
936 ARMCC::CondCodes Pred, unsigned PredReg,
937 const ARMBaseInstrInfo &TII) {
938 bool isSub = NumBytes < 0;
939 if (isSub) NumBytes = -NumBytes;
942 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
943 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
944 assert(ThisVal && "Didn't extract field correctly");
946 // We will handle these bits from offset, clear them.
947 NumBytes &= ~ThisVal;
949 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
951 // Build the new ADD / SUB.
952 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
953 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
954 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
955 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
960 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
961 unsigned FrameReg, int &Offset,
962 const ARMBaseInstrInfo &TII) {
963 unsigned Opcode = MI.getOpcode();
964 const TargetInstrDesc &Desc = MI.getDesc();
965 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
968 // Memory operands in inline assembly always use AddrMode2.
969 if (Opcode == ARM::INLINEASM)
970 AddrMode = ARMII::AddrMode2;
972 if (Opcode == ARM::ADDri) {
973 Offset += MI.getOperand(FrameRegIdx+1).getImm();
975 // Turn it into a move.
976 MI.setDesc(TII.get(ARM::MOVr));
977 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
978 MI.RemoveOperand(FrameRegIdx+1);
981 } else if (Offset < 0) {
984 MI.setDesc(TII.get(ARM::SUBri));
987 // Common case: small offset, fits into instruction.
988 if (ARM_AM::getSOImmVal(Offset) != -1) {
989 // Replace the FrameIndex with sp / fp
990 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
991 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
996 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
998 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
999 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1001 // We will handle these bits from offset, clear them.
1002 Offset &= ~ThisImmVal;
1004 // Get the properly encoded SOImmVal field.
1005 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1006 "Bit extraction didn't work?");
1007 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1009 unsigned ImmIdx = 0;
1011 unsigned NumBits = 0;
1014 case ARMII::AddrMode2: {
1015 ImmIdx = FrameRegIdx+2;
1016 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1017 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1022 case ARMII::AddrMode3: {
1023 ImmIdx = FrameRegIdx+2;
1024 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1025 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1030 case ARMII::AddrMode4:
1031 // Can't fold any offset even if it's zero.
1033 case ARMII::AddrMode5: {
1034 ImmIdx = FrameRegIdx+1;
1035 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1036 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1043 llvm_unreachable("Unsupported addressing mode!");
1047 Offset += InstrOffs * Scale;
1048 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1054 // Attempt to fold address comp. if opcode has offset bits
1056 // Common case: small offset, fits into instruction.
1057 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1058 int ImmedOffset = Offset / Scale;
1059 unsigned Mask = (1 << NumBits) - 1;
1060 if ((unsigned)Offset <= Mask * Scale) {
1061 // Replace the FrameIndex with sp
1062 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1064 ImmedOffset |= 1 << NumBits;
1065 ImmOp.ChangeToImmediate(ImmedOffset);
1070 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1071 ImmedOffset = ImmedOffset & Mask;
1073 ImmedOffset |= 1 << NumBits;
1074 ImmOp.ChangeToImmediate(ImmedOffset);
1075 Offset &= ~(Mask*Scale);
1079 Offset = (isSub) ? -Offset : Offset;