1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/PseudoSourceValue.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
40 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
41 cl::desc("Enable ARM 2-addr to 3-addr conv"));
43 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
44 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
49 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
50 MachineBasicBlock::iterator &MBBI,
51 LiveVariables *LV) const {
52 // FIXME: Thumb2 support.
57 MachineInstr *MI = MBBI;
58 MachineFunction &MF = *MI->getParent()->getParent();
59 uint64_t TSFlags = MI->getDesc().TSFlags;
61 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
63 case ARMII::IndexModePre:
66 case ARMII::IndexModePost:
70 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
72 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
76 MachineInstr *UpdateMI = NULL;
77 MachineInstr *MemMI = NULL;
78 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
79 const TargetInstrDesc &TID = MI->getDesc();
80 unsigned NumOps = TID.getNumOperands();
81 bool isLoad = !TID.mayStore();
82 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
83 const MachineOperand &Base = MI->getOperand(2);
84 const MachineOperand &Offset = MI->getOperand(NumOps-3);
85 unsigned WBReg = WB.getReg();
86 unsigned BaseReg = Base.getReg();
87 unsigned OffReg = Offset.getReg();
88 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
89 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
92 assert(false && "Unknown indexed op!");
94 case ARMII::AddrMode2: {
95 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
96 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
98 if (ARM_AM::getSOImmVal(Amt) == -1)
99 // Can't encode it in a so_imm operand. This transformation will
100 // add more than 1 instruction. Abandon!
102 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
103 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
104 .addReg(BaseReg).addImm(Amt)
105 .addImm(Pred).addReg(0).addReg(0);
106 } else if (Amt != 0) {
107 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
108 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
109 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
110 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
111 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
112 .addImm(Pred).addReg(0).addReg(0);
114 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
115 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
116 .addReg(BaseReg).addReg(OffReg)
117 .addImm(Pred).addReg(0).addReg(0);
120 case ARMII::AddrMode3 : {
121 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
122 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
124 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
125 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
126 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
127 .addReg(BaseReg).addImm(Amt)
128 .addImm(Pred).addReg(0).addReg(0);
130 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
131 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
132 .addReg(BaseReg).addReg(OffReg)
133 .addImm(Pred).addReg(0).addReg(0);
138 std::vector<MachineInstr*> NewMIs;
141 MemMI = BuildMI(MF, MI->getDebugLoc(),
142 get(MemOpc), MI->getOperand(0).getReg())
143 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
145 MemMI = BuildMI(MF, MI->getDebugLoc(),
146 get(MemOpc)).addReg(MI->getOperand(1).getReg())
147 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
148 NewMIs.push_back(MemMI);
149 NewMIs.push_back(UpdateMI);
152 MemMI = BuildMI(MF, MI->getDebugLoc(),
153 get(MemOpc), MI->getOperand(0).getReg())
154 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
156 MemMI = BuildMI(MF, MI->getDebugLoc(),
157 get(MemOpc)).addReg(MI->getOperand(1).getReg())
158 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
160 UpdateMI->getOperand(0).setIsDead();
161 NewMIs.push_back(UpdateMI);
162 NewMIs.push_back(MemMI);
165 // Transfer LiveVariables states, kill / dead info.
167 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg() && MO.getReg() &&
170 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
171 unsigned Reg = MO.getReg();
173 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
175 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
177 LV->addVirtualRegisterDead(Reg, NewMI);
179 if (MO.isUse() && MO.isKill()) {
180 for (unsigned j = 0; j < 2; ++j) {
181 // Look at the two new MI's in reverse order.
182 MachineInstr *NewMI = NewMIs[j];
183 if (!NewMI->readsRegister(Reg))
185 LV->addVirtualRegisterKilled(Reg, NewMI);
186 if (VI.removeKill(MI))
187 VI.Kills.push_back(NewMI);
195 MFI->insert(MBBI, NewMIs[1]);
196 MFI->insert(MBBI, NewMIs[0]);
201 ARMBaseInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MI,
203 const std::vector<CalleeSavedInfo> &CSI,
204 const TargetRegisterInfo *TRI) const {
209 if (MI != MBB.end()) DL = MI->getDebugLoc();
211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
212 unsigned Reg = CSI[i].getReg();
215 // Add the callee-saved register as live-in unless it's LR and
216 // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
217 // then it's already added to the function and entry block live-in sets.
218 if (Reg == ARM::LR) {
219 MachineFunction &MF = *MBB.getParent();
220 if (MF.getFrameInfo()->isReturnAddressTaken() &&
221 MF.getRegInfo().isLiveIn(Reg))
228 // Insert the spill to the stack frame. The register is killed at the spill
230 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
231 storeRegToStackSlot(MBB, MI, Reg, isKill,
232 CSI[i].getFrameIdx(), RC, TRI);
239 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
240 MachineBasicBlock *&FBB,
241 SmallVectorImpl<MachineOperand> &Cond,
242 bool AllowModify) const {
243 // If the block has no terminators, it just falls into the block after it.
244 MachineBasicBlock::iterator I = MBB.end();
245 if (I == MBB.begin())
248 while (I->isDebugValue()) {
249 if (I == MBB.begin())
253 if (!isUnpredicatedTerminator(I))
256 // Get the last instruction in the block.
257 MachineInstr *LastInst = I;
259 // If there is only one terminator instruction, process it.
260 unsigned LastOpc = LastInst->getOpcode();
261 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
262 if (isUncondBranchOpcode(LastOpc)) {
263 TBB = LastInst->getOperand(0).getMBB();
266 if (isCondBranchOpcode(LastOpc)) {
267 // Block ends with fall-through condbranch.
268 TBB = LastInst->getOperand(0).getMBB();
269 Cond.push_back(LastInst->getOperand(1));
270 Cond.push_back(LastInst->getOperand(2));
273 return true; // Can't handle indirect branch.
276 // Get the instruction before it if it is a terminator.
277 MachineInstr *SecondLastInst = I;
279 // If there are three terminators, we don't know what sort of block this is.
280 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
283 // If the block ends with a B and a Bcc, handle it.
284 unsigned SecondLastOpc = SecondLastInst->getOpcode();
285 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
286 TBB = SecondLastInst->getOperand(0).getMBB();
287 Cond.push_back(SecondLastInst->getOperand(1));
288 Cond.push_back(SecondLastInst->getOperand(2));
289 FBB = LastInst->getOperand(0).getMBB();
293 // If the block ends with two unconditional branches, handle it. The second
294 // one is not executed, so remove it.
295 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
296 TBB = SecondLastInst->getOperand(0).getMBB();
299 I->eraseFromParent();
303 // ...likewise if it ends with a branch table followed by an unconditional
304 // branch. The branch folder can create these, and we must get rid of them for
305 // correctness of Thumb constant islands.
306 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
307 isIndirectBranchOpcode(SecondLastOpc)) &&
308 isUncondBranchOpcode(LastOpc)) {
311 I->eraseFromParent();
315 // Otherwise, can't handle this.
320 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
321 MachineBasicBlock::iterator I = MBB.end();
322 if (I == MBB.begin()) return 0;
324 while (I->isDebugValue()) {
325 if (I == MBB.begin())
329 if (!isUncondBranchOpcode(I->getOpcode()) &&
330 !isCondBranchOpcode(I->getOpcode()))
333 // Remove the branch.
334 I->eraseFromParent();
338 if (I == MBB.begin()) return 1;
340 if (!isCondBranchOpcode(I->getOpcode()))
343 // Remove the branch.
344 I->eraseFromParent();
349 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350 MachineBasicBlock *FBB,
351 const SmallVectorImpl<MachineOperand> &Cond,
353 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
354 int BOpc = !AFI->isThumbFunction()
355 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
356 int BccOpc = !AFI->isThumbFunction()
357 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
359 // Shouldn't be a fall through.
360 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
361 assert((Cond.size() == 2 || Cond.size() == 0) &&
362 "ARM branch conditions have two components!");
365 if (Cond.empty()) // Unconditional branch?
366 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
368 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
369 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
373 // Two-way conditional branch.
374 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
375 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
376 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
380 bool ARMBaseInstrInfo::
381 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
382 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
383 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
387 bool ARMBaseInstrInfo::
388 PredicateInstruction(MachineInstr *MI,
389 const SmallVectorImpl<MachineOperand> &Pred) const {
390 unsigned Opc = MI->getOpcode();
391 if (isUncondBranchOpcode(Opc)) {
392 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
393 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
394 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
398 int PIdx = MI->findFirstPredOperandIdx();
400 MachineOperand &PMO = MI->getOperand(PIdx);
401 PMO.setImm(Pred[0].getImm());
402 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
408 bool ARMBaseInstrInfo::
409 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
410 const SmallVectorImpl<MachineOperand> &Pred2) const {
411 if (Pred1.size() > 2 || Pred2.size() > 2)
414 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
415 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
425 return CC2 == ARMCC::HI;
427 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
429 return CC2 == ARMCC::GT;
431 return CC2 == ARMCC::LT;
435 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
436 std::vector<MachineOperand> &Pred) const {
437 // FIXME: This confuses implicit_def with optional CPSR def.
438 const TargetInstrDesc &TID = MI->getDesc();
439 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
443 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444 const MachineOperand &MO = MI->getOperand(i);
445 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
454 /// isPredicable - Return true if the specified instruction can be predicated.
455 /// By default, this returns true for every instruction with a
456 /// PredicateOperand.
457 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
458 const TargetInstrDesc &TID = MI->getDesc();
459 if (!TID.isPredicable())
462 if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
463 ARMFunctionInfo *AFI =
464 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
465 return AFI->isThumb2Function();
470 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
472 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
474 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
476 assert(JTI < JT.size());
477 return JT[JTI].MBBs.size();
480 /// GetInstSize - Return the size of the specified MachineInstr.
482 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
483 const MachineBasicBlock &MBB = *MI->getParent();
484 const MachineFunction *MF = MBB.getParent();
485 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
487 // Basic size info comes from the TSFlags field.
488 const TargetInstrDesc &TID = MI->getDesc();
489 uint64_t TSFlags = TID.TSFlags;
491 unsigned Opc = MI->getOpcode();
492 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
494 // If this machine instr is an inline asm, measure it.
495 if (MI->getOpcode() == ARM::INLINEASM)
496 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
501 llvm_unreachable("Unknown or unset size field for instr!");
502 case TargetOpcode::IMPLICIT_DEF:
503 case TargetOpcode::KILL:
504 case TargetOpcode::DBG_LABEL:
505 case TargetOpcode::EH_LABEL:
506 case TargetOpcode::DBG_VALUE:
511 case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
512 case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
513 case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
514 case ARMII::SizeSpecial: {
516 case ARM::CONSTPOOL_ENTRY:
517 // If this machine instr is a constant pool entry, its size is recorded as
519 return MI->getOperand(2).getImm();
520 case ARM::Int_eh_sjlj_longjmp:
522 case ARM::tInt_eh_sjlj_longjmp:
524 case ARM::Int_eh_sjlj_setjmp:
525 case ARM::Int_eh_sjlj_setjmp_nofp:
527 case ARM::tInt_eh_sjlj_setjmp:
528 case ARM::t2Int_eh_sjlj_setjmp:
529 case ARM::t2Int_eh_sjlj_setjmp_nofp:
538 // These are jumptable branches, i.e. a branch followed by an inlined
539 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
540 // entry is one byte; TBH two byte each.
541 unsigned EntrySize = (Opc == ARM::t2TBB)
542 ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
543 unsigned NumOps = TID.getNumOperands();
544 MachineOperand JTOP =
545 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
546 unsigned JTI = JTOP.getIndex();
547 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
549 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
550 assert(JTI < JT.size());
551 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
552 // 4 aligned. The assembler / linker may add 2 byte padding just before
553 // the JT entries. The size does not include this padding; the
554 // constant islands pass does separate bookkeeping for it.
555 // FIXME: If we know the size of the function is less than (1 << 16) *2
556 // bytes, we can use 16-bit entries instead. Then there won't be an
558 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
559 unsigned NumEntries = getNumJTEntries(JT, JTI);
560 if (Opc == ARM::t2TBB && (NumEntries & 1))
561 // Make sure the instruction that follows TBB is 2-byte aligned.
562 // FIXME: Constant island pass should insert an "ALIGN" instruction
565 return NumEntries * EntrySize + InstSize;
568 // Otherwise, pseudo-instruction sizes are zero.
573 return 0; // Not reached
576 /// Return true if the instruction is a register to register move and
577 /// leave the source and dest operands in the passed parameters.
580 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
581 unsigned &SrcReg, unsigned &DstReg,
582 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
583 switch (MI.getOpcode()) {
590 SrcReg = MI.getOperand(1).getReg();
591 DstReg = MI.getOperand(0).getReg();
592 SrcSubIdx = MI.getOperand(1).getSubReg();
593 DstSubIdx = MI.getOperand(0).getSubReg();
599 case ARM::tMOVgpr2tgpr:
600 case ARM::tMOVtgpr2gpr:
601 case ARM::tMOVgpr2gpr:
603 assert(MI.getDesc().getNumOperands() >= 2 &&
604 MI.getOperand(0).isReg() &&
605 MI.getOperand(1).isReg() &&
606 "Invalid ARM MOV instruction");
607 SrcReg = MI.getOperand(1).getReg();
608 DstReg = MI.getOperand(0).getReg();
609 SrcSubIdx = MI.getOperand(1).getSubReg();
610 DstSubIdx = MI.getOperand(0).getSubReg();
619 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
620 int &FrameIndex) const {
621 switch (MI->getOpcode()) {
624 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
625 if (MI->getOperand(1).isFI() &&
626 MI->getOperand(2).isReg() &&
627 MI->getOperand(3).isImm() &&
628 MI->getOperand(2).getReg() == 0 &&
629 MI->getOperand(3).getImm() == 0) {
630 FrameIndex = MI->getOperand(1).getIndex();
631 return MI->getOperand(0).getReg();
636 if (MI->getOperand(1).isFI() &&
637 MI->getOperand(2).isImm() &&
638 MI->getOperand(2).getImm() == 0) {
639 FrameIndex = MI->getOperand(1).getIndex();
640 return MI->getOperand(0).getReg();
645 if (MI->getOperand(1).isFI() &&
646 MI->getOperand(2).isImm() &&
647 MI->getOperand(2).getImm() == 0) {
648 FrameIndex = MI->getOperand(1).getIndex();
649 return MI->getOperand(0).getReg();
658 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
659 int &FrameIndex) const {
660 switch (MI->getOpcode()) {
663 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
664 if (MI->getOperand(1).isFI() &&
665 MI->getOperand(2).isReg() &&
666 MI->getOperand(3).isImm() &&
667 MI->getOperand(2).getReg() == 0 &&
668 MI->getOperand(3).getImm() == 0) {
669 FrameIndex = MI->getOperand(1).getIndex();
670 return MI->getOperand(0).getReg();
675 if (MI->getOperand(1).isFI() &&
676 MI->getOperand(2).isImm() &&
677 MI->getOperand(2).getImm() == 0) {
678 FrameIndex = MI->getOperand(1).getIndex();
679 return MI->getOperand(0).getReg();
684 if (MI->getOperand(1).isFI() &&
685 MI->getOperand(2).isImm() &&
686 MI->getOperand(2).getImm() == 0) {
687 FrameIndex = MI->getOperand(1).getIndex();
688 return MI->getOperand(0).getReg();
697 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
698 MachineBasicBlock::iterator I,
699 unsigned DestReg, unsigned SrcReg,
700 const TargetRegisterClass *DestRC,
701 const TargetRegisterClass *SrcRC,
703 // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid
704 // using certain registers. Just treat them as GPR here.
705 if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass)
706 DestRC = ARM::GPRRegisterClass;
707 if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
708 SrcRC = ARM::GPRRegisterClass;
710 if (DestRC == ARM::SPR_8RegisterClass)
711 DestRC = ARM::SPRRegisterClass;
712 if (SrcRC == ARM::SPR_8RegisterClass)
713 SrcRC = ARM::SPRRegisterClass;
715 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
716 if (DestRC == ARM::DPR_8RegisterClass)
717 DestRC = ARM::DPR_VFP2RegisterClass;
718 if (SrcRC == ARM::DPR_8RegisterClass)
719 SrcRC = ARM::DPR_VFP2RegisterClass;
721 // NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
722 if (DestRC == ARM::DPR_VFP2RegisterClass)
723 DestRC = ARM::DPRRegisterClass;
724 if (SrcRC == ARM::DPR_VFP2RegisterClass)
725 SrcRC = ARM::DPRRegisterClass;
727 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
728 if (DestRC == ARM::QPR_VFP2RegisterClass ||
729 DestRC == ARM::QPR_8RegisterClass)
730 DestRC = ARM::QPRRegisterClass;
731 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
732 SrcRC == ARM::QPR_8RegisterClass)
733 SrcRC = ARM::QPRRegisterClass;
735 // Allow QQPR / QQPR_VFP2 cross-class copies.
736 if (DestRC == ARM::QQPR_VFP2RegisterClass)
737 DestRC = ARM::QQPRRegisterClass;
738 if (SrcRC == ARM::QQPR_VFP2RegisterClass)
739 SrcRC = ARM::QQPRRegisterClass;
741 // Disallow copies of unequal sizes.
742 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
745 if (DestRC == ARM::GPRRegisterClass) {
746 if (SrcRC == ARM::SPRRegisterClass)
747 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
750 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
751 DestReg).addReg(SrcReg)));
755 if (DestRC == ARM::SPRRegisterClass)
756 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
757 else if (DestRC == ARM::DPRRegisterClass)
759 else if (DestRC == ARM::QPRRegisterClass)
761 else if (DestRC == ARM::QQPRRegisterClass)
763 else if (DestRC == ARM::QQQQPRRegisterClass)
768 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
770 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
778 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
779 unsigned Reg, unsigned SubIdx, unsigned State,
780 const TargetRegisterInfo *TRI) {
782 return MIB.addReg(Reg, State);
784 if (TargetRegisterInfo::isPhysicalRegister(Reg))
785 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
786 return MIB.addReg(Reg, State, SubIdx);
789 void ARMBaseInstrInfo::
790 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
791 unsigned SrcReg, bool isKill, int FI,
792 const TargetRegisterClass *RC,
793 const TargetRegisterInfo *TRI) const {
795 if (I != MBB.end()) DL = I->getDebugLoc();
796 MachineFunction &MF = *MBB.getParent();
797 MachineFrameInfo &MFI = *MF.getFrameInfo();
798 unsigned Align = MFI.getObjectAlignment(FI);
800 MachineMemOperand *MMO =
801 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
802 MachineMemOperand::MOStore, 0,
803 MFI.getObjectSize(FI),
806 // tGPR is used sometimes in ARM instructions that need to avoid using
807 // certain registers. Just treat it as GPR here.
808 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
809 RC = ARM::GPRRegisterClass;
811 switch (RC->getID()) {
812 case ARM::GPRRegClassID:
813 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
814 .addReg(SrcReg, getKillRegState(isKill))
815 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
817 case ARM::SPRRegClassID:
818 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
819 .addReg(SrcReg, getKillRegState(isKill))
820 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
822 case ARM::DPRRegClassID:
823 case ARM::DPR_VFP2RegClassID:
824 case ARM::DPR_8RegClassID:
825 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
826 .addReg(SrcReg, getKillRegState(isKill))
827 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
829 case ARM::QPRRegClassID:
830 case ARM::QPR_VFP2RegClassID:
831 case ARM::QPR_8RegClassID:
832 // FIXME: Neon instructions should support predicates
833 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
834 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
835 .addFrameIndex(FI).addImm(16)
836 .addReg(SrcReg, getKillRegState(isKill))
837 .addMemOperand(MMO));
839 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
840 .addReg(SrcReg, getKillRegState(isKill))
842 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
843 .addMemOperand(MMO));
846 case ARM::QQPRRegClassID:
847 case ARM::QQPR_VFP2RegClassID:
848 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
849 // FIXME: It's possible to only store part of the QQ register if the
850 // spilled def has a sub-register index.
851 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
852 .addFrameIndex(FI).addImm(16);
853 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
854 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
855 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
856 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
857 AddDefaultPred(MIB.addMemOperand(MMO));
859 MachineInstrBuilder MIB =
860 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
862 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
864 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
865 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
866 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
867 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
870 case ARM::QQQQPRRegClassID: {
871 MachineInstrBuilder MIB =
872 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
874 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
876 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
877 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
878 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
879 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
880 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
881 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
882 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
883 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
887 llvm_unreachable("Unknown regclass!");
891 void ARMBaseInstrInfo::
892 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
893 unsigned DestReg, int FI,
894 const TargetRegisterClass *RC,
895 const TargetRegisterInfo *TRI) const {
897 if (I != MBB.end()) DL = I->getDebugLoc();
898 MachineFunction &MF = *MBB.getParent();
899 MachineFrameInfo &MFI = *MF.getFrameInfo();
900 unsigned Align = MFI.getObjectAlignment(FI);
901 MachineMemOperand *MMO =
902 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
903 MachineMemOperand::MOLoad, 0,
904 MFI.getObjectSize(FI),
907 // tGPR is used sometimes in ARM instructions that need to avoid using
908 // certain registers. Just treat it as GPR here.
909 if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass)
910 RC = ARM::GPRRegisterClass;
912 switch (RC->getID()) {
913 case ARM::GPRRegClassID:
914 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
915 .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
917 case ARM::SPRRegClassID:
918 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
919 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
921 case ARM::DPRRegClassID:
922 case ARM::DPR_VFP2RegClassID:
923 case ARM::DPR_8RegClassID:
924 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
925 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
927 case ARM::QPRRegClassID:
928 case ARM::QPR_VFP2RegClassID:
929 case ARM::QPR_8RegClassID:
930 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
931 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
932 .addFrameIndex(FI).addImm(16)
933 .addMemOperand(MMO));
935 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
937 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
938 .addMemOperand(MMO));
941 case ARM::QQPRRegClassID:
942 case ARM::QQPR_VFP2RegClassID:
943 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
944 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
945 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
946 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
947 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
948 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
949 AddDefaultPred(MIB.addFrameIndex(FI).addImm(16).addMemOperand(MMO));
951 MachineInstrBuilder MIB =
952 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
954 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
956 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
957 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
958 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
959 AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
962 case ARM::QQQQPRRegClassID: {
963 MachineInstrBuilder MIB =
964 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
966 .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
968 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
969 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
970 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
971 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
972 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
973 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
974 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
975 AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
979 llvm_unreachable("Unknown regclass!");
984 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
985 int FrameIx, uint64_t Offset,
988 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
989 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
993 MachineInstr *ARMBaseInstrInfo::
994 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
995 const SmallVectorImpl<unsigned> &Ops, int FI) const {
996 if (Ops.size() != 1) return NULL;
998 unsigned OpNum = Ops[0];
999 unsigned Opc = MI->getOpcode();
1000 MachineInstr *NewMI = NULL;
1001 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1002 // If it is updating CPSR, then it cannot be folded.
1003 if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
1005 unsigned Pred = MI->getOperand(2).getImm();
1006 unsigned PredReg = MI->getOperand(3).getReg();
1007 if (OpNum == 0) { // move -> store
1008 unsigned SrcReg = MI->getOperand(1).getReg();
1009 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1010 bool isKill = MI->getOperand(1).isKill();
1011 bool isUndef = MI->getOperand(1).isUndef();
1012 if (Opc == ARM::MOVr)
1013 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
1015 getKillRegState(isKill) | getUndefRegState(isUndef),
1017 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1019 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1021 getKillRegState(isKill) | getUndefRegState(isUndef),
1023 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1024 } else { // move -> load
1025 unsigned DstReg = MI->getOperand(0).getReg();
1026 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1027 bool isDead = MI->getOperand(0).isDead();
1028 bool isUndef = MI->getOperand(0).isUndef();
1029 if (Opc == ARM::MOVr)
1030 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
1033 getDeadRegState(isDead) |
1034 getUndefRegState(isUndef), DstSubReg)
1035 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1037 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1040 getDeadRegState(isDead) |
1041 getUndefRegState(isUndef), DstSubReg)
1042 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1044 } else if (Opc == ARM::tMOVgpr2gpr ||
1045 Opc == ARM::tMOVtgpr2gpr ||
1046 Opc == ARM::tMOVgpr2tgpr) {
1047 if (OpNum == 0) { // move -> store
1048 unsigned SrcReg = MI->getOperand(1).getReg();
1049 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1050 bool isKill = MI->getOperand(1).isKill();
1051 bool isUndef = MI->getOperand(1).isUndef();
1052 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
1054 getKillRegState(isKill) | getUndefRegState(isUndef),
1056 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1057 } else { // move -> load
1058 unsigned DstReg = MI->getOperand(0).getReg();
1059 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1060 bool isDead = MI->getOperand(0).isDead();
1061 bool isUndef = MI->getOperand(0).isUndef();
1062 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
1065 getDeadRegState(isDead) |
1066 getUndefRegState(isUndef),
1068 .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
1070 } else if (Opc == ARM::VMOVS) {
1071 unsigned Pred = MI->getOperand(2).getImm();
1072 unsigned PredReg = MI->getOperand(3).getReg();
1073 if (OpNum == 0) { // move -> store
1074 unsigned SrcReg = MI->getOperand(1).getReg();
1075 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1076 bool isKill = MI->getOperand(1).isKill();
1077 bool isUndef = MI->getOperand(1).isUndef();
1078 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
1079 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
1082 .addImm(0).addImm(Pred).addReg(PredReg);
1083 } else { // move -> load
1084 unsigned DstReg = MI->getOperand(0).getReg();
1085 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1086 bool isDead = MI->getOperand(0).isDead();
1087 bool isUndef = MI->getOperand(0).isUndef();
1088 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
1091 getDeadRegState(isDead) |
1092 getUndefRegState(isUndef),
1094 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1096 } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
1097 unsigned Pred = MI->getOperand(2).getImm();
1098 unsigned PredReg = MI->getOperand(3).getReg();
1099 if (OpNum == 0) { // move -> store
1100 unsigned SrcReg = MI->getOperand(1).getReg();
1101 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1102 bool isKill = MI->getOperand(1).isKill();
1103 bool isUndef = MI->getOperand(1).isUndef();
1104 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
1106 getKillRegState(isKill) | getUndefRegState(isUndef),
1108 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1109 } else { // move -> load
1110 unsigned DstReg = MI->getOperand(0).getReg();
1111 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1112 bool isDead = MI->getOperand(0).isDead();
1113 bool isUndef = MI->getOperand(0).isUndef();
1114 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
1117 getDeadRegState(isDead) |
1118 getUndefRegState(isUndef),
1120 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
1122 } else if (Opc == ARM::VMOVQ) {
1123 MachineFrameInfo &MFI = *MF.getFrameInfo();
1124 unsigned Pred = MI->getOperand(2).getImm();
1125 unsigned PredReg = MI->getOperand(3).getReg();
1126 if (OpNum == 0) { // move -> store
1127 unsigned SrcReg = MI->getOperand(1).getReg();
1128 unsigned SrcSubReg = MI->getOperand(1).getSubReg();
1129 bool isKill = MI->getOperand(1).isKill();
1130 bool isUndef = MI->getOperand(1).isUndef();
1131 if (MFI.getObjectAlignment(FI) >= 16 &&
1132 getRegisterInfo().canRealignStack(MF)) {
1133 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
1134 .addFrameIndex(FI).addImm(16)
1136 getKillRegState(isKill) | getUndefRegState(isUndef),
1138 .addImm(Pred).addReg(PredReg);
1140 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
1142 getKillRegState(isKill) | getUndefRegState(isUndef),
1144 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1145 .addImm(Pred).addReg(PredReg);
1147 } else { // move -> load
1148 unsigned DstReg = MI->getOperand(0).getReg();
1149 unsigned DstSubReg = MI->getOperand(0).getSubReg();
1150 bool isDead = MI->getOperand(0).isDead();
1151 bool isUndef = MI->getOperand(0).isUndef();
1152 if (MFI.getObjectAlignment(FI) >= 16 &&
1153 getRegisterInfo().canRealignStack(MF)) {
1154 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
1157 getDeadRegState(isDead) |
1158 getUndefRegState(isUndef),
1160 .addFrameIndex(FI).addImm(16).addImm(Pred).addReg(PredReg);
1162 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
1165 getDeadRegState(isDead) |
1166 getUndefRegState(isUndef),
1168 .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
1169 .addImm(Pred).addReg(PredReg);
1178 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
1180 const SmallVectorImpl<unsigned> &Ops,
1181 MachineInstr* LoadMI) const {
1187 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
1188 const SmallVectorImpl<unsigned> &Ops) const {
1189 if (Ops.size() != 1) return false;
1191 unsigned Opc = MI->getOpcode();
1192 if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
1193 // If it is updating CPSR, then it cannot be folded.
1194 return MI->getOperand(4).getReg() != ARM::CPSR ||
1195 MI->getOperand(4).isDead();
1196 } else if (Opc == ARM::tMOVgpr2gpr ||
1197 Opc == ARM::tMOVtgpr2gpr ||
1198 Opc == ARM::tMOVgpr2tgpr) {
1200 } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
1201 Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
1205 // FIXME: VMOVQQ and VMOVQQQQ?
1210 /// Create a copy of a const pool value. Update CPI to the new index and return
1212 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1213 MachineConstantPool *MCP = MF.getConstantPool();
1214 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1216 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1217 assert(MCPE.isMachineConstantPoolEntry() &&
1218 "Expecting a machine constantpool entry!");
1219 ARMConstantPoolValue *ACPV =
1220 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1222 unsigned PCLabelId = AFI->createConstPoolEntryUId();
1223 ARMConstantPoolValue *NewCPV = 0;
1224 if (ACPV->isGlobalValue())
1225 NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId,
1227 else if (ACPV->isExtSymbol())
1228 NewCPV = new ARMConstantPoolValue(MF.getFunction()->getContext(),
1229 ACPV->getSymbol(), PCLabelId, 4);
1230 else if (ACPV->isBlockAddress())
1231 NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId,
1232 ARMCP::CPBlockAddress, 4);
1234 llvm_unreachable("Unexpected ARM constantpool value type!!");
1235 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1239 void ARMBaseInstrInfo::
1240 reMaterialize(MachineBasicBlock &MBB,
1241 MachineBasicBlock::iterator I,
1242 unsigned DestReg, unsigned SubIdx,
1243 const MachineInstr *Orig,
1244 const TargetRegisterInfo &TRI) const {
1245 unsigned Opcode = Orig->getOpcode();
1248 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1249 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1253 case ARM::tLDRpci_pic:
1254 case ARM::t2LDRpci_pic: {
1255 MachineFunction &MF = *MBB.getParent();
1256 unsigned CPI = Orig->getOperand(1).getIndex();
1257 unsigned PCLabelId = duplicateCPV(MF, CPI);
1258 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1260 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1261 (*MIB).setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1268 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1269 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1270 switch(Orig->getOpcode()) {
1271 case ARM::tLDRpci_pic:
1272 case ARM::t2LDRpci_pic: {
1273 unsigned CPI = Orig->getOperand(1).getIndex();
1274 unsigned PCLabelId = duplicateCPV(MF, CPI);
1275 Orig->getOperand(1).setIndex(CPI);
1276 Orig->getOperand(2).setImm(PCLabelId);
1283 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1284 const MachineInstr *MI1) const {
1285 int Opcode = MI0->getOpcode();
1286 if (Opcode == ARM::t2LDRpci ||
1287 Opcode == ARM::t2LDRpci_pic ||
1288 Opcode == ARM::tLDRpci ||
1289 Opcode == ARM::tLDRpci_pic) {
1290 if (MI1->getOpcode() != Opcode)
1292 if (MI0->getNumOperands() != MI1->getNumOperands())
1295 const MachineOperand &MO0 = MI0->getOperand(1);
1296 const MachineOperand &MO1 = MI1->getOperand(1);
1297 if (MO0.getOffset() != MO1.getOffset())
1300 const MachineFunction *MF = MI0->getParent()->getParent();
1301 const MachineConstantPool *MCP = MF->getConstantPool();
1302 int CPI0 = MO0.getIndex();
1303 int CPI1 = MO1.getIndex();
1304 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1305 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1306 ARMConstantPoolValue *ACPV0 =
1307 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1308 ARMConstantPoolValue *ACPV1 =
1309 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1310 return ACPV0->hasSameValue(ACPV1);
1313 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1316 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1317 /// determine if two loads are loading from the same base address. It should
1318 /// only return true if the base pointers are the same and the only differences
1319 /// between the two addresses is the offset. It also returns the offsets by
1321 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1323 int64_t &Offset2) const {
1324 // Don't worry about Thumb: just ARM and Thumb2.
1325 if (Subtarget.isThumb1Only()) return false;
1327 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1330 switch (Load1->getMachineOpcode()) {
1343 case ARM::t2LDRSHi8:
1345 case ARM::t2LDRSHi12:
1349 switch (Load2->getMachineOpcode()) {
1362 case ARM::t2LDRSHi8:
1364 case ARM::t2LDRSHi12:
1368 // Check if base addresses and chain operands match.
1369 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1370 Load1->getOperand(4) != Load2->getOperand(4))
1373 // Index should be Reg0.
1374 if (Load1->getOperand(3) != Load2->getOperand(3))
1377 // Determine the offsets.
1378 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1379 isa<ConstantSDNode>(Load2->getOperand(1))) {
1380 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1381 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1388 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1389 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
1390 /// be scheduled togther. On some targets if two loads are loading from
1391 /// addresses in the same cache line, it's better if they are scheduled
1392 /// together. This function takes two integers that represent the load offsets
1393 /// from the common base address. It returns true if it decides it's desirable
1394 /// to schedule the two loads together. "NumLoads" is the number of loads that
1395 /// have already been scheduled after Load1.
1396 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1397 int64_t Offset1, int64_t Offset2,
1398 unsigned NumLoads) const {
1399 // Don't worry about Thumb: just ARM and Thumb2.
1400 if (Subtarget.isThumb1Only()) return false;
1402 assert(Offset2 > Offset1);
1404 if ((Offset2 - Offset1) / 8 > 64)
1407 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1408 return false; // FIXME: overly conservative?
1410 // Four loads in a row should be sufficient.
1417 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1418 const MachineBasicBlock *MBB,
1419 const MachineFunction &MF) const {
1420 // Debug info is never a scheduling boundary. It's necessary to be explicit
1421 // due to the special treatment of IT instructions below, otherwise a
1422 // dbg_value followed by an IT will result in the IT instruction being
1423 // considered a scheduling hazard, which is wrong. It should be the actual
1424 // instruction preceding the dbg_value instruction(s), just like it is
1425 // when debug info is not present.
1426 if (MI->isDebugValue())
1429 // Terminators and labels can't be scheduled around.
1430 if (MI->getDesc().isTerminator() || MI->isLabel())
1433 // Treat the start of the IT block as a scheduling boundary, but schedule
1434 // t2IT along with all instructions following it.
1435 // FIXME: This is a big hammer. But the alternative is to add all potential
1436 // true and anti dependencies to IT block instructions as implicit operands
1437 // to the t2IT instruction. The added compile time and complexity does not
1439 MachineBasicBlock::const_iterator I = MI;
1440 // Make sure to skip any dbg_value instructions
1441 while (++I != MBB->end() && I->isDebugValue())
1443 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1446 // Don't attempt to schedule around any instruction that defines
1447 // a stack-oriented pointer, as it's unlikely to be profitable. This
1448 // saves compile time, because it doesn't require every single
1449 // stack slot reference to depend on the instruction that does the
1451 if (MI->definesRegister(ARM::SP))
1457 bool ARMBaseInstrInfo::
1458 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const {
1461 if (Subtarget.getCPUString() == "generic")
1462 // Generic (and overly aggressive) if-conversion limits for testing.
1463 return NumInstrs <= 10;
1464 else if (Subtarget.hasV7Ops())
1465 return NumInstrs <= 3;
1466 return NumInstrs <= 2;
1469 bool ARMBaseInstrInfo::
1470 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
1471 MachineBasicBlock &FMBB, unsigned NumF) const {
1472 return NumT && NumF && NumT <= 2 && NumF <= 2;
1475 /// getInstrPredicate - If instruction is predicated, returns its predicate
1476 /// condition, otherwise returns AL. It also returns the condition code
1477 /// register by reference.
1479 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1480 int PIdx = MI->findFirstPredOperandIdx();
1486 PredReg = MI->getOperand(PIdx+1).getReg();
1487 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1491 int llvm::getMatchingCondBranchOpcode(int Opc) {
1494 else if (Opc == ARM::tB)
1496 else if (Opc == ARM::t2B)
1499 llvm_unreachable("Unknown unconditional branch opcode!");
1504 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1505 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1506 unsigned DestReg, unsigned BaseReg, int NumBytes,
1507 ARMCC::CondCodes Pred, unsigned PredReg,
1508 const ARMBaseInstrInfo &TII) {
1509 bool isSub = NumBytes < 0;
1510 if (isSub) NumBytes = -NumBytes;
1513 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1514 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1515 assert(ThisVal && "Didn't extract field correctly");
1517 // We will handle these bits from offset, clear them.
1518 NumBytes &= ~ThisVal;
1520 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1522 // Build the new ADD / SUB.
1523 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1524 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1525 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1526 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
1531 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1532 unsigned FrameReg, int &Offset,
1533 const ARMBaseInstrInfo &TII) {
1534 unsigned Opcode = MI.getOpcode();
1535 const TargetInstrDesc &Desc = MI.getDesc();
1536 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1539 // Memory operands in inline assembly always use AddrMode2.
1540 if (Opcode == ARM::INLINEASM)
1541 AddrMode = ARMII::AddrMode2;
1543 if (Opcode == ARM::ADDri) {
1544 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1546 // Turn it into a move.
1547 MI.setDesc(TII.get(ARM::MOVr));
1548 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1549 MI.RemoveOperand(FrameRegIdx+1);
1552 } else if (Offset < 0) {
1555 MI.setDesc(TII.get(ARM::SUBri));
1558 // Common case: small offset, fits into instruction.
1559 if (ARM_AM::getSOImmVal(Offset) != -1) {
1560 // Replace the FrameIndex with sp / fp
1561 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1562 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1567 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1569 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1570 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1572 // We will handle these bits from offset, clear them.
1573 Offset &= ~ThisImmVal;
1575 // Get the properly encoded SOImmVal field.
1576 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1577 "Bit extraction didn't work?");
1578 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1580 unsigned ImmIdx = 0;
1582 unsigned NumBits = 0;
1585 case ARMII::AddrMode2: {
1586 ImmIdx = FrameRegIdx+2;
1587 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1588 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1593 case ARMII::AddrMode3: {
1594 ImmIdx = FrameRegIdx+2;
1595 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1596 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1601 case ARMII::AddrMode4:
1602 case ARMII::AddrMode6:
1603 // Can't fold any offset even if it's zero.
1605 case ARMII::AddrMode5: {
1606 ImmIdx = FrameRegIdx+1;
1607 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1608 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1615 llvm_unreachable("Unsupported addressing mode!");
1619 Offset += InstrOffs * Scale;
1620 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1626 // Attempt to fold address comp. if opcode has offset bits
1628 // Common case: small offset, fits into instruction.
1629 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1630 int ImmedOffset = Offset / Scale;
1631 unsigned Mask = (1 << NumBits) - 1;
1632 if ((unsigned)Offset <= Mask * Scale) {
1633 // Replace the FrameIndex with sp
1634 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1636 ImmedOffset |= 1 << NumBits;
1637 ImmOp.ChangeToImmediate(ImmedOffset);
1642 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1643 ImmedOffset = ImmedOffset & Mask;
1645 ImmedOffset |= 1 << NumBits;
1646 ImmOp.ChangeToImmediate(ImmedOffset);
1647 Offset &= ~(Mask*Scale);
1651 Offset = (isSub) ? -Offset : Offset;