1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
23 class ARMBaseRegisterInfo;
25 /// ARMII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
30 //===------------------------------------------------------------------===//
33 //===------------------------------------------------------------------===//
34 // This four-bit field describes the addressing mode used.
47 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
51 AddrModeT2_pc = 14, // +/- i12 for pc relative data
52 AddrModeT2_i8s4 = 15, // i8 * 4
54 // Size* - Flags to keep track of the size of an instruction.
56 SizeMask = 7 << SizeShift,
57 SizeSpecial = 1, // 0 byte pseudo or special case.
62 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63 // and store ops only. Generic "updating" flag is used for ld/st multiple.
65 IndexModeMask = 3 << IndexModeShift,
70 //===------------------------------------------------------------------===//
71 // Instruction encoding formats.
74 FormMask = 0x3f << FormShift,
76 // Pseudo instructions
77 Pseudo = 0 << FormShift,
79 // Multiply instructions
80 MulFrm = 1 << FormShift,
82 // Branch instructions
83 BrFrm = 2 << FormShift,
84 BrMiscFrm = 3 << FormShift,
86 // Data Processing instructions
87 DPFrm = 4 << FormShift,
88 DPSoRegFrm = 5 << FormShift,
91 LdFrm = 6 << FormShift,
92 StFrm = 7 << FormShift,
93 LdMiscFrm = 8 << FormShift,
94 StMiscFrm = 9 << FormShift,
95 LdStMulFrm = 10 << FormShift,
97 LdStExFrm = 11 << FormShift,
99 // Miscellaneous arithmetic instructions
100 ArithMiscFrm = 12 << FormShift,
102 // Extend instructions
103 ExtFrm = 13 << FormShift,
106 VFPUnaryFrm = 14 << FormShift,
107 VFPBinaryFrm = 15 << FormShift,
108 VFPConv1Frm = 16 << FormShift,
109 VFPConv2Frm = 17 << FormShift,
110 VFPConv3Frm = 18 << FormShift,
111 VFPConv4Frm = 19 << FormShift,
112 VFPConv5Frm = 20 << FormShift,
113 VFPLdStFrm = 21 << FormShift,
114 VFPLdStMulFrm = 22 << FormShift,
115 VFPMiscFrm = 23 << FormShift,
118 ThumbFrm = 24 << FormShift,
120 // Miscelleaneous format
121 MiscFrm = 25 << FormShift,
124 NGetLnFrm = 26 << FormShift,
125 NSetLnFrm = 27 << FormShift,
126 NDupFrm = 28 << FormShift,
127 NLdStFrm = 29 << FormShift,
128 N1RegModImmFrm= 30 << FormShift,
129 N2RegFrm = 31 << FormShift,
130 NVCVTFrm = 32 << FormShift,
131 NVDupLnFrm = 33 << FormShift,
132 N2RegVShLFrm = 34 << FormShift,
133 N2RegVShRFrm = 35 << FormShift,
134 N3RegFrm = 36 << FormShift,
135 N3RegVShFrm = 37 << FormShift,
136 NVExtFrm = 38 << FormShift,
137 NVMulSLFrm = 39 << FormShift,
138 NVTBLFrm = 40 << FormShift,
140 //===------------------------------------------------------------------===//
143 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
144 // it doesn't have a Rn operand.
147 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
148 // a 16-bit Thumb instruction if certain conditions are met.
149 Xform16Bit = 1 << 16,
151 //===------------------------------------------------------------------===//
154 DomainMask = 3 << DomainShift,
155 DomainGeneral = 0 << DomainShift,
156 DomainVFP = 1 << DomainShift,
157 DomainNEON = 2 << DomainShift,
159 //===------------------------------------------------------------------===//
160 // Field shifts - such shifts are used to set field while generating
161 // machine instructions.
184 /// Target Operand Flag enum.
186 //===------------------------------------------------------------------===//
187 // ARM Specific MachineOperand flags.
191 /// MO_LO16 - On a symbol operand, this represents a relocation containing
192 /// lower 16 bit of the address. Used only via movw instruction.
195 /// MO_HI16 - On a symbol operand, this represents a relocation containing
196 /// higher 16 bit of the address. Used only via movt instruction.
201 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
202 const ARMSubtarget &Subtarget;
204 // Can be only subclassed.
205 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
207 // Return the non-pre/post incrementing version of 'Opc'. Return 0
208 // if there is not such an opcode.
209 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
211 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
212 MachineBasicBlock::iterator &MBBI,
213 LiveVariables *LV) const;
215 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
216 const ARMSubtarget &getSubtarget() const { return Subtarget; }
218 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator MI,
220 const std::vector<CalleeSavedInfo> &CSI,
221 const TargetRegisterInfo *TRI) const;
224 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
225 MachineBasicBlock *&FBB,
226 SmallVectorImpl<MachineOperand> &Cond,
227 bool AllowModify = false) const;
228 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
229 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
230 MachineBasicBlock *FBB,
231 const SmallVectorImpl<MachineOperand> &Cond,
235 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
237 // Predication support.
238 bool isPredicated(const MachineInstr *MI) const {
239 int PIdx = MI->findFirstPredOperandIdx();
240 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
243 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
244 int PIdx = MI->findFirstPredOperandIdx();
245 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
250 bool PredicateInstruction(MachineInstr *MI,
251 const SmallVectorImpl<MachineOperand> &Pred) const;
254 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
255 const SmallVectorImpl<MachineOperand> &Pred2) const;
257 virtual bool DefinesPredicate(MachineInstr *MI,
258 std::vector<MachineOperand> &Pred) const;
260 virtual bool isPredicable(MachineInstr *MI) const;
262 /// GetInstSize - Returns the size of the specified MachineInstr.
264 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
266 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
267 int &FrameIndex) const;
268 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
269 int &FrameIndex) const;
271 virtual void copyPhysReg(MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator I, DebugLoc DL,
273 unsigned DestReg, unsigned SrcReg,
276 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator MBBI,
278 unsigned SrcReg, bool isKill, int FrameIndex,
279 const TargetRegisterClass *RC,
280 const TargetRegisterInfo *TRI) const;
282 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator MBBI,
284 unsigned DestReg, int FrameIndex,
285 const TargetRegisterClass *RC,
286 const TargetRegisterInfo *TRI) const;
288 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
294 virtual void reMaterialize(MachineBasicBlock &MBB,
295 MachineBasicBlock::iterator MI,
296 unsigned DestReg, unsigned SubIdx,
297 const MachineInstr *Orig,
298 const TargetRegisterInfo &TRI) const;
300 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
302 virtual bool produceSameValue(const MachineInstr *MI0,
303 const MachineInstr *MI1) const;
305 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
306 /// determine if two loads are loading from the same base address. It should
307 /// only return true if the base pointers are the same and the only
308 /// differences between the two addresses is the offset. It also returns the
309 /// offsets by reference.
310 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
311 int64_t &Offset1, int64_t &Offset2)const;
313 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
314 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
315 /// be scheduled togther. On some targets if two loads are loading from
316 /// addresses in the same cache line, it's better if they are scheduled
317 /// together. This function takes two integers that represent the load offsets
318 /// from the common base address. It returns true if it decides it's desirable
319 /// to schedule the two loads together. "NumLoads" is the number of loads that
320 /// have already been scheduled after Load1.
321 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
322 int64_t Offset1, int64_t Offset2,
323 unsigned NumLoads) const;
325 virtual bool isSchedulingBoundary(const MachineInstr *MI,
326 const MachineBasicBlock *MBB,
327 const MachineFunction &MF) const;
329 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
330 unsigned NumInstrs) const;
332 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
333 MachineBasicBlock &FMBB,unsigned NumF) const;
335 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
336 unsigned NumInstrs) const {
337 return NumInstrs && NumInstrs == 1;
342 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
343 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
347 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
348 return MIB.addReg(0);
352 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
353 bool isDead = false) {
354 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
358 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
359 return MIB.addReg(0);
363 bool isUncondBranchOpcode(int Opc) {
364 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
368 bool isCondBranchOpcode(int Opc) {
369 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
373 bool isJumpTableBranchOpcode(int Opc) {
374 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
375 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
379 bool isIndirectBranchOpcode(int Opc) {
380 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
383 /// getInstrPredicate - If instruction is predicated, returns its predicate
384 /// condition, otherwise returns AL. It also returns the condition code
385 /// register by reference.
386 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
388 int getMatchingCondBranchOpcode(int Opc);
390 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
391 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
393 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
394 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
395 unsigned DestReg, unsigned BaseReg, int NumBytes,
396 ARMCC::CondCodes Pred, unsigned PredReg,
397 const ARMBaseInstrInfo &TII);
399 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
400 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
401 unsigned DestReg, unsigned BaseReg, int NumBytes,
402 ARMCC::CondCodes Pred, unsigned PredReg,
403 const ARMBaseInstrInfo &TII);
406 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
407 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
408 /// offset could not be handled directly in MI, and return the left-over
409 /// portion by reference.
410 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
411 unsigned FrameReg, int &Offset,
412 const ARMBaseInstrInfo &TII);
414 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
415 unsigned FrameReg, int &Offset,
416 const ARMBaseInstrInfo &TII);
418 } // End llvm namespace