1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
62 // and store ops only. Generic "updating" flag is used for ld/st multiple.
64 IndexModeMask = 3 << IndexModeShift,
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x3f << FormShift,
75 // Pseudo instructions
76 Pseudo = 0 << FormShift,
78 // Multiply instructions
79 MulFrm = 1 << FormShift,
81 // Branch instructions
82 BrFrm = 2 << FormShift,
83 BrMiscFrm = 3 << FormShift,
85 // Data Processing instructions
86 DPFrm = 4 << FormShift,
87 DPSoRegFrm = 5 << FormShift,
90 LdFrm = 6 << FormShift,
91 StFrm = 7 << FormShift,
92 LdMiscFrm = 8 << FormShift,
93 StMiscFrm = 9 << FormShift,
94 LdStMulFrm = 10 << FormShift,
96 LdStExFrm = 11 << FormShift,
98 // Miscellaneous arithmetic instructions
99 ArithMiscFrm = 12 << FormShift,
101 // Extend instructions
102 ExtFrm = 13 << FormShift,
105 VFPUnaryFrm = 14 << FormShift,
106 VFPBinaryFrm = 15 << FormShift,
107 VFPConv1Frm = 16 << FormShift,
108 VFPConv2Frm = 17 << FormShift,
109 VFPConv3Frm = 18 << FormShift,
110 VFPConv4Frm = 19 << FormShift,
111 VFPConv5Frm = 20 << FormShift,
112 VFPLdStFrm = 21 << FormShift,
113 VFPLdStMulFrm = 22 << FormShift,
114 VFPMiscFrm = 23 << FormShift,
117 ThumbFrm = 24 << FormShift,
120 NEONFrm = 25 << FormShift,
121 NEONGetLnFrm = 26 << FormShift,
122 NEONSetLnFrm = 27 << FormShift,
123 NEONDupFrm = 28 << FormShift,
125 //===------------------------------------------------------------------===//
128 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
129 // it doesn't have a Rn operand.
132 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
133 // a 16-bit Thumb instruction if certain conditions are met.
134 Xform16Bit = 1 << 16,
136 //===------------------------------------------------------------------===//
139 DomainMask = 3 << DomainShift,
140 DomainGeneral = 0 << DomainShift,
141 DomainVFP = 1 << DomainShift,
142 DomainNEON = 2 << DomainShift,
144 //===------------------------------------------------------------------===//
145 // Field shifts - such shifts are used to set field while generating
146 // machine instructions.
169 /// Target Operand Flag enum.
171 //===------------------------------------------------------------------===//
172 // ARM Specific MachineOperand flags.
176 /// MO_LO16 - On a symbol operand, this represents a relocation containing
177 /// lower 16 bit of the address. Used only via movw instruction.
180 /// MO_HI16 - On a symbol operand, this represents a relocation containing
181 /// higher 16 bit of the address. Used only via movt instruction.
186 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
187 const ARMSubtarget& Subtarget;
189 // Can be only subclassed.
190 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
192 // Return the non-pre/post incrementing version of 'Opc'. Return 0
193 // if there is not such an opcode.
194 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
196 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
197 MachineBasicBlock::iterator &MBBI,
198 LiveVariables *LV) const;
200 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
201 const ARMSubtarget &getSubtarget() const { return Subtarget; }
204 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
205 MachineBasicBlock *&FBB,
206 SmallVectorImpl<MachineOperand> &Cond,
207 bool AllowModify) const;
208 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
209 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
210 MachineBasicBlock *FBB,
211 const SmallVectorImpl<MachineOperand> &Cond) const;
214 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
216 // Predication support.
217 bool isPredicated(const MachineInstr *MI) const {
218 int PIdx = MI->findFirstPredOperandIdx();
219 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
222 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
223 int PIdx = MI->findFirstPredOperandIdx();
224 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
229 bool PredicateInstruction(MachineInstr *MI,
230 const SmallVectorImpl<MachineOperand> &Pred) const;
233 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
234 const SmallVectorImpl<MachineOperand> &Pred2) const;
236 virtual bool DefinesPredicate(MachineInstr *MI,
237 std::vector<MachineOperand> &Pred) const;
239 virtual bool isPredicable(MachineInstr *MI) const;
241 /// GetInstSize - Returns the size of the specified MachineInstr.
243 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
245 /// Return true if the instruction is a register to register move and return
246 /// the source and dest operands and their sub-register indices by reference.
247 virtual bool isMoveInstr(const MachineInstr &MI,
248 unsigned &SrcReg, unsigned &DstReg,
249 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
251 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
252 int &FrameIndex) const;
253 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
254 int &FrameIndex) const;
256 virtual bool copyRegToReg(MachineBasicBlock &MBB,
257 MachineBasicBlock::iterator I,
258 unsigned DestReg, unsigned SrcReg,
259 const TargetRegisterClass *DestRC,
260 const TargetRegisterClass *SrcRC) const;
262 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator MBBI,
264 unsigned SrcReg, bool isKill, int FrameIndex,
265 const TargetRegisterClass *RC) const;
267 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MBBI,
269 unsigned DestReg, int FrameIndex,
270 const TargetRegisterClass *RC) const;
272 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
273 const SmallVectorImpl<unsigned> &Ops) const;
275 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
277 const SmallVectorImpl<unsigned> &Ops,
278 int FrameIndex) const;
280 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
282 const SmallVectorImpl<unsigned> &Ops,
283 MachineInstr* LoadMI) const;
285 virtual void reMaterialize(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI,
287 unsigned DestReg, unsigned SubIdx,
288 const MachineInstr *Orig,
289 const TargetRegisterInfo *TRI) const;
291 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
293 virtual bool produceSameValue(const MachineInstr *MI0,
294 const MachineInstr *MI1) const;
298 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
299 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
303 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
304 return MIB.addReg(0);
308 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
309 bool isDead = false) {
310 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
314 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
315 return MIB.addReg(0);
319 bool isUncondBranchOpcode(int Opc) {
320 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
324 bool isCondBranchOpcode(int Opc) {
325 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
329 bool isJumpTableBranchOpcode(int Opc) {
330 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
331 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
335 bool isIndirectBranchOpcode(int Opc) {
336 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
339 /// getInstrPredicate - If instruction is predicated, returns its predicate
340 /// condition, otherwise returns AL. It also returns the condition code
341 /// register by reference.
342 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
344 int getMatchingCondBranchOpcode(int Opc);
346 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
347 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
349 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
350 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
351 unsigned DestReg, unsigned BaseReg, int NumBytes,
352 ARMCC::CondCodes Pred, unsigned PredReg,
353 const ARMBaseInstrInfo &TII);
355 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
356 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
357 unsigned DestReg, unsigned BaseReg, int NumBytes,
358 ARMCC::CondCodes Pred, unsigned PredReg,
359 const ARMBaseInstrInfo &TII);
362 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
363 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
364 /// offset could not be handled directly in MI, and return the left-over
365 /// portion by reference.
366 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
367 unsigned FrameReg, int &Offset,
368 const ARMBaseInstrInfo &TII);
370 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
371 unsigned FrameReg, int &Offset,
372 const ARMBaseInstrInfo &TII);
374 } // End llvm namespace