1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
28 class ARMBaseRegisterInfo;
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 // Return the non-pre/post incrementing version of 'Opc'. Return 0
39 // if there is not such an opcode.
40 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
42 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
43 MachineBasicBlock::iterator &MBBI,
44 LiveVariables *LV) const;
46 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
47 const ARMSubtarget &getSubtarget() const { return Subtarget; }
49 ScheduleHazardRecognizer *
50 CreateTargetHazardRecognizer(const TargetMachine *TM,
51 const ScheduleDAG *DAG) const;
53 ScheduleHazardRecognizer *
54 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
55 const ScheduleDAG *DAG) const;
58 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
59 MachineBasicBlock *&FBB,
60 SmallVectorImpl<MachineOperand> &Cond,
61 bool AllowModify = false) const;
62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
64 MachineBasicBlock *FBB,
65 const SmallVectorImpl<MachineOperand> &Cond,
69 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
71 // Predication support.
72 bool isPredicated(const MachineInstr *MI) const {
73 int PIdx = MI->findFirstPredOperandIdx();
74 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
94 virtual bool isPredicable(MachineInstr *MI) const;
96 /// GetInstSize - Returns the size of the specified MachineInstr.
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
126 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
132 virtual void reMaterialize(MachineBasicBlock &MBB,
133 MachineBasicBlock::iterator MI,
134 unsigned DestReg, unsigned SubIdx,
135 const MachineInstr *Orig,
136 const TargetRegisterInfo &TRI) const;
138 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
140 virtual bool produceSameValue(const MachineInstr *MI0,
141 const MachineInstr *MI1,
142 const MachineRegisterInfo *MRI) const;
144 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
145 /// determine if two loads are loading from the same base address. It should
146 /// only return true if the base pointers are the same and the only
147 /// differences between the two addresses is the offset. It also returns the
148 /// offsets by reference.
149 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
150 int64_t &Offset1, int64_t &Offset2)const;
152 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
153 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
154 /// should be scheduled togther. On some targets if two loads are loading from
155 /// addresses in the same cache line, it's better if they are scheduled
156 /// together. This function takes two integers that represent the load offsets
157 /// from the common base address. It returns true if it decides it's desirable
158 /// to schedule the two loads together. "NumLoads" is the number of loads that
159 /// have already been scheduled after Load1.
160 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
161 int64_t Offset1, int64_t Offset2,
162 unsigned NumLoads) const;
164 virtual bool isSchedulingBoundary(const MachineInstr *MI,
165 const MachineBasicBlock *MBB,
166 const MachineFunction &MF) const;
168 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
169 unsigned NumCycles, unsigned ExtraPredCycles,
170 const BranchProbability &Probability) const;
172 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
173 unsigned NumT, unsigned ExtraT,
174 MachineBasicBlock &FMBB,
175 unsigned NumF, unsigned ExtraF,
176 const BranchProbability &Probability) const;
178 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
180 const BranchProbability
181 &Probability) const {
182 return NumCycles == 1;
185 /// AnalyzeCompare - For a comparison instruction, return the source register
186 /// in SrcReg and the value it compares against in CmpValue. Return true if
187 /// the comparison instruction can be analyzed.
188 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
189 int &CmpMask, int &CmpValue) const;
191 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
192 /// that we can remove a "comparison with zero".
193 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
194 int CmpMask, int CmpValue,
195 const MachineRegisterInfo *MRI) const;
197 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
198 /// instruction, try to fold the immediate into the use instruction.
199 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
200 unsigned Reg, MachineRegisterInfo *MRI) const;
202 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
203 const MachineInstr *MI) const;
206 int getOperandLatency(const InstrItineraryData *ItinData,
207 const MachineInstr *DefMI, unsigned DefIdx,
208 const MachineInstr *UseMI, unsigned UseIdx) const;
210 int getOperandLatency(const InstrItineraryData *ItinData,
211 SDNode *DefNode, unsigned DefIdx,
212 SDNode *UseNode, unsigned UseIdx) const;
214 int getVLDMDefCycle(const InstrItineraryData *ItinData,
215 const MCInstrDesc &DefMCID,
217 unsigned DefIdx, unsigned DefAlign) const;
218 int getLDMDefCycle(const InstrItineraryData *ItinData,
219 const MCInstrDesc &DefMCID,
221 unsigned DefIdx, unsigned DefAlign) const;
222 int getVSTMUseCycle(const InstrItineraryData *ItinData,
223 const MCInstrDesc &UseMCID,
225 unsigned UseIdx, unsigned UseAlign) const;
226 int getSTMUseCycle(const InstrItineraryData *ItinData,
227 const MCInstrDesc &UseMCID,
229 unsigned UseIdx, unsigned UseAlign) const;
230 int getOperandLatency(const InstrItineraryData *ItinData,
231 const MCInstrDesc &DefMCID,
232 unsigned DefIdx, unsigned DefAlign,
233 const MCInstrDesc &UseMCID,
234 unsigned UseIdx, unsigned UseAlign) const;
236 int getInstrLatency(const InstrItineraryData *ItinData,
237 const MachineInstr *MI, unsigned *PredCost = 0) const;
239 int getInstrLatency(const InstrItineraryData *ItinData,
242 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
243 const MachineRegisterInfo *MRI,
244 const MachineInstr *DefMI, unsigned DefIdx,
245 const MachineInstr *UseMI, unsigned UseIdx) const;
246 bool hasLowDefLatency(const InstrItineraryData *ItinData,
247 const MachineInstr *DefMI, unsigned DefIdx) const;
250 /// Modeling special VFP / NEON fp MLA / MLS hazards.
252 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
254 DenseMap<unsigned, unsigned> MLxEntryMap;
256 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
257 /// stalls when scheduled together with fp MLA / MLS opcodes.
258 SmallSet<unsigned, 16> MLxHazardOpcodes;
261 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
263 bool isFpMLxInstruction(unsigned Opcode) const {
264 return MLxEntryMap.count(Opcode);
267 /// isFpMLxInstruction - This version also returns the multiply opcode and the
268 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
269 /// the MLX instructions with an extra lane operand.
270 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
271 unsigned &AddSubOpc, bool &NegAcc,
272 bool &HasLane) const;
274 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
275 /// will cause stalls when scheduled after (within 4-cycle window) a fp
276 /// MLA / MLS instruction.
277 bool canCauseFpMLxStall(unsigned Opcode) const {
278 return MLxHazardOpcodes.count(Opcode);
283 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
284 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
288 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
289 return MIB.addReg(0);
293 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
294 bool isDead = false) {
295 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
299 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
300 return MIB.addReg(0);
304 bool isUncondBranchOpcode(int Opc) {
305 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
309 bool isCondBranchOpcode(int Opc) {
310 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
314 bool isJumpTableBranchOpcode(int Opc) {
315 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
316 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
320 bool isIndirectBranchOpcode(int Opc) {
321 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
324 /// getInstrPredicate - If instruction is predicated, returns its predicate
325 /// condition, otherwise returns AL. It also returns the condition code
326 /// register by reference.
327 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
329 int getMatchingCondBranchOpcode(int Opc);
331 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
332 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
334 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
335 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
336 unsigned DestReg, unsigned BaseReg, int NumBytes,
337 ARMCC::CondCodes Pred, unsigned PredReg,
338 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
340 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
341 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
342 unsigned DestReg, unsigned BaseReg, int NumBytes,
343 ARMCC::CondCodes Pred, unsigned PredReg,
344 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
345 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
346 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
347 unsigned DestReg, unsigned BaseReg,
348 int NumBytes, const TargetInstrInfo &TII,
349 const ARMBaseRegisterInfo& MRI,
350 unsigned MIFlags = 0);
353 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
354 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
355 /// offset could not be handled directly in MI, and return the left-over
356 /// portion by reference.
357 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
358 unsigned FrameReg, int &Offset,
359 const ARMBaseInstrInfo &TII);
361 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
362 unsigned FrameReg, int &Offset,
363 const ARMBaseInstrInfo &TII);
365 } // End llvm namespace