1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
28 class ARMBaseRegisterInfo;
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 // Return whether the target has an explicit NOP encoding.
41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
42 // if there is not such an opcode.
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46 MachineBasicBlock::iterator &MBBI,
47 LiveVariables *LV) const;
49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
50 const ARMSubtarget &getSubtarget() const { return Subtarget; }
52 ScheduleHazardRecognizer *
53 CreateTargetHazardRecognizer(const TargetMachine *TM,
54 const ScheduleDAG *DAG) const;
56 ScheduleHazardRecognizer *
57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58 const ScheduleDAG *DAG) const;
61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify = false) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
74 // Predication support.
75 bool isPredicated(const MachineInstr *MI) const;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
94 virtual bool isPredicable(MachineInstr *MI) const;
96 /// GetInstSize - Returns the size of the specified MachineInstr.
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
128 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
134 virtual void reMaterialize(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator MI,
136 unsigned DestReg, unsigned SubIdx,
137 const MachineInstr *Orig,
138 const TargetRegisterInfo &TRI) const;
140 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
142 virtual bool produceSameValue(const MachineInstr *MI0,
143 const MachineInstr *MI1,
144 const MachineRegisterInfo *MRI) const;
146 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
147 /// determine if two loads are loading from the same base address. It should
148 /// only return true if the base pointers are the same and the only
149 /// differences between the two addresses is the offset. It also returns the
150 /// offsets by reference.
151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
152 int64_t &Offset1, int64_t &Offset2)const;
154 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
155 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
156 /// should be scheduled togther. On some targets if two loads are loading from
157 /// addresses in the same cache line, it's better if they are scheduled
158 /// together. This function takes two integers that represent the load offsets
159 /// from the common base address. It returns true if it decides it's desirable
160 /// to schedule the two loads together. "NumLoads" is the number of loads that
161 /// have already been scheduled after Load1.
162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
163 int64_t Offset1, int64_t Offset2,
164 unsigned NumLoads) const;
166 virtual bool isSchedulingBoundary(const MachineInstr *MI,
167 const MachineBasicBlock *MBB,
168 const MachineFunction &MF) const;
170 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
171 unsigned NumCycles, unsigned ExtraPredCycles,
172 const BranchProbability &Probability) const;
174 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
175 unsigned NumT, unsigned ExtraT,
176 MachineBasicBlock &FMBB,
177 unsigned NumF, unsigned ExtraF,
178 const BranchProbability &Probability) const;
180 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
182 const BranchProbability
183 &Probability) const {
184 return NumCycles == 1;
187 /// AnalyzeCompare - For a comparison instruction, return the source register
188 /// in SrcReg and the value it compares against in CmpValue. Return true if
189 /// the comparison instruction can be analyzed.
190 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
191 int &CmpMask, int &CmpValue) const;
193 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
194 /// that we can remove a "comparison with zero".
195 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
196 int CmpMask, int CmpValue,
197 const MachineRegisterInfo *MRI) const;
199 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
200 /// instruction, try to fold the immediate into the use instruction.
201 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
202 unsigned Reg, MachineRegisterInfo *MRI) const;
204 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
205 const MachineInstr *MI) const;
208 int getOperandLatency(const InstrItineraryData *ItinData,
209 const MachineInstr *DefMI, unsigned DefIdx,
210 const MachineInstr *UseMI, unsigned UseIdx) const;
212 int getOperandLatency(const InstrItineraryData *ItinData,
213 SDNode *DefNode, unsigned DefIdx,
214 SDNode *UseNode, unsigned UseIdx) const;
216 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
217 const MachineInstr *DefMI, unsigned DefIdx,
218 const MachineInstr *DepMI) const;
220 /// VFP/NEON execution domains.
221 std::pair<uint16_t, uint16_t>
222 getExecutionDomain(const MachineInstr *MI) const;
223 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
226 unsigned getInstBundleLength(const MachineInstr *MI) const;
228 int getVLDMDefCycle(const InstrItineraryData *ItinData,
229 const MCInstrDesc &DefMCID,
231 unsigned DefIdx, unsigned DefAlign) const;
232 int getLDMDefCycle(const InstrItineraryData *ItinData,
233 const MCInstrDesc &DefMCID,
235 unsigned DefIdx, unsigned DefAlign) const;
236 int getVSTMUseCycle(const InstrItineraryData *ItinData,
237 const MCInstrDesc &UseMCID,
239 unsigned UseIdx, unsigned UseAlign) const;
240 int getSTMUseCycle(const InstrItineraryData *ItinData,
241 const MCInstrDesc &UseMCID,
243 unsigned UseIdx, unsigned UseAlign) const;
244 int getOperandLatency(const InstrItineraryData *ItinData,
245 const MCInstrDesc &DefMCID,
246 unsigned DefIdx, unsigned DefAlign,
247 const MCInstrDesc &UseMCID,
248 unsigned UseIdx, unsigned UseAlign) const;
250 int getInstrLatency(const InstrItineraryData *ItinData,
251 const MachineInstr *MI, unsigned *PredCost = 0) const;
253 int getInstrLatency(const InstrItineraryData *ItinData,
256 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
257 const MachineRegisterInfo *MRI,
258 const MachineInstr *DefMI, unsigned DefIdx,
259 const MachineInstr *UseMI, unsigned UseIdx) const;
260 bool hasLowDefLatency(const InstrItineraryData *ItinData,
261 const MachineInstr *DefMI, unsigned DefIdx) const;
263 /// verifyInstruction - Perform target specific instruction verification.
264 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
267 /// Modeling special VFP / NEON fp MLA / MLS hazards.
269 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
271 DenseMap<unsigned, unsigned> MLxEntryMap;
273 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
274 /// stalls when scheduled together with fp MLA / MLS opcodes.
275 SmallSet<unsigned, 16> MLxHazardOpcodes;
278 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
280 bool isFpMLxInstruction(unsigned Opcode) const {
281 return MLxEntryMap.count(Opcode);
284 /// isFpMLxInstruction - This version also returns the multiply opcode and the
285 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
286 /// the MLX instructions with an extra lane operand.
287 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
288 unsigned &AddSubOpc, bool &NegAcc,
289 bool &HasLane) const;
291 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
292 /// will cause stalls when scheduled after (within 4-cycle window) a fp
293 /// MLA / MLS instruction.
294 bool canCauseFpMLxStall(unsigned Opcode) const {
295 return MLxHazardOpcodes.count(Opcode);
300 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
301 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
305 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
306 return MIB.addReg(0);
310 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
311 bool isDead = false) {
312 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
316 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
317 return MIB.addReg(0);
321 bool isUncondBranchOpcode(int Opc) {
322 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
326 bool isCondBranchOpcode(int Opc) {
327 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
331 bool isJumpTableBranchOpcode(int Opc) {
332 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
333 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
337 bool isIndirectBranchOpcode(int Opc) {
338 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
341 /// getInstrPredicate - If instruction is predicated, returns its predicate
342 /// condition, otherwise returns AL. It also returns the condition code
343 /// register by reference.
344 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
346 int getMatchingCondBranchOpcode(int Opc);
349 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
350 /// the instruction is encoded with an 'S' bit is determined by the optional
351 /// CPSR def operand.
352 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
354 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
355 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
357 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
358 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
359 unsigned DestReg, unsigned BaseReg, int NumBytes,
360 ARMCC::CondCodes Pred, unsigned PredReg,
361 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
363 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
365 unsigned DestReg, unsigned BaseReg, int NumBytes,
366 ARMCC::CondCodes Pred, unsigned PredReg,
367 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
368 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
370 unsigned DestReg, unsigned BaseReg,
371 int NumBytes, const TargetInstrInfo &TII,
372 const ARMBaseRegisterInfo& MRI,
373 unsigned MIFlags = 0);
376 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
377 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
378 /// offset could not be handled directly in MI, and return the left-over
379 /// portion by reference.
380 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
381 unsigned FrameReg, int &Offset,
382 const ARMBaseInstrInfo &TII);
384 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
385 unsigned FrameReg, int &Offset,
386 const ARMBaseInstrInfo &TII);
388 } // End llvm namespace