1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
64 IndexModeMask = 3 << IndexModeShift,
68 //===------------------------------------------------------------------===//
69 // Instruction encoding formats.
72 FormMask = 0x3f << FormShift,
74 // Pseudo instructions
75 Pseudo = 0 << FormShift,
77 // Multiply instructions
78 MulFrm = 1 << FormShift,
80 // Branch instructions
81 BrFrm = 2 << FormShift,
82 BrMiscFrm = 3 << FormShift,
84 // Data Processing instructions
85 DPFrm = 4 << FormShift,
86 DPSoRegFrm = 5 << FormShift,
89 LdFrm = 6 << FormShift,
90 StFrm = 7 << FormShift,
91 LdMiscFrm = 8 << FormShift,
92 StMiscFrm = 9 << FormShift,
93 LdStMulFrm = 10 << FormShift,
95 // Miscellaneous arithmetic instructions
96 ArithMiscFrm = 11 << FormShift,
98 // Extend instructions
99 ExtFrm = 12 << FormShift,
102 VFPUnaryFrm = 13 << FormShift,
103 VFPBinaryFrm = 14 << FormShift,
104 VFPConv1Frm = 15 << FormShift,
105 VFPConv2Frm = 16 << FormShift,
106 VFPConv3Frm = 17 << FormShift,
107 VFPConv4Frm = 18 << FormShift,
108 VFPConv5Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
114 ThumbFrm = 23 << FormShift,
117 NEONFrm = 24 << FormShift,
118 NEONGetLnFrm = 25 << FormShift,
119 NEONSetLnFrm = 26 << FormShift,
120 NEONDupFrm = 27 << FormShift,
122 //===------------------------------------------------------------------===//
125 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126 // it doesn't have a Rn operand.
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
133 //===------------------------------------------------------------------===//
136 DomainMask = 3 << DomainShift,
137 DomainGeneral = 0 << DomainShift,
138 DomainVFP = 1 << DomainShift,
139 DomainNEON = 2 << DomainShift,
141 //===------------------------------------------------------------------===//
142 // Field shifts - such shifts are used to set field while generating
143 // machine instructions.
166 /// Target Operand Flag enum.
168 //===------------------------------------------------------------------===//
169 // ARM Specific MachineOperand flags.
173 /// MO_LO16 - On a symbol operand, this represents a relocation containing
174 /// lower 16 bit of the address. Used only via movw instruction.
177 /// MO_HI16 - On a symbol operand, this represents a relocation containing
178 /// higher 16 bit of the address. Used only via movt instruction.
183 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
184 const ARMSubtarget& Subtarget;
186 // Can be only subclassed.
187 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
189 // Return the non-pre/post incrementing version of 'Opc'. Return 0
190 // if there is not such an opcode.
191 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
193 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
194 MachineBasicBlock::iterator &MBBI,
195 LiveVariables *LV) const;
197 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
198 const ARMSubtarget &getSubtarget() const { return Subtarget; }
201 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
202 MachineBasicBlock *&FBB,
203 SmallVectorImpl<MachineOperand> &Cond,
204 bool AllowModify) const;
205 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
206 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
207 MachineBasicBlock *FBB,
208 const SmallVectorImpl<MachineOperand> &Cond) const;
211 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
213 // Predication support.
214 bool isPredicated(const MachineInstr *MI) const {
215 int PIdx = MI->findFirstPredOperandIdx();
216 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
219 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
220 int PIdx = MI->findFirstPredOperandIdx();
221 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
226 bool PredicateInstruction(MachineInstr *MI,
227 const SmallVectorImpl<MachineOperand> &Pred) const;
230 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
231 const SmallVectorImpl<MachineOperand> &Pred2) const;
233 virtual bool DefinesPredicate(MachineInstr *MI,
234 std::vector<MachineOperand> &Pred) const;
236 virtual bool isPredicable(MachineInstr *MI) const;
238 /// GetInstSize - Returns the size of the specified MachineInstr.
240 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
242 /// Return true if the instruction is a register to register move and return
243 /// the source and dest operands and their sub-register indices by reference.
244 virtual bool isMoveInstr(const MachineInstr &MI,
245 unsigned &SrcReg, unsigned &DstReg,
246 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
248 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
249 int &FrameIndex) const;
250 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
251 int &FrameIndex) const;
253 virtual bool copyRegToReg(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator I,
255 unsigned DestReg, unsigned SrcReg,
256 const TargetRegisterClass *DestRC,
257 const TargetRegisterClass *SrcRC) const;
259 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
260 MachineBasicBlock::iterator MBBI,
261 unsigned SrcReg, bool isKill, int FrameIndex,
262 const TargetRegisterClass *RC) const;
264 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator MBBI,
266 unsigned DestReg, int FrameIndex,
267 const TargetRegisterClass *RC) const;
269 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
270 const SmallVectorImpl<unsigned> &Ops) const;
272 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
274 const SmallVectorImpl<unsigned> &Ops,
275 int FrameIndex) const;
277 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
279 const SmallVectorImpl<unsigned> &Ops,
280 MachineInstr* LoadMI) const;
282 virtual void reMaterialize(MachineBasicBlock &MBB,
283 MachineBasicBlock::iterator MI,
284 unsigned DestReg, unsigned SubIdx,
285 const MachineInstr *Orig,
286 const TargetRegisterInfo *TRI) const;
288 virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
289 const MachineRegisterInfo *MRI) const;
293 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
294 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
298 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
299 return MIB.addReg(0);
303 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
304 bool isDead = false) {
305 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
309 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
310 return MIB.addReg(0);
314 bool isUncondBranchOpcode(int Opc) {
315 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
319 bool isCondBranchOpcode(int Opc) {
320 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
324 bool isJumpTableBranchOpcode(int Opc) {
325 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
326 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
330 bool isIndirectBranchOpcode(int Opc) {
331 return Opc == ARM::BRIND || Opc == ARM::tBRIND;
334 /// getInstrPredicate - If instruction is predicated, returns its predicate
335 /// condition, otherwise returns AL. It also returns the condition code
336 /// register by reference.
337 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
339 int getMatchingCondBranchOpcode(int Opc);
341 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
342 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
344 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
345 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
346 unsigned DestReg, unsigned BaseReg, int NumBytes,
347 ARMCC::CondCodes Pred, unsigned PredReg,
348 const ARMBaseInstrInfo &TII);
350 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
351 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
352 unsigned DestReg, unsigned BaseReg, int NumBytes,
353 ARMCC::CondCodes Pred, unsigned PredReg,
354 const ARMBaseInstrInfo &TII);
357 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
358 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
359 /// offset could not be handled directly in MI, and return the left-over
360 /// portion by reference.
361 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
362 unsigned FrameReg, int &Offset,
363 const ARMBaseInstrInfo &TII);
365 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
366 unsigned FrameReg, int &Offset,
367 const ARMBaseInstrInfo &TII);
369 } // End llvm namespace