1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CodeGen.h"
22 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
29 class ARMBaseRegisterInfo;
31 class ARMBaseInstrInfo : public ARMGenInstrInfo {
32 const ARMSubtarget &Subtarget;
35 // Can be only subclassed.
36 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
39 unsigned LoadImmOpc, unsigned LoadOpc,
40 Reloc::Model RM) const;
42 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
44 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
45 /// the list is modeled as <Reg:SubReg, SubIdx>.
46 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
48 /// - vreg1:sub1, sub0
51 /// \returns true if it is possible to build such an input sequence
52 /// with the pair \p MI, \p DefIdx. False otherwise.
54 /// \pre MI.isRegSequenceLike().
55 bool getRegSequenceLikeInputs(
56 const MachineInstr &MI, unsigned DefIdx,
57 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
59 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
61 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
62 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
63 /// - vreg1:sub1, sub0
65 /// \returns true if it is possible to build such an input sequence
66 /// with the pair \p MI, \p DefIdx. False otherwise.
68 /// \pre MI.isExtractSubregLike().
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
70 RegSubRegPairAndIdx &InputReg) const override;
72 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
74 /// \p [out] BaseReg and \p [out] InsertedReg contain
75 /// the equivalent inputs of INSERT_SUBREG.
76 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
77 /// - BaseReg: vreg0:sub0
78 /// - InsertedReg: vreg1:sub1, sub3
80 /// \returns true if it is possible to build such an input sequence
81 /// with the pair \p MI, \p DefIdx. False otherwise.
83 /// \pre MI.isInsertSubregLike().
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
86 RegSubRegPair &BaseReg,
87 RegSubRegPairAndIdx &InsertedReg) const override;
90 // Return whether the target has an explicit NOP encoding.
93 // Return the non-pre/post incrementing version of 'Opc'. Return 0
94 // if there is not such an opcode.
95 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
97 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
98 MachineBasicBlock::iterator &MBBI,
99 LiveVariables *LV) const override;
101 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
102 const ARMSubtarget &getSubtarget() const { return Subtarget; }
104 ScheduleHazardRecognizer *
105 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
106 const ScheduleDAG *DAG) const override;
108 ScheduleHazardRecognizer *
109 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
110 const ScheduleDAG *DAG) const override;
113 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
114 MachineBasicBlock *&FBB,
115 SmallVectorImpl<MachineOperand> &Cond,
116 bool AllowModify = false) const override;
117 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
118 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
119 MachineBasicBlock *FBB,
120 const SmallVectorImpl<MachineOperand> &Cond,
121 DebugLoc DL) const override;
124 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
126 // Predication support.
127 bool isPredicated(const MachineInstr *MI) const override;
129 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
130 int PIdx = MI->findFirstPredOperandIdx();
131 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
135 bool PredicateInstruction(MachineInstr *MI,
136 const SmallVectorImpl<MachineOperand> &Pred) const override;
138 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
139 const SmallVectorImpl<MachineOperand> &Pred2) const override;
141 bool DefinesPredicate(MachineInstr *MI,
142 std::vector<MachineOperand> &Pred) const override;
144 bool isPredicable(MachineInstr *MI) const override;
146 /// GetInstSize - Returns the size of the specified MachineInstr.
148 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
150 unsigned isLoadFromStackSlot(const MachineInstr *MI,
151 int &FrameIndex) const override;
152 unsigned isStoreToStackSlot(const MachineInstr *MI,
153 int &FrameIndex) const override;
154 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
155 int &FrameIndex) const override;
156 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
157 int &FrameIndex) const override;
159 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
160 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
161 bool KillSrc) const override;
163 void storeRegToStackSlot(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator MBBI,
165 unsigned SrcReg, bool isKill, int FrameIndex,
166 const TargetRegisterClass *RC,
167 const TargetRegisterInfo *TRI) const override;
169 void loadRegFromStackSlot(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MBBI,
171 unsigned DestReg, int FrameIndex,
172 const TargetRegisterClass *RC,
173 const TargetRegisterInfo *TRI) const override;
175 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
177 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
178 unsigned DestReg, unsigned SubIdx,
179 const MachineInstr *Orig,
180 const TargetRegisterInfo &TRI) const override;
182 MachineInstr *duplicate(MachineInstr *Orig,
183 MachineFunction &MF) const override;
185 MachineInstr *commuteInstruction(MachineInstr*,
186 bool=false) const override;
188 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
189 unsigned SubIdx, unsigned State,
190 const TargetRegisterInfo *TRI) const;
192 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
193 const MachineRegisterInfo *MRI) const override;
195 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
196 /// determine if two loads are loading from the same base address. It should
197 /// only return true if the base pointers are the same and the only
198 /// differences between the two addresses is the offset. It also returns the
199 /// offsets by reference.
200 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
201 int64_t &Offset2) const override;
203 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
204 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
205 /// should be scheduled togther. On some targets if two loads are loading from
206 /// addresses in the same cache line, it's better if they are scheduled
207 /// together. This function takes two integers that represent the load offsets
208 /// from the common base address. It returns true if it decides it's desirable
209 /// to schedule the two loads together. "NumLoads" is the number of loads that
210 /// have already been scheduled after Load1.
211 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
212 int64_t Offset1, int64_t Offset2,
213 unsigned NumLoads) const override;
215 bool isSchedulingBoundary(const MachineInstr *MI,
216 const MachineBasicBlock *MBB,
217 const MachineFunction &MF) const override;
219 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
220 unsigned NumCycles, unsigned ExtraPredCycles,
221 const BranchProbability &Probability) const override;
223 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
224 unsigned ExtraT, MachineBasicBlock &FMBB,
225 unsigned NumF, unsigned ExtraF,
226 const BranchProbability &Probability) const override;
228 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
229 const BranchProbability &Probability) const override {
230 return NumCycles == 1;
233 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
234 MachineBasicBlock &FMBB) const override;
236 /// analyzeCompare - For a comparison instruction, return the source registers
237 /// in SrcReg and SrcReg2 if having two register operands, and the value it
238 /// compares against in CmpValue. Return true if the comparison instruction
240 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
241 unsigned &SrcReg2, int &CmpMask,
242 int &CmpValue) const override;
244 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
245 /// that we can remove a "comparison with zero"; Remove a redundant CMP
246 /// instruction if the flags can be updated in the same way by an earlier
247 /// instruction such as SUB.
248 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
249 unsigned SrcReg2, int CmpMask, int CmpValue,
250 const MachineRegisterInfo *MRI) const override;
252 bool analyzeSelect(const MachineInstr *MI,
253 SmallVectorImpl<MachineOperand> &Cond,
254 unsigned &TrueOp, unsigned &FalseOp,
255 bool &Optimizable) const override;
257 MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
259 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
260 /// instruction, try to fold the immediate into the use instruction.
261 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
262 unsigned Reg, MachineRegisterInfo *MRI) const override;
264 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
265 const MachineInstr *MI) const override;
267 int getOperandLatency(const InstrItineraryData *ItinData,
268 const MachineInstr *DefMI, unsigned DefIdx,
269 const MachineInstr *UseMI,
270 unsigned UseIdx) const override;
271 int getOperandLatency(const InstrItineraryData *ItinData,
272 SDNode *DefNode, unsigned DefIdx,
273 SDNode *UseNode, unsigned UseIdx) const override;
275 /// VFP/NEON execution domains.
276 std::pair<uint16_t, uint16_t>
277 getExecutionDomain(const MachineInstr *MI) const override;
278 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
280 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
281 const TargetRegisterInfo*) const override;
282 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
283 const TargetRegisterInfo *TRI) const override;
286 getUnconditionalBranch(MCInst &Branch,
287 const MCSymbolRefExpr *BranchTarget) const override;
289 void getTrap(MCInst &MI) const override;
291 /// Get the number of addresses by LDM or VLDM or zero for unknown.
292 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
295 unsigned getInstBundleLength(const MachineInstr *MI) const;
297 int getVLDMDefCycle(const InstrItineraryData *ItinData,
298 const MCInstrDesc &DefMCID,
300 unsigned DefIdx, unsigned DefAlign) const;
301 int getLDMDefCycle(const InstrItineraryData *ItinData,
302 const MCInstrDesc &DefMCID,
304 unsigned DefIdx, unsigned DefAlign) const;
305 int getVSTMUseCycle(const InstrItineraryData *ItinData,
306 const MCInstrDesc &UseMCID,
308 unsigned UseIdx, unsigned UseAlign) const;
309 int getSTMUseCycle(const InstrItineraryData *ItinData,
310 const MCInstrDesc &UseMCID,
312 unsigned UseIdx, unsigned UseAlign) const;
313 int getOperandLatency(const InstrItineraryData *ItinData,
314 const MCInstrDesc &DefMCID,
315 unsigned DefIdx, unsigned DefAlign,
316 const MCInstrDesc &UseMCID,
317 unsigned UseIdx, unsigned UseAlign) const;
319 unsigned getPredicationCost(const MachineInstr *MI) const override;
321 unsigned getInstrLatency(const InstrItineraryData *ItinData,
322 const MachineInstr *MI,
323 unsigned *PredCost = nullptr) const override;
325 int getInstrLatency(const InstrItineraryData *ItinData,
326 SDNode *Node) const override;
328 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
329 const MachineRegisterInfo *MRI,
330 const MachineInstr *DefMI, unsigned DefIdx,
331 const MachineInstr *UseMI,
332 unsigned UseIdx) const override;
333 bool hasLowDefLatency(const InstrItineraryData *ItinData,
334 const MachineInstr *DefMI,
335 unsigned DefIdx) const override;
337 /// verifyInstruction - Perform target specific instruction verification.
338 bool verifyInstruction(const MachineInstr *MI,
339 StringRef &ErrInfo) const override;
341 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
342 Reloc::Model RM) const = 0;
345 /// Modeling special VFP / NEON fp MLA / MLS hazards.
347 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
349 DenseMap<unsigned, unsigned> MLxEntryMap;
351 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
352 /// stalls when scheduled together with fp MLA / MLS opcodes.
353 SmallSet<unsigned, 16> MLxHazardOpcodes;
356 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
358 bool isFpMLxInstruction(unsigned Opcode) const {
359 return MLxEntryMap.count(Opcode);
362 /// isFpMLxInstruction - This version also returns the multiply opcode and the
363 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
364 /// the MLX instructions with an extra lane operand.
365 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
366 unsigned &AddSubOpc, bool &NegAcc,
367 bool &HasLane) const;
369 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
370 /// will cause stalls when scheduled after (within 4-cycle window) a fp
371 /// MLA / MLS instruction.
372 bool canCauseFpMLxStall(unsigned Opcode) const {
373 return MLxHazardOpcodes.count(Opcode);
376 /// Returns true if the instruction has a shift by immediate that can be
377 /// executed in one cycle less.
378 bool isSwiftFastImmShift(const MachineInstr *MI) const;
382 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
383 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
387 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
388 return MIB.addReg(0);
392 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
393 bool isDead = false) {
394 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
398 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
399 return MIB.addReg(0);
403 bool isUncondBranchOpcode(int Opc) {
404 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
408 bool isCondBranchOpcode(int Opc) {
409 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
413 bool isJumpTableBranchOpcode(int Opc) {
414 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
415 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
419 bool isIndirectBranchOpcode(int Opc) {
420 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
423 static inline bool isPopOpcode(int Opc) {
424 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
425 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
426 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
429 static inline bool isPushOpcode(int Opc) {
430 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
431 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
434 /// getInstrPredicate - If instruction is predicated, returns its predicate
435 /// condition, otherwise returns AL. It also returns the condition code
436 /// register by reference.
437 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
439 int getMatchingCondBranchOpcode(int Opc);
441 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
442 /// opcode of the SSA instruction representing the conditional MI.
443 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
445 const MachineRegisterInfo &MRI);
447 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
448 /// the instruction is encoded with an 'S' bit is determined by the optional
449 /// CPSR def operand.
450 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
452 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
453 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
455 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
456 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
457 unsigned DestReg, unsigned BaseReg, int NumBytes,
458 ARMCC::CondCodes Pred, unsigned PredReg,
459 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
461 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
463 unsigned DestReg, unsigned BaseReg, int NumBytes,
464 ARMCC::CondCodes Pred, unsigned PredReg,
465 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
466 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
467 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
468 unsigned DestReg, unsigned BaseReg,
469 int NumBytes, const TargetInstrInfo &TII,
470 const ARMBaseRegisterInfo& MRI,
471 unsigned MIFlags = 0);
473 /// Tries to add registers to the reglist of a given base-updating
474 /// push/pop instruction to adjust the stack by an additional
475 /// NumBytes. This can save a few bytes per function in code-size, but
476 /// obviously generates more memory traffic. As such, it only takes
477 /// effect in functions being optimised for size.
478 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
479 MachineFunction &MF, MachineInstr *MI,
482 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
483 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
484 /// offset could not be handled directly in MI, and return the left-over
485 /// portion by reference.
486 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
487 unsigned FrameReg, int &Offset,
488 const ARMBaseInstrInfo &TII);
490 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
491 unsigned FrameReg, int &Offset,
492 const ARMBaseInstrInfo &TII);
494 } // End llvm namespace