1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Target/TargetInstrInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
62 // and store ops only. Generic "updating" flag is used for ld/st multiple.
64 IndexModeMask = 3 << IndexModeShift,
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x3f << FormShift,
75 // Pseudo instructions
76 Pseudo = 0 << FormShift,
78 // Multiply instructions
79 MulFrm = 1 << FormShift,
81 // Branch instructions
82 BrFrm = 2 << FormShift,
83 BrMiscFrm = 3 << FormShift,
85 // Data Processing instructions
86 DPFrm = 4 << FormShift,
87 DPSoRegFrm = 5 << FormShift,
90 LdFrm = 6 << FormShift,
91 StFrm = 7 << FormShift,
92 LdMiscFrm = 8 << FormShift,
93 StMiscFrm = 9 << FormShift,
94 LdStMulFrm = 10 << FormShift,
96 LdStExFrm = 11 << FormShift,
98 // Miscellaneous arithmetic instructions
99 ArithMiscFrm = 12 << FormShift,
101 // Extend instructions
102 ExtFrm = 13 << FormShift,
105 VFPUnaryFrm = 14 << FormShift,
106 VFPBinaryFrm = 15 << FormShift,
107 VFPConv1Frm = 16 << FormShift,
108 VFPConv2Frm = 17 << FormShift,
109 VFPConv3Frm = 18 << FormShift,
110 VFPConv4Frm = 19 << FormShift,
111 VFPConv5Frm = 20 << FormShift,
112 VFPLdStFrm = 21 << FormShift,
113 VFPLdStMulFrm = 22 << FormShift,
114 VFPMiscFrm = 23 << FormShift,
117 ThumbFrm = 24 << FormShift,
119 // Miscelleaneous format
120 MiscFrm = 25 << FormShift,
123 NGetLnFrm = 26 << FormShift,
124 NSetLnFrm = 27 << FormShift,
125 NDupFrm = 28 << FormShift,
126 NLdStFrm = 29 << FormShift,
127 N1RegModImmFrm= 30 << FormShift,
128 N2RegFrm = 31 << FormShift,
129 NVCVTFrm = 32 << FormShift,
130 NVDupLnFrm = 33 << FormShift,
131 N2RegVShLFrm = 34 << FormShift,
132 N2RegVShRFrm = 35 << FormShift,
133 N3RegFrm = 36 << FormShift,
134 N3RegVShFrm = 37 << FormShift,
135 NVExtFrm = 38 << FormShift,
136 NVMulSLFrm = 39 << FormShift,
137 NVTBLFrm = 40 << FormShift,
139 //===------------------------------------------------------------------===//
142 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
143 // it doesn't have a Rn operand.
146 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
147 // a 16-bit Thumb instruction if certain conditions are met.
148 Xform16Bit = 1 << 16,
150 //===------------------------------------------------------------------===//
153 DomainMask = 3 << DomainShift,
154 DomainGeneral = 0 << DomainShift,
155 DomainVFP = 1 << DomainShift,
156 DomainNEON = 2 << DomainShift,
158 //===------------------------------------------------------------------===//
159 // Field shifts - such shifts are used to set field while generating
160 // machine instructions.
183 /// Target Operand Flag enum.
185 //===------------------------------------------------------------------===//
186 // ARM Specific MachineOperand flags.
190 /// MO_LO16 - On a symbol operand, this represents a relocation containing
191 /// lower 16 bit of the address. Used only via movw instruction.
194 /// MO_HI16 - On a symbol operand, this represents a relocation containing
195 /// higher 16 bit of the address. Used only via movt instruction.
200 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
201 const ARMSubtarget& Subtarget;
203 // Can be only subclassed.
204 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
206 // Return the non-pre/post incrementing version of 'Opc'. Return 0
207 // if there is not such an opcode.
208 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
210 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
211 MachineBasicBlock::iterator &MBBI,
212 LiveVariables *LV) const;
214 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
215 const ARMSubtarget &getSubtarget() const { return Subtarget; }
217 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
218 MachineBasicBlock::iterator MI,
219 const std::vector<CalleeSavedInfo> &CSI,
220 const TargetRegisterInfo *TRI) const;
223 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
224 MachineBasicBlock *&FBB,
225 SmallVectorImpl<MachineOperand> &Cond,
226 bool AllowModify) const;
227 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
228 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
229 MachineBasicBlock *FBB,
230 const SmallVectorImpl<MachineOperand> &Cond,
234 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
236 // Predication support.
237 bool isPredicated(const MachineInstr *MI) const {
238 int PIdx = MI->findFirstPredOperandIdx();
239 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
242 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
243 int PIdx = MI->findFirstPredOperandIdx();
244 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
249 bool PredicateInstruction(MachineInstr *MI,
250 const SmallVectorImpl<MachineOperand> &Pred) const;
253 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
254 const SmallVectorImpl<MachineOperand> &Pred2) const;
256 virtual bool DefinesPredicate(MachineInstr *MI,
257 std::vector<MachineOperand> &Pred) const;
259 virtual bool isPredicable(MachineInstr *MI) const;
261 /// GetInstSize - Returns the size of the specified MachineInstr.
263 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
265 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
266 int &FrameIndex) const;
267 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
268 int &FrameIndex) const;
270 virtual void copyPhysReg(MachineBasicBlock &MBB,
271 MachineBasicBlock::iterator I, DebugLoc DL,
272 unsigned DestReg, unsigned SrcReg,
275 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator MBBI,
277 unsigned SrcReg, bool isKill, int FrameIndex,
278 const TargetRegisterClass *RC,
279 const TargetRegisterInfo *TRI) const;
281 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator MBBI,
283 unsigned DestReg, int FrameIndex,
284 const TargetRegisterClass *RC,
285 const TargetRegisterInfo *TRI) const;
287 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
293 virtual void reMaterialize(MachineBasicBlock &MBB,
294 MachineBasicBlock::iterator MI,
295 unsigned DestReg, unsigned SubIdx,
296 const MachineInstr *Orig,
297 const TargetRegisterInfo &TRI) const;
299 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
301 virtual bool produceSameValue(const MachineInstr *MI0,
302 const MachineInstr *MI1) const;
304 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
305 /// determine if two loads are loading from the same base address. It should
306 /// only return true if the base pointers are the same and the only
307 /// differences between the two addresses is the offset. It also returns the
308 /// offsets by reference.
309 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
310 int64_t &Offset1, int64_t &Offset2)const;
312 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
313 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
314 /// be scheduled togther. On some targets if two loads are loading from
315 /// addresses in the same cache line, it's better if they are scheduled
316 /// together. This function takes two integers that represent the load offsets
317 /// from the common base address. It returns true if it decides it's desirable
318 /// to schedule the two loads together. "NumLoads" is the number of loads that
319 /// have already been scheduled after Load1.
320 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
321 int64_t Offset1, int64_t Offset2,
322 unsigned NumLoads) const;
324 virtual bool isSchedulingBoundary(const MachineInstr *MI,
325 const MachineBasicBlock *MBB,
326 const MachineFunction &MF) const;
328 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
329 unsigned NumInstrs) const;
331 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
332 MachineBasicBlock &FMBB,unsigned NumF) const;
334 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
335 unsigned NumInstrs) const {
336 return NumInstrs && NumInstrs == 1;
341 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
342 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
346 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
347 return MIB.addReg(0);
351 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
352 bool isDead = false) {
353 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
357 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
358 return MIB.addReg(0);
362 bool isUncondBranchOpcode(int Opc) {
363 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
367 bool isCondBranchOpcode(int Opc) {
368 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
372 bool isJumpTableBranchOpcode(int Opc) {
373 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
374 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
378 bool isIndirectBranchOpcode(int Opc) {
379 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
382 /// getInstrPredicate - If instruction is predicated, returns its predicate
383 /// condition, otherwise returns AL. It also returns the condition code
384 /// register by reference.
385 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
387 int getMatchingCondBranchOpcode(int Opc);
389 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
390 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
392 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
394 unsigned DestReg, unsigned BaseReg, int NumBytes,
395 ARMCC::CondCodes Pred, unsigned PredReg,
396 const ARMBaseInstrInfo &TII);
398 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
399 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
400 unsigned DestReg, unsigned BaseReg, int NumBytes,
401 ARMCC::CondCodes Pred, unsigned PredReg,
402 const ARMBaseInstrInfo &TII);
405 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
406 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
407 /// offset could not be handled directly in MI, and return the left-over
408 /// portion by reference.
409 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
410 unsigned FrameReg, int &Offset,
411 const ARMBaseInstrInfo &TII);
413 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
414 unsigned FrameReg, int &Offset,
415 const ARMBaseInstrInfo &TII);
417 } // End llvm namespace