1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CodeGen.h"
22 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
29 class ARMBaseRegisterInfo;
31 class ARMBaseInstrInfo : public ARMGenInstrInfo {
32 const ARMSubtarget &Subtarget;
35 // Can be only subclassed.
36 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
39 unsigned LoadImmOpc, unsigned LoadOpc,
40 Reloc::Model RM) const;
42 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
44 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
45 /// the list is modeled as <Reg:SubReg, SubIdx>.
46 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
48 /// - vreg1:sub1, sub0
51 /// \returns true if it is possible to build such an input sequence
52 /// with the pair \p MI, \p DefIdx. False otherwise.
54 /// \pre MI.isRegSequenceLike().
55 bool getRegSequenceLikeInputs(
56 const MachineInstr &MI, unsigned DefIdx,
57 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
59 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
61 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
62 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
63 /// - vreg1:sub1, sub0
65 /// \returns true if it is possible to build such an input sequence
66 /// with the pair \p MI, \p DefIdx. False otherwise.
68 /// \pre MI.isExtractSubregLike().
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
70 RegSubRegPairAndIdx &InputReg) const override;
72 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
74 /// \p [out] BaseReg and \p [out] InsertedReg contain
75 /// the equivalent inputs of INSERT_SUBREG.
76 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
77 /// - BaseReg: vreg0:sub0
78 /// - InsertedReg: vreg1:sub1, sub3
80 /// \returns true if it is possible to build such an input sequence
81 /// with the pair \p MI, \p DefIdx. False otherwise.
83 /// \pre MI.isInsertSubregLike().
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
86 RegSubRegPair &BaseReg,
87 RegSubRegPairAndIdx &InsertedReg) const override;
90 // Return whether the target has an explicit NOP encoding.
93 // Return the non-pre/post incrementing version of 'Opc'. Return 0
94 // if there is not such an opcode.
95 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
97 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
98 MachineBasicBlock::iterator &MBBI,
99 LiveVariables *LV) const override;
101 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
102 const ARMSubtarget &getSubtarget() const { return Subtarget; }
104 ScheduleHazardRecognizer *
105 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
106 const ScheduleDAG *DAG) const override;
108 ScheduleHazardRecognizer *
109 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
110 const ScheduleDAG *DAG) const override;
113 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
114 MachineBasicBlock *&FBB,
115 SmallVectorImpl<MachineOperand> &Cond,
116 bool AllowModify = false) const override;
117 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
118 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
119 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
120 DebugLoc DL) const override;
123 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
125 // Predication support.
126 bool isPredicated(const MachineInstr *MI) const override;
128 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
129 int PIdx = MI->findFirstPredOperandIdx();
130 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
134 bool PredicateInstruction(MachineInstr *MI,
135 ArrayRef<MachineOperand> Pred) const override;
137 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
138 ArrayRef<MachineOperand> Pred2) const override;
140 bool DefinesPredicate(MachineInstr *MI,
141 std::vector<MachineOperand> &Pred) const override;
143 bool isPredicable(MachineInstr *MI) const override;
145 /// GetInstSize - Returns the size of the specified MachineInstr.
147 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
149 unsigned isLoadFromStackSlot(const MachineInstr *MI,
150 int &FrameIndex) const override;
151 unsigned isStoreToStackSlot(const MachineInstr *MI,
152 int &FrameIndex) const override;
153 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
154 int &FrameIndex) const override;
155 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
156 int &FrameIndex) const override;
158 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
159 unsigned SrcReg, bool KillSrc,
160 const ARMSubtarget &Subtarget) const;
161 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
162 unsigned DestReg, bool KillSrc,
163 const ARMSubtarget &Subtarget) const;
165 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
166 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
167 bool KillSrc) const override;
169 void storeRegToStackSlot(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MBBI,
171 unsigned SrcReg, bool isKill, int FrameIndex,
172 const TargetRegisterClass *RC,
173 const TargetRegisterInfo *TRI) const override;
175 void loadRegFromStackSlot(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator MBBI,
177 unsigned DestReg, int FrameIndex,
178 const TargetRegisterClass *RC,
179 const TargetRegisterInfo *TRI) const override;
181 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
183 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
184 unsigned DestReg, unsigned SubIdx,
185 const MachineInstr *Orig,
186 const TargetRegisterInfo &TRI) const override;
188 MachineInstr *duplicate(MachineInstr *Orig,
189 MachineFunction &MF) const override;
191 MachineInstr *commuteInstruction(MachineInstr*,
192 bool=false) const override;
194 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
195 unsigned SubIdx, unsigned State,
196 const TargetRegisterInfo *TRI) const;
198 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
199 const MachineRegisterInfo *MRI) const override;
201 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
202 /// determine if two loads are loading from the same base address. It should
203 /// only return true if the base pointers are the same and the only
204 /// differences between the two addresses is the offset. It also returns the
205 /// offsets by reference.
206 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
207 int64_t &Offset2) const override;
209 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
210 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
211 /// should be scheduled togther. On some targets if two loads are loading from
212 /// addresses in the same cache line, it's better if they are scheduled
213 /// together. This function takes two integers that represent the load offsets
214 /// from the common base address. It returns true if it decides it's desirable
215 /// to schedule the two loads together. "NumLoads" is the number of loads that
216 /// have already been scheduled after Load1.
217 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
218 int64_t Offset1, int64_t Offset2,
219 unsigned NumLoads) const override;
221 bool isSchedulingBoundary(const MachineInstr *MI,
222 const MachineBasicBlock *MBB,
223 const MachineFunction &MF) const override;
225 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
226 unsigned NumCycles, unsigned ExtraPredCycles,
227 BranchProbability Probability) const override;
229 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
230 unsigned ExtraT, MachineBasicBlock &FMBB,
231 unsigned NumF, unsigned ExtraF,
232 BranchProbability Probability) const override;
234 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
235 BranchProbability Probability) const override {
236 return NumCycles == 1;
239 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
240 MachineBasicBlock &FMBB) const override;
242 /// analyzeCompare - For a comparison instruction, return the source registers
243 /// in SrcReg and SrcReg2 if having two register operands, and the value it
244 /// compares against in CmpValue. Return true if the comparison instruction
246 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
247 unsigned &SrcReg2, int &CmpMask,
248 int &CmpValue) const override;
250 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
251 /// that we can remove a "comparison with zero"; Remove a redundant CMP
252 /// instruction if the flags can be updated in the same way by an earlier
253 /// instruction such as SUB.
254 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
255 unsigned SrcReg2, int CmpMask, int CmpValue,
256 const MachineRegisterInfo *MRI) const override;
258 bool analyzeSelect(const MachineInstr *MI,
259 SmallVectorImpl<MachineOperand> &Cond,
260 unsigned &TrueOp, unsigned &FalseOp,
261 bool &Optimizable) const override;
263 MachineInstr *optimizeSelect(MachineInstr *MI,
264 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
265 bool) const override;
267 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
268 /// instruction, try to fold the immediate into the use instruction.
269 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
270 unsigned Reg, MachineRegisterInfo *MRI) const override;
272 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
273 const MachineInstr *MI) const override;
275 int getOperandLatency(const InstrItineraryData *ItinData,
276 const MachineInstr *DefMI, unsigned DefIdx,
277 const MachineInstr *UseMI,
278 unsigned UseIdx) const override;
279 int getOperandLatency(const InstrItineraryData *ItinData,
280 SDNode *DefNode, unsigned DefIdx,
281 SDNode *UseNode, unsigned UseIdx) const override;
283 /// VFP/NEON execution domains.
284 std::pair<uint16_t, uint16_t>
285 getExecutionDomain(const MachineInstr *MI) const override;
286 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
288 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
289 const TargetRegisterInfo*) const override;
290 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
291 const TargetRegisterInfo *TRI) const override;
293 /// Get the number of addresses by LDM or VLDM or zero for unknown.
294 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
297 unsigned getInstBundleLength(const MachineInstr *MI) const;
299 int getVLDMDefCycle(const InstrItineraryData *ItinData,
300 const MCInstrDesc &DefMCID,
302 unsigned DefIdx, unsigned DefAlign) const;
303 int getLDMDefCycle(const InstrItineraryData *ItinData,
304 const MCInstrDesc &DefMCID,
306 unsigned DefIdx, unsigned DefAlign) const;
307 int getVSTMUseCycle(const InstrItineraryData *ItinData,
308 const MCInstrDesc &UseMCID,
310 unsigned UseIdx, unsigned UseAlign) const;
311 int getSTMUseCycle(const InstrItineraryData *ItinData,
312 const MCInstrDesc &UseMCID,
314 unsigned UseIdx, unsigned UseAlign) const;
315 int getOperandLatency(const InstrItineraryData *ItinData,
316 const MCInstrDesc &DefMCID,
317 unsigned DefIdx, unsigned DefAlign,
318 const MCInstrDesc &UseMCID,
319 unsigned UseIdx, unsigned UseAlign) const;
321 unsigned getPredicationCost(const MachineInstr *MI) const override;
323 unsigned getInstrLatency(const InstrItineraryData *ItinData,
324 const MachineInstr *MI,
325 unsigned *PredCost = nullptr) const override;
327 int getInstrLatency(const InstrItineraryData *ItinData,
328 SDNode *Node) const override;
330 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
331 const MachineRegisterInfo *MRI,
332 const MachineInstr *DefMI, unsigned DefIdx,
333 const MachineInstr *UseMI,
334 unsigned UseIdx) const override;
335 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
336 const MachineInstr *DefMI,
337 unsigned DefIdx) const override;
339 /// verifyInstruction - Perform target specific instruction verification.
340 bool verifyInstruction(const MachineInstr *MI,
341 StringRef &ErrInfo) const override;
343 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
344 Reloc::Model RM) const = 0;
347 /// Modeling special VFP / NEON fp MLA / MLS hazards.
349 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
351 DenseMap<unsigned, unsigned> MLxEntryMap;
353 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
354 /// stalls when scheduled together with fp MLA / MLS opcodes.
355 SmallSet<unsigned, 16> MLxHazardOpcodes;
358 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
360 bool isFpMLxInstruction(unsigned Opcode) const {
361 return MLxEntryMap.count(Opcode);
364 /// isFpMLxInstruction - This version also returns the multiply opcode and the
365 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
366 /// the MLX instructions with an extra lane operand.
367 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
368 unsigned &AddSubOpc, bool &NegAcc,
369 bool &HasLane) const;
371 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
372 /// will cause stalls when scheduled after (within 4-cycle window) a fp
373 /// MLA / MLS instruction.
374 bool canCauseFpMLxStall(unsigned Opcode) const {
375 return MLxHazardOpcodes.count(Opcode);
378 /// Returns true if the instruction has a shift by immediate that can be
379 /// executed in one cycle less.
380 bool isSwiftFastImmShift(const MachineInstr *MI) const;
384 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
385 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
389 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
390 return MIB.addReg(0);
394 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
395 bool isDead = false) {
396 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
400 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
401 return MIB.addReg(0);
405 bool isUncondBranchOpcode(int Opc) {
406 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
410 bool isCondBranchOpcode(int Opc) {
411 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
415 bool isJumpTableBranchOpcode(int Opc) {
416 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
417 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
421 bool isIndirectBranchOpcode(int Opc) {
422 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
425 static inline bool isPopOpcode(int Opc) {
426 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
427 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
428 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
431 static inline bool isPushOpcode(int Opc) {
432 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
433 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
436 /// getInstrPredicate - If instruction is predicated, returns its predicate
437 /// condition, otherwise returns AL. It also returns the condition code
438 /// register by reference.
439 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
441 unsigned getMatchingCondBranchOpcode(unsigned Opc);
443 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
444 /// opcode of the SSA instruction representing the conditional MI.
445 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
447 const MachineRegisterInfo &MRI);
449 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
450 /// the instruction is encoded with an 'S' bit is determined by the optional
451 /// CPSR def operand.
452 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
454 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
455 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
457 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
458 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
459 unsigned DestReg, unsigned BaseReg, int NumBytes,
460 ARMCC::CondCodes Pred, unsigned PredReg,
461 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
463 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
464 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
465 unsigned DestReg, unsigned BaseReg, int NumBytes,
466 ARMCC::CondCodes Pred, unsigned PredReg,
467 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
468 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
470 unsigned DestReg, unsigned BaseReg,
471 int NumBytes, const TargetInstrInfo &TII,
472 const ARMBaseRegisterInfo& MRI,
473 unsigned MIFlags = 0);
475 /// Tries to add registers to the reglist of a given base-updating
476 /// push/pop instruction to adjust the stack by an additional
477 /// NumBytes. This can save a few bytes per function in code-size, but
478 /// obviously generates more memory traffic. As such, it only takes
479 /// effect in functions being optimised for size.
480 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
481 MachineFunction &MF, MachineInstr *MI,
484 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
485 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
486 /// offset could not be handled directly in MI, and return the left-over
487 /// portion by reference.
488 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
489 unsigned FrameReg, int &Offset,
490 const ARMBaseInstrInfo &TII);
492 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
493 unsigned FrameReg, int &Offset,
494 const ARMBaseInstrInfo &TII);
496 } // End llvm namespace