1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
23 class ARMBaseRegisterInfo;
25 /// ARMII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
30 //===------------------------------------------------------------------===//
33 //===------------------------------------------------------------------===//
34 // This four-bit field describes the addressing mode used.
47 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
51 AddrModeT2_pc = 14, // +/- i12 for pc relative data
52 AddrModeT2_i8s4 = 15, // i8 * 4
55 // Size* - Flags to keep track of the size of an instruction.
57 SizeMask = 7 << SizeShift,
58 SizeSpecial = 1, // 0 byte pseudo or special case.
63 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
64 // and store ops only. Generic "updating" flag is used for ld/st multiple.
66 IndexModeMask = 3 << IndexModeShift,
71 //===------------------------------------------------------------------===//
72 // Instruction encoding formats.
75 FormMask = 0x3f << FormShift,
77 // Pseudo instructions
78 Pseudo = 0 << FormShift,
80 // Multiply instructions
81 MulFrm = 1 << FormShift,
83 // Branch instructions
84 BrFrm = 2 << FormShift,
85 BrMiscFrm = 3 << FormShift,
87 // Data Processing instructions
88 DPFrm = 4 << FormShift,
89 DPSoRegFrm = 5 << FormShift,
92 LdFrm = 6 << FormShift,
93 StFrm = 7 << FormShift,
94 LdMiscFrm = 8 << FormShift,
95 StMiscFrm = 9 << FormShift,
96 LdStMulFrm = 10 << FormShift,
98 LdStExFrm = 11 << FormShift,
100 // Miscellaneous arithmetic instructions
101 ArithMiscFrm = 12 << FormShift,
102 SatFrm = 13 << FormShift,
104 // Extend instructions
105 ExtFrm = 14 << FormShift,
108 VFPUnaryFrm = 15 << FormShift,
109 VFPBinaryFrm = 16 << FormShift,
110 VFPConv1Frm = 17 << FormShift,
111 VFPConv2Frm = 18 << FormShift,
112 VFPConv3Frm = 19 << FormShift,
113 VFPConv4Frm = 20 << FormShift,
114 VFPConv5Frm = 21 << FormShift,
115 VFPLdStFrm = 22 << FormShift,
116 VFPLdStMulFrm = 23 << FormShift,
117 VFPMiscFrm = 24 << FormShift,
120 ThumbFrm = 25 << FormShift,
122 // Miscelleaneous format
123 MiscFrm = 26 << FormShift,
126 NGetLnFrm = 27 << FormShift,
127 NSetLnFrm = 28 << FormShift,
128 NDupFrm = 29 << FormShift,
129 NLdStFrm = 30 << FormShift,
130 N1RegModImmFrm= 31 << FormShift,
131 N2RegFrm = 32 << FormShift,
132 NVCVTFrm = 33 << FormShift,
133 NVDupLnFrm = 34 << FormShift,
134 N2RegVShLFrm = 35 << FormShift,
135 N2RegVShRFrm = 36 << FormShift,
136 N3RegFrm = 37 << FormShift,
137 N3RegVShFrm = 38 << FormShift,
138 NVExtFrm = 39 << FormShift,
139 NVMulSLFrm = 40 << FormShift,
140 NVTBLFrm = 41 << FormShift,
142 //===------------------------------------------------------------------===//
145 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
146 // it doesn't have a Rn operand.
149 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
150 // a 16-bit Thumb instruction if certain conditions are met.
151 Xform16Bit = 1 << 17,
153 //===------------------------------------------------------------------===//
156 DomainMask = 3 << DomainShift,
157 DomainGeneral = 0 << DomainShift,
158 DomainVFP = 1 << DomainShift,
159 DomainNEON = 2 << DomainShift,
161 //===------------------------------------------------------------------===//
162 // Field shifts - such shifts are used to set field while generating
163 // machine instructions.
165 // FIXME: This list will need adjusting/fixing as the MC code emitter
166 // takes shape and the ARMCodeEmitter.cpp bits go away.
192 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
193 const ARMSubtarget &Subtarget;
195 // Can be only subclassed.
196 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
198 // Return the non-pre/post incrementing version of 'Opc'. Return 0
199 // if there is not such an opcode.
200 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
202 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
203 MachineBasicBlock::iterator &MBBI,
204 LiveVariables *LV) const;
206 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
207 const ARMSubtarget &getSubtarget() const { return Subtarget; }
209 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
210 MachineBasicBlock::iterator MI,
211 const std::vector<CalleeSavedInfo> &CSI,
212 const TargetRegisterInfo *TRI) const;
215 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
216 MachineBasicBlock *&FBB,
217 SmallVectorImpl<MachineOperand> &Cond,
218 bool AllowModify = false) const;
219 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
220 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
221 MachineBasicBlock *FBB,
222 const SmallVectorImpl<MachineOperand> &Cond,
226 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
228 // Predication support.
229 bool isPredicated(const MachineInstr *MI) const {
230 int PIdx = MI->findFirstPredOperandIdx();
231 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
234 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
235 int PIdx = MI->findFirstPredOperandIdx();
236 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
241 bool PredicateInstruction(MachineInstr *MI,
242 const SmallVectorImpl<MachineOperand> &Pred) const;
245 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
246 const SmallVectorImpl<MachineOperand> &Pred2) const;
248 virtual bool DefinesPredicate(MachineInstr *MI,
249 std::vector<MachineOperand> &Pred) const;
251 virtual bool isPredicable(MachineInstr *MI) const;
253 /// GetInstSize - Returns the size of the specified MachineInstr.
255 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
257 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
258 int &FrameIndex) const;
259 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
260 int &FrameIndex) const;
262 virtual void copyPhysReg(MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator I, DebugLoc DL,
264 unsigned DestReg, unsigned SrcReg,
267 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MBBI,
269 unsigned SrcReg, bool isKill, int FrameIndex,
270 const TargetRegisterClass *RC,
271 const TargetRegisterInfo *TRI) const;
273 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MBBI,
275 unsigned DestReg, int FrameIndex,
276 const TargetRegisterClass *RC,
277 const TargetRegisterInfo *TRI) const;
279 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
285 virtual void reMaterialize(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI,
287 unsigned DestReg, unsigned SubIdx,
288 const MachineInstr *Orig,
289 const TargetRegisterInfo &TRI) const;
291 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
293 virtual bool produceSameValue(const MachineInstr *MI0,
294 const MachineInstr *MI1) const;
296 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
297 /// determine if two loads are loading from the same base address. It should
298 /// only return true if the base pointers are the same and the only
299 /// differences between the two addresses is the offset. It also returns the
300 /// offsets by reference.
301 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
302 int64_t &Offset1, int64_t &Offset2)const;
304 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
305 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
306 /// be scheduled togther. On some targets if two loads are loading from
307 /// addresses in the same cache line, it's better if they are scheduled
308 /// together. This function takes two integers that represent the load offsets
309 /// from the common base address. It returns true if it decides it's desirable
310 /// to schedule the two loads together. "NumLoads" is the number of loads that
311 /// have already been scheduled after Load1.
312 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
313 int64_t Offset1, int64_t Offset2,
314 unsigned NumLoads) const;
316 virtual bool isSchedulingBoundary(const MachineInstr *MI,
317 const MachineBasicBlock *MBB,
318 const MachineFunction &MF) const;
320 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
322 float Prob, float Confidence) const;
324 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
325 MachineBasicBlock &FMBB,unsigned NumF,
326 float Probability, float Confidence) const;
328 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
331 float Confidence) const {
332 return NumInstrs == 1;
335 /// AnalyzeCompare - For a comparison instruction, return the source register
336 /// in SrcReg and the value it compares against in CmpValue. Return true if
337 /// the comparison instruction can be analyzed.
338 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
339 int &CmpMask, int &CmpValue) const;
341 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
342 /// that we can remove a "comparison with zero".
343 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
344 int CmpMask, int CmpValue,
345 const MachineRegisterInfo *MRI,
346 MachineBasicBlock::iterator &MII) const;
348 virtual unsigned getNumMicroOps(const MachineInstr *MI,
349 const InstrItineraryData *ItinData) const;
352 int getOperandLatency(const InstrItineraryData *ItinData,
353 const MachineInstr *DefMI, unsigned DefIdx,
354 const MachineInstr *UseMI, unsigned UseIdx) const;
356 int getOperandLatency(const InstrItineraryData *ItinData,
357 SDNode *DefNode, unsigned DefIdx,
358 SDNode *UseNode, unsigned UseIdx) const;
360 int getVLDMDefCycle(const InstrItineraryData *ItinData,
361 const TargetInstrDesc &DefTID,
363 unsigned DefIdx, unsigned DefAlign) const;
364 int getLDMDefCycle(const InstrItineraryData *ItinData,
365 const TargetInstrDesc &DefTID,
367 unsigned DefIdx, unsigned DefAlign) const;
368 int getVSTMUseCycle(const InstrItineraryData *ItinData,
369 const TargetInstrDesc &UseTID,
371 unsigned UseIdx, unsigned UseAlign) const;
372 int getSTMUseCycle(const InstrItineraryData *ItinData,
373 const TargetInstrDesc &UseTID,
375 unsigned UseIdx, unsigned UseAlign) const;
376 int getOperandLatency(const InstrItineraryData *ItinData,
377 const TargetInstrDesc &DefTID,
378 unsigned DefIdx, unsigned DefAlign,
379 const TargetInstrDesc &UseTID,
380 unsigned UseIdx, unsigned UseAlign) const;
382 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
383 const MachineRegisterInfo *MRI,
384 const MachineInstr *DefMI, unsigned DefIdx,
385 const MachineInstr *UseMI, unsigned UseIdx) const;
386 bool hasLowDefLatency(const InstrItineraryData *ItinData,
387 const MachineInstr *DefMI, unsigned DefIdx) const;
391 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
392 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
396 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
397 return MIB.addReg(0);
401 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
402 bool isDead = false) {
403 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
407 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
408 return MIB.addReg(0);
412 bool isUncondBranchOpcode(int Opc) {
413 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
417 bool isCondBranchOpcode(int Opc) {
418 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
422 bool isJumpTableBranchOpcode(int Opc) {
423 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
424 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
428 bool isIndirectBranchOpcode(int Opc) {
429 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
432 /// getInstrPredicate - If instruction is predicated, returns its predicate
433 /// condition, otherwise returns AL. It also returns the condition code
434 /// register by reference.
435 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
437 int getMatchingCondBranchOpcode(int Opc);
439 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
440 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
442 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
444 unsigned DestReg, unsigned BaseReg, int NumBytes,
445 ARMCC::CondCodes Pred, unsigned PredReg,
446 const ARMBaseInstrInfo &TII);
448 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
449 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
450 unsigned DestReg, unsigned BaseReg, int NumBytes,
451 ARMCC::CondCodes Pred, unsigned PredReg,
452 const ARMBaseInstrInfo &TII);
453 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator &MBBI,
455 unsigned DestReg, unsigned BaseReg,
456 int NumBytes, const TargetInstrInfo &TII,
457 const ARMBaseRegisterInfo& MRI,
461 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
462 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
463 /// offset could not be handled directly in MI, and return the left-over
464 /// portion by reference.
465 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
466 unsigned FrameReg, int &Offset,
467 const ARMBaseInstrInfo &TII);
469 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
470 unsigned FrameReg, int &Offset,
471 const ARMBaseInstrInfo &TII);
473 } // End llvm namespace