1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/SmallSet.h"
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
28 class ARMBaseRegisterInfo;
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 // Return whether the target has an explicit NOP encoding.
41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
42 // if there is not such an opcode.
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46 MachineBasicBlock::iterator &MBBI,
47 LiveVariables *LV) const;
49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
50 const ARMSubtarget &getSubtarget() const { return Subtarget; }
52 ScheduleHazardRecognizer *
53 CreateTargetHazardRecognizer(const TargetMachine *TM,
54 const ScheduleDAG *DAG) const;
56 ScheduleHazardRecognizer *
57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58 const ScheduleDAG *DAG) const;
61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify = false) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
74 // Predication support.
75 bool isPredicated(const MachineInstr *MI) const;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
94 virtual bool isPredicable(MachineInstr *MI) const;
96 /// GetInstSize - Returns the size of the specified MachineInstr.
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
128 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
134 virtual void reMaterialize(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator MI,
136 unsigned DestReg, unsigned SubIdx,
137 const MachineInstr *Orig,
138 const TargetRegisterInfo &TRI) const;
140 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
142 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
144 virtual bool produceSameValue(const MachineInstr *MI0,
145 const MachineInstr *MI1,
146 const MachineRegisterInfo *MRI) const;
148 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
149 /// determine if two loads are loading from the same base address. It should
150 /// only return true if the base pointers are the same and the only
151 /// differences between the two addresses is the offset. It also returns the
152 /// offsets by reference.
153 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
154 int64_t &Offset1, int64_t &Offset2)const;
156 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
157 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
158 /// should be scheduled togther. On some targets if two loads are loading from
159 /// addresses in the same cache line, it's better if they are scheduled
160 /// together. This function takes two integers that represent the load offsets
161 /// from the common base address. It returns true if it decides it's desirable
162 /// to schedule the two loads together. "NumLoads" is the number of loads that
163 /// have already been scheduled after Load1.
164 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
165 int64_t Offset1, int64_t Offset2,
166 unsigned NumLoads) const;
168 virtual bool isSchedulingBoundary(const MachineInstr *MI,
169 const MachineBasicBlock *MBB,
170 const MachineFunction &MF) const;
172 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
173 unsigned NumCycles, unsigned ExtraPredCycles,
174 const BranchProbability &Probability) const;
176 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
177 unsigned NumT, unsigned ExtraT,
178 MachineBasicBlock &FMBB,
179 unsigned NumF, unsigned ExtraF,
180 const BranchProbability &Probability) const;
182 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
184 const BranchProbability
185 &Probability) const {
186 return NumCycles == 1;
189 /// analyzeCompare - For a comparison instruction, return the source registers
190 /// in SrcReg and SrcReg2 if having two register operands, and the value it
191 /// compares against in CmpValue. Return true if the comparison instruction
193 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
194 unsigned &SrcReg2, int &CmpMask,
195 int &CmpValue) const;
197 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
198 /// that we can remove a "comparison with zero"; Remove a redundant CMP
199 /// instruction if the flags can be updated in the same way by an earlier
200 /// instruction such as SUB.
201 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
202 unsigned SrcReg2, int CmpMask, int CmpValue,
203 const MachineRegisterInfo *MRI) const;
205 virtual bool analyzeSelect(const MachineInstr *MI,
206 SmallVectorImpl<MachineOperand> &Cond,
207 unsigned &TrueOp, unsigned &FalseOp,
208 bool &Optimizable) const;
210 virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
212 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
213 /// instruction, try to fold the immediate into the use instruction.
214 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
215 unsigned Reg, MachineRegisterInfo *MRI) const;
217 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
218 const MachineInstr *MI) const;
221 int getOperandLatency(const InstrItineraryData *ItinData,
222 const MachineInstr *DefMI, unsigned DefIdx,
223 const MachineInstr *UseMI, unsigned UseIdx) const;
225 int getOperandLatency(const InstrItineraryData *ItinData,
226 SDNode *DefNode, unsigned DefIdx,
227 SDNode *UseNode, unsigned UseIdx) const;
229 virtual unsigned getOutputLatency(const InstrItineraryData *ItinData,
230 const MachineInstr *DefMI, unsigned DefIdx,
231 const MachineInstr *DepMI) const;
233 /// VFP/NEON execution domains.
234 std::pair<uint16_t, uint16_t>
235 getExecutionDomain(const MachineInstr *MI) const;
236 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
239 unsigned getInstBundleLength(const MachineInstr *MI) const;
241 int getVLDMDefCycle(const InstrItineraryData *ItinData,
242 const MCInstrDesc &DefMCID,
244 unsigned DefIdx, unsigned DefAlign) const;
245 int getLDMDefCycle(const InstrItineraryData *ItinData,
246 const MCInstrDesc &DefMCID,
248 unsigned DefIdx, unsigned DefAlign) const;
249 int getVSTMUseCycle(const InstrItineraryData *ItinData,
250 const MCInstrDesc &UseMCID,
252 unsigned UseIdx, unsigned UseAlign) const;
253 int getSTMUseCycle(const InstrItineraryData *ItinData,
254 const MCInstrDesc &UseMCID,
256 unsigned UseIdx, unsigned UseAlign) const;
257 int getOperandLatency(const InstrItineraryData *ItinData,
258 const MCInstrDesc &DefMCID,
259 unsigned DefIdx, unsigned DefAlign,
260 const MCInstrDesc &UseMCID,
261 unsigned UseIdx, unsigned UseAlign) const;
263 unsigned getInstrLatency(const InstrItineraryData *ItinData,
264 const MachineInstr *MI,
265 unsigned *PredCost = 0) const;
267 int getInstrLatency(const InstrItineraryData *ItinData,
270 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
271 const MachineRegisterInfo *MRI,
272 const MachineInstr *DefMI, unsigned DefIdx,
273 const MachineInstr *UseMI, unsigned UseIdx) const;
274 bool hasLowDefLatency(const InstrItineraryData *ItinData,
275 const MachineInstr *DefMI, unsigned DefIdx) const;
277 /// verifyInstruction - Perform target specific instruction verification.
278 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
281 /// Modeling special VFP / NEON fp MLA / MLS hazards.
283 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
285 DenseMap<unsigned, unsigned> MLxEntryMap;
287 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
288 /// stalls when scheduled together with fp MLA / MLS opcodes.
289 SmallSet<unsigned, 16> MLxHazardOpcodes;
292 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
294 bool isFpMLxInstruction(unsigned Opcode) const {
295 return MLxEntryMap.count(Opcode);
298 /// isFpMLxInstruction - This version also returns the multiply opcode and the
299 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
300 /// the MLX instructions with an extra lane operand.
301 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
302 unsigned &AddSubOpc, bool &NegAcc,
303 bool &HasLane) const;
305 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
306 /// will cause stalls when scheduled after (within 4-cycle window) a fp
307 /// MLA / MLS instruction.
308 bool canCauseFpMLxStall(unsigned Opcode) const {
309 return MLxHazardOpcodes.count(Opcode);
314 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
315 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
319 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
320 return MIB.addReg(0);
324 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
325 bool isDead = false) {
326 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
330 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
331 return MIB.addReg(0);
335 bool isUncondBranchOpcode(int Opc) {
336 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
340 bool isCondBranchOpcode(int Opc) {
341 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
345 bool isJumpTableBranchOpcode(int Opc) {
346 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
347 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
351 bool isIndirectBranchOpcode(int Opc) {
352 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
355 /// getInstrPredicate - If instruction is predicated, returns its predicate
356 /// condition, otherwise returns AL. It also returns the condition code
357 /// register by reference.
358 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
360 int getMatchingCondBranchOpcode(int Opc);
362 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
363 /// opcode of the SSA instruction representing the conditional MI.
364 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
366 const MachineRegisterInfo &MRI);
368 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
369 /// the instruction is encoded with an 'S' bit is determined by the optional
370 /// CPSR def operand.
371 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
373 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
374 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
376 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
377 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
378 unsigned DestReg, unsigned BaseReg, int NumBytes,
379 ARMCC::CondCodes Pred, unsigned PredReg,
380 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
382 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
384 unsigned DestReg, unsigned BaseReg, int NumBytes,
385 ARMCC::CondCodes Pred, unsigned PredReg,
386 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
387 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
388 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
389 unsigned DestReg, unsigned BaseReg,
390 int NumBytes, const TargetInstrInfo &TII,
391 const ARMBaseRegisterInfo& MRI,
392 unsigned MIFlags = 0);
395 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
396 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
397 /// offset could not be handled directly in MI, and return the left-over
398 /// portion by reference.
399 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
400 unsigned FrameReg, int &Offset,
401 const ARMBaseInstrInfo &TII);
403 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
404 unsigned FrameReg, int &Offset,
405 const ARMBaseInstrInfo &TII);
407 } // End llvm namespace