1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CodeGen.h"
22 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
29 class ARMBaseRegisterInfo;
31 class ARMBaseInstrInfo : public ARMGenInstrInfo {
32 const ARMSubtarget &Subtarget;
35 // Can be only subclassed.
36 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
39 unsigned LoadImmOpc, unsigned LoadOpc,
40 Reloc::Model RM) const;
43 // Return whether the target has an explicit NOP encoding.
46 // Return the non-pre/post incrementing version of 'Opc'. Return 0
47 // if there is not such an opcode.
48 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
50 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
51 MachineBasicBlock::iterator &MBBI,
52 LiveVariables *LV) const override;
54 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
55 const ARMSubtarget &getSubtarget() const { return Subtarget; }
57 ScheduleHazardRecognizer *
58 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
59 const ScheduleDAG *DAG) const override;
61 ScheduleHazardRecognizer *
62 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
63 const ScheduleDAG *DAG) const override;
66 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
67 MachineBasicBlock *&FBB,
68 SmallVectorImpl<MachineOperand> &Cond,
69 bool AllowModify = false) const override;
70 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72 MachineBasicBlock *FBB,
73 const SmallVectorImpl<MachineOperand> &Cond,
74 DebugLoc DL) const override;
77 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
79 // Predication support.
80 bool isPredicated(const MachineInstr *MI) const override;
82 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
83 int PIdx = MI->findFirstPredOperandIdx();
84 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
88 bool PredicateInstruction(MachineInstr *MI,
89 const SmallVectorImpl<MachineOperand> &Pred) const override;
91 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
92 const SmallVectorImpl<MachineOperand> &Pred2) const override;
94 bool DefinesPredicate(MachineInstr *MI,
95 std::vector<MachineOperand> &Pred) const override;
97 bool isPredicable(MachineInstr *MI) const override;
99 /// GetInstSize - Returns the size of the specified MachineInstr.
101 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
103 unsigned isLoadFromStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const override;
105 unsigned isStoreToStackSlot(const MachineInstr *MI,
106 int &FrameIndex) const override;
107 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
108 int &FrameIndex) const override;
109 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
110 int &FrameIndex) const override;
112 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
113 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
114 bool KillSrc) const override;
116 void storeRegToStackSlot(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator MBBI,
118 unsigned SrcReg, bool isKill, int FrameIndex,
119 const TargetRegisterClass *RC,
120 const TargetRegisterInfo *TRI) const override;
122 void loadRegFromStackSlot(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MBBI,
124 unsigned DestReg, int FrameIndex,
125 const TargetRegisterClass *RC,
126 const TargetRegisterInfo *TRI) const override;
128 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
130 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
131 unsigned DestReg, unsigned SubIdx,
132 const MachineInstr *Orig,
133 const TargetRegisterInfo &TRI) const override;
135 MachineInstr *duplicate(MachineInstr *Orig,
136 MachineFunction &MF) const override;
138 MachineInstr *commuteInstruction(MachineInstr*,
139 bool=false) const override;
141 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
142 unsigned SubIdx, unsigned State,
143 const TargetRegisterInfo *TRI) const;
145 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
146 const MachineRegisterInfo *MRI) const override;
148 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
149 /// determine if two loads are loading from the same base address. It should
150 /// only return true if the base pointers are the same and the only
151 /// differences between the two addresses is the offset. It also returns the
152 /// offsets by reference.
153 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
154 int64_t &Offset2) const override;
156 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
157 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
158 /// should be scheduled togther. On some targets if two loads are loading from
159 /// addresses in the same cache line, it's better if they are scheduled
160 /// together. This function takes two integers that represent the load offsets
161 /// from the common base address. It returns true if it decides it's desirable
162 /// to schedule the two loads together. "NumLoads" is the number of loads that
163 /// have already been scheduled after Load1.
164 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
165 int64_t Offset1, int64_t Offset2,
166 unsigned NumLoads) const override;
168 bool isSchedulingBoundary(const MachineInstr *MI,
169 const MachineBasicBlock *MBB,
170 const MachineFunction &MF) const override;
172 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
173 unsigned NumCycles, unsigned ExtraPredCycles,
174 const BranchProbability &Probability) const override;
176 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
177 unsigned ExtraT, MachineBasicBlock &FMBB,
178 unsigned NumF, unsigned ExtraF,
179 const BranchProbability &Probability) const override;
181 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
182 const BranchProbability &Probability) const override {
183 return NumCycles == 1;
186 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
187 MachineBasicBlock &FMBB) const override;
189 /// analyzeCompare - For a comparison instruction, return the source registers
190 /// in SrcReg and SrcReg2 if having two register operands, and the value it
191 /// compares against in CmpValue. Return true if the comparison instruction
193 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
194 unsigned &SrcReg2, int &CmpMask,
195 int &CmpValue) const override;
197 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
198 /// that we can remove a "comparison with zero"; Remove a redundant CMP
199 /// instruction if the flags can be updated in the same way by an earlier
200 /// instruction such as SUB.
201 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
202 unsigned SrcReg2, int CmpMask, int CmpValue,
203 const MachineRegisterInfo *MRI) const override;
205 bool analyzeSelect(const MachineInstr *MI,
206 SmallVectorImpl<MachineOperand> &Cond,
207 unsigned &TrueOp, unsigned &FalseOp,
208 bool &Optimizable) const override;
210 MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
212 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
213 /// instruction, try to fold the immediate into the use instruction.
214 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
215 unsigned Reg, MachineRegisterInfo *MRI) const override;
217 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
218 const MachineInstr *MI) const override;
220 int getOperandLatency(const InstrItineraryData *ItinData,
221 const MachineInstr *DefMI, unsigned DefIdx,
222 const MachineInstr *UseMI,
223 unsigned UseIdx) const override;
224 int getOperandLatency(const InstrItineraryData *ItinData,
225 SDNode *DefNode, unsigned DefIdx,
226 SDNode *UseNode, unsigned UseIdx) const override;
228 /// VFP/NEON execution domains.
229 std::pair<uint16_t, uint16_t>
230 getExecutionDomain(const MachineInstr *MI) const override;
231 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
233 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
234 const TargetRegisterInfo*) const override;
235 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
236 const TargetRegisterInfo *TRI) const override;
239 getUnconditionalBranch(MCInst &Branch,
240 const MCSymbolRefExpr *BranchTarget) const override;
242 void getTrap(MCInst &MI) const override;
244 /// Get the number of addresses by LDM or VLDM or zero for unknown.
245 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
248 unsigned getInstBundleLength(const MachineInstr *MI) const;
250 int getVLDMDefCycle(const InstrItineraryData *ItinData,
251 const MCInstrDesc &DefMCID,
253 unsigned DefIdx, unsigned DefAlign) const;
254 int getLDMDefCycle(const InstrItineraryData *ItinData,
255 const MCInstrDesc &DefMCID,
257 unsigned DefIdx, unsigned DefAlign) const;
258 int getVSTMUseCycle(const InstrItineraryData *ItinData,
259 const MCInstrDesc &UseMCID,
261 unsigned UseIdx, unsigned UseAlign) const;
262 int getSTMUseCycle(const InstrItineraryData *ItinData,
263 const MCInstrDesc &UseMCID,
265 unsigned UseIdx, unsigned UseAlign) const;
266 int getOperandLatency(const InstrItineraryData *ItinData,
267 const MCInstrDesc &DefMCID,
268 unsigned DefIdx, unsigned DefAlign,
269 const MCInstrDesc &UseMCID,
270 unsigned UseIdx, unsigned UseAlign) const;
272 unsigned getPredicationCost(const MachineInstr *MI) const override;
274 unsigned getInstrLatency(const InstrItineraryData *ItinData,
275 const MachineInstr *MI,
276 unsigned *PredCost = nullptr) const override;
278 int getInstrLatency(const InstrItineraryData *ItinData,
279 SDNode *Node) const override;
281 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
282 const MachineRegisterInfo *MRI,
283 const MachineInstr *DefMI, unsigned DefIdx,
284 const MachineInstr *UseMI,
285 unsigned UseIdx) const override;
286 bool hasLowDefLatency(const InstrItineraryData *ItinData,
287 const MachineInstr *DefMI,
288 unsigned DefIdx) const override;
290 /// verifyInstruction - Perform target specific instruction verification.
291 bool verifyInstruction(const MachineInstr *MI,
292 StringRef &ErrInfo) const override;
294 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
295 Reloc::Model RM) const = 0;
298 /// Modeling special VFP / NEON fp MLA / MLS hazards.
300 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
302 DenseMap<unsigned, unsigned> MLxEntryMap;
304 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
305 /// stalls when scheduled together with fp MLA / MLS opcodes.
306 SmallSet<unsigned, 16> MLxHazardOpcodes;
309 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
311 bool isFpMLxInstruction(unsigned Opcode) const {
312 return MLxEntryMap.count(Opcode);
315 /// isFpMLxInstruction - This version also returns the multiply opcode and the
316 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
317 /// the MLX instructions with an extra lane operand.
318 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
319 unsigned &AddSubOpc, bool &NegAcc,
320 bool &HasLane) const;
322 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
323 /// will cause stalls when scheduled after (within 4-cycle window) a fp
324 /// MLA / MLS instruction.
325 bool canCauseFpMLxStall(unsigned Opcode) const {
326 return MLxHazardOpcodes.count(Opcode);
329 /// Returns true if the instruction has a shift by immediate that can be
330 /// executed in one cycle less.
331 bool isSwiftFastImmShift(const MachineInstr *MI) const;
335 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
336 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
340 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
341 return MIB.addReg(0);
345 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
346 bool isDead = false) {
347 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
351 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
352 return MIB.addReg(0);
356 bool isUncondBranchOpcode(int Opc) {
357 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
361 bool isCondBranchOpcode(int Opc) {
362 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
366 bool isJumpTableBranchOpcode(int Opc) {
367 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
368 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
372 bool isIndirectBranchOpcode(int Opc) {
373 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
376 static inline bool isPopOpcode(int Opc) {
377 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
378 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
379 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
382 static inline bool isPushOpcode(int Opc) {
383 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
384 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
387 /// getInstrPredicate - If instruction is predicated, returns its predicate
388 /// condition, otherwise returns AL. It also returns the condition code
389 /// register by reference.
390 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
392 int getMatchingCondBranchOpcode(int Opc);
394 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
395 /// opcode of the SSA instruction representing the conditional MI.
396 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
398 const MachineRegisterInfo &MRI);
400 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
401 /// the instruction is encoded with an 'S' bit is determined by the optional
402 /// CPSR def operand.
403 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
405 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
406 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
408 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
409 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
410 unsigned DestReg, unsigned BaseReg, int NumBytes,
411 ARMCC::CondCodes Pred, unsigned PredReg,
412 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
414 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
415 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
416 unsigned DestReg, unsigned BaseReg, int NumBytes,
417 ARMCC::CondCodes Pred, unsigned PredReg,
418 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
419 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
420 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
421 unsigned DestReg, unsigned BaseReg,
422 int NumBytes, const TargetInstrInfo &TII,
423 const ARMBaseRegisterInfo& MRI,
424 unsigned MIFlags = 0);
426 /// Tries to add registers to the reglist of a given base-updating
427 /// push/pop instruction to adjust the stack by an additional
428 /// NumBytes. This can save a few bytes per function in code-size, but
429 /// obviously generates more memory traffic. As such, it only takes
430 /// effect in functions being optimised for size.
431 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
432 MachineFunction &MF, MachineInstr *MI,
435 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
436 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
437 /// offset could not be handled directly in MI, and return the left-over
438 /// portion by reference.
439 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
440 unsigned FrameReg, int &Offset,
441 const ARMBaseInstrInfo &TII);
443 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
444 unsigned FrameReg, int &Offset,
445 const ARMBaseInstrInfo &TII);
447 } // End llvm namespace