1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Target/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "ARMGenInstrInfo.inc"
28 class ARMBaseRegisterInfo;
30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
31 const ARMSubtarget &Subtarget;
34 // Can be only subclassed.
35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
38 // Return whether the target has an explicit NOP encoding.
41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
42 // if there is not such an opcode.
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
46 MachineBasicBlock::iterator &MBBI,
47 LiveVariables *LV) const;
49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
50 const ARMSubtarget &getSubtarget() const { return Subtarget; }
52 ScheduleHazardRecognizer *
53 CreateTargetHazardRecognizer(const TargetMachine *TM,
54 const ScheduleDAG *DAG) const;
56 ScheduleHazardRecognizer *
57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
58 const ScheduleDAG *DAG) const;
61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
62 MachineBasicBlock *&FBB,
63 SmallVectorImpl<MachineOperand> &Cond,
64 bool AllowModify = false) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
67 MachineBasicBlock *FBB,
68 const SmallVectorImpl<MachineOperand> &Cond,
72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
74 // Predication support.
75 bool isPredicated(const MachineInstr *MI) const;
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
78 int PIdx = MI->findFirstPredOperandIdx();
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
84 bool PredicateInstruction(MachineInstr *MI,
85 const SmallVectorImpl<MachineOperand> &Pred) const;
88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
89 const SmallVectorImpl<MachineOperand> &Pred2) const;
91 virtual bool DefinesPredicate(MachineInstr *MI,
92 std::vector<MachineOperand> &Pred) const;
94 virtual bool isPredicable(MachineInstr *MI) const;
96 /// GetInstSize - Returns the size of the specified MachineInstr.
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const;
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
103 int &FrameIndex) const;
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
105 int &FrameIndex) const;
106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
107 int &FrameIndex) const;
109 virtual void copyPhysReg(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator I, DebugLoc DL,
111 unsigned DestReg, unsigned SrcReg,
114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MBBI,
116 unsigned SrcReg, bool isKill, int FrameIndex,
117 const TargetRegisterClass *RC,
118 const TargetRegisterInfo *TRI) const;
120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator MBBI,
122 unsigned DestReg, int FrameIndex,
123 const TargetRegisterClass *RC,
124 const TargetRegisterInfo *TRI) const;
126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
128 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
134 virtual void reMaterialize(MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator MI,
136 unsigned DestReg, unsigned SubIdx,
137 const MachineInstr *Orig,
138 const TargetRegisterInfo &TRI) const;
140 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
142 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
144 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
145 unsigned SubIdx, unsigned State,
146 const TargetRegisterInfo *TRI) const;
148 virtual bool produceSameValue(const MachineInstr *MI0,
149 const MachineInstr *MI1,
150 const MachineRegisterInfo *MRI) const;
152 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
153 /// determine if two loads are loading from the same base address. It should
154 /// only return true if the base pointers are the same and the only
155 /// differences between the two addresses is the offset. It also returns the
156 /// offsets by reference.
157 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
158 int64_t &Offset1, int64_t &Offset2)const;
160 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
161 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
162 /// should be scheduled togther. On some targets if two loads are loading from
163 /// addresses in the same cache line, it's better if they are scheduled
164 /// together. This function takes two integers that represent the load offsets
165 /// from the common base address. It returns true if it decides it's desirable
166 /// to schedule the two loads together. "NumLoads" is the number of loads that
167 /// have already been scheduled after Load1.
168 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
169 int64_t Offset1, int64_t Offset2,
170 unsigned NumLoads) const;
172 virtual bool isSchedulingBoundary(const MachineInstr *MI,
173 const MachineBasicBlock *MBB,
174 const MachineFunction &MF) const;
176 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
177 unsigned NumCycles, unsigned ExtraPredCycles,
178 const BranchProbability &Probability) const;
180 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
181 unsigned NumT, unsigned ExtraT,
182 MachineBasicBlock &FMBB,
183 unsigned NumF, unsigned ExtraF,
184 const BranchProbability &Probability) const;
186 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
188 const BranchProbability
189 &Probability) const {
190 return NumCycles == 1;
193 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
194 MachineBasicBlock &FMBB) const;
196 /// analyzeCompare - For a comparison instruction, return the source registers
197 /// in SrcReg and SrcReg2 if having two register operands, and the value it
198 /// compares against in CmpValue. Return true if the comparison instruction
200 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
201 unsigned &SrcReg2, int &CmpMask,
202 int &CmpValue) const;
204 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
205 /// that we can remove a "comparison with zero"; Remove a redundant CMP
206 /// instruction if the flags can be updated in the same way by an earlier
207 /// instruction such as SUB.
208 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
209 unsigned SrcReg2, int CmpMask, int CmpValue,
210 const MachineRegisterInfo *MRI) const;
212 virtual bool analyzeSelect(const MachineInstr *MI,
213 SmallVectorImpl<MachineOperand> &Cond,
214 unsigned &TrueOp, unsigned &FalseOp,
215 bool &Optimizable) const;
217 virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
219 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
220 /// instruction, try to fold the immediate into the use instruction.
221 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
222 unsigned Reg, MachineRegisterInfo *MRI) const;
224 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
225 const MachineInstr *MI) const;
228 int getOperandLatency(const InstrItineraryData *ItinData,
229 const MachineInstr *DefMI, unsigned DefIdx,
230 const MachineInstr *UseMI, unsigned UseIdx) const;
232 int getOperandLatency(const InstrItineraryData *ItinData,
233 SDNode *DefNode, unsigned DefIdx,
234 SDNode *UseNode, unsigned UseIdx) const;
236 /// VFP/NEON execution domains.
237 std::pair<uint16_t, uint16_t>
238 getExecutionDomain(const MachineInstr *MI) const;
239 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
241 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
242 const TargetRegisterInfo*) const;
243 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
244 const TargetRegisterInfo *TRI) const;
245 /// Get the number of addresses by LDM or VLDM or zero for unknown.
246 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
249 unsigned getInstBundleLength(const MachineInstr *MI) const;
251 int getVLDMDefCycle(const InstrItineraryData *ItinData,
252 const MCInstrDesc &DefMCID,
254 unsigned DefIdx, unsigned DefAlign) const;
255 int getLDMDefCycle(const InstrItineraryData *ItinData,
256 const MCInstrDesc &DefMCID,
258 unsigned DefIdx, unsigned DefAlign) const;
259 int getVSTMUseCycle(const InstrItineraryData *ItinData,
260 const MCInstrDesc &UseMCID,
262 unsigned UseIdx, unsigned UseAlign) const;
263 int getSTMUseCycle(const InstrItineraryData *ItinData,
264 const MCInstrDesc &UseMCID,
266 unsigned UseIdx, unsigned UseAlign) const;
267 int getOperandLatency(const InstrItineraryData *ItinData,
268 const MCInstrDesc &DefMCID,
269 unsigned DefIdx, unsigned DefAlign,
270 const MCInstrDesc &UseMCID,
271 unsigned UseIdx, unsigned UseAlign) const;
273 unsigned getInstrLatency(const InstrItineraryData *ItinData,
274 const MachineInstr *MI,
275 unsigned *PredCost = 0) const;
277 int getInstrLatency(const InstrItineraryData *ItinData,
280 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
281 const MachineRegisterInfo *MRI,
282 const MachineInstr *DefMI, unsigned DefIdx,
283 const MachineInstr *UseMI, unsigned UseIdx) const;
284 bool hasLowDefLatency(const InstrItineraryData *ItinData,
285 const MachineInstr *DefMI, unsigned DefIdx) const;
287 /// verifyInstruction - Perform target specific instruction verification.
288 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
291 /// Modeling special VFP / NEON fp MLA / MLS hazards.
293 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
295 DenseMap<unsigned, unsigned> MLxEntryMap;
297 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
298 /// stalls when scheduled together with fp MLA / MLS opcodes.
299 SmallSet<unsigned, 16> MLxHazardOpcodes;
302 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
304 bool isFpMLxInstruction(unsigned Opcode) const {
305 return MLxEntryMap.count(Opcode);
308 /// isFpMLxInstruction - This version also returns the multiply opcode and the
309 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
310 /// the MLX instructions with an extra lane operand.
311 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
312 unsigned &AddSubOpc, bool &NegAcc,
313 bool &HasLane) const;
315 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
316 /// will cause stalls when scheduled after (within 4-cycle window) a fp
317 /// MLA / MLS instruction.
318 bool canCauseFpMLxStall(unsigned Opcode) const {
319 return MLxHazardOpcodes.count(Opcode);
322 /// Returns true if the instruction has a shift by immediate that can be
323 /// executed in one cycle less.
324 bool isSwiftFastImmShift(const MachineInstr *MI) const;
328 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
329 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
333 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
334 return MIB.addReg(0);
338 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
339 bool isDead = false) {
340 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
344 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
345 return MIB.addReg(0);
349 bool isUncondBranchOpcode(int Opc) {
350 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
354 bool isCondBranchOpcode(int Opc) {
355 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
359 bool isJumpTableBranchOpcode(int Opc) {
360 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
361 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
365 bool isIndirectBranchOpcode(int Opc) {
366 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
369 /// getInstrPredicate - If instruction is predicated, returns its predicate
370 /// condition, otherwise returns AL. It also returns the condition code
371 /// register by reference.
372 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
374 int getMatchingCondBranchOpcode(int Opc);
376 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
377 /// opcode of the SSA instruction representing the conditional MI.
378 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
380 const MachineRegisterInfo &MRI);
382 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
383 /// the instruction is encoded with an 'S' bit is determined by the optional
384 /// CPSR def operand.
385 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
387 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
388 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
390 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
391 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
392 unsigned DestReg, unsigned BaseReg, int NumBytes,
393 ARMCC::CondCodes Pred, unsigned PredReg,
394 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
396 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
398 unsigned DestReg, unsigned BaseReg, int NumBytes,
399 ARMCC::CondCodes Pred, unsigned PredReg,
400 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
401 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
403 unsigned DestReg, unsigned BaseReg,
404 int NumBytes, const TargetInstrInfo &TII,
405 const ARMBaseRegisterInfo& MRI,
406 unsigned MIFlags = 0);
409 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
410 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
411 /// offset could not be handled directly in MI, and return the left-over
412 /// portion by reference.
413 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
414 unsigned FrameReg, int &Offset,
415 const ARMBaseInstrInfo &TII);
417 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
418 unsigned FrameReg, int &Offset,
419 const ARMBaseInstrInfo &TII);
421 } // End llvm namespace