1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "ARMRegisterInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Target/TargetInstrInfo.h"
25 /// ARMII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
30 //===------------------------------------------------------------------===//
33 //===------------------------------------------------------------------===//
34 // This four-bit field describes the addressing mode used.
47 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
51 AddrModeT2_pc = 14, // +/- i12 for pc relative data
52 AddrModeT2_i8s4 = 15, // i8 * 4
54 // Size* - Flags to keep track of the size of an instruction.
56 SizeMask = 7 << SizeShift,
57 SizeSpecial = 1, // 0 byte pseudo or special case.
62 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
65 IndexModeMask = 3 << IndexModeShift,
69 //===------------------------------------------------------------------===//
70 // Instruction encoding formats.
73 FormMask = 0x3f << FormShift,
75 // Pseudo instructions
76 Pseudo = 0 << FormShift,
78 // Multiply instructions
79 MulFrm = 1 << FormShift,
81 // Branch instructions
82 BrFrm = 2 << FormShift,
83 BrMiscFrm = 3 << FormShift,
85 // Data Processing instructions
86 DPFrm = 4 << FormShift,
87 DPSoRegFrm = 5 << FormShift,
90 LdFrm = 6 << FormShift,
91 StFrm = 7 << FormShift,
92 LdMiscFrm = 8 << FormShift,
93 StMiscFrm = 9 << FormShift,
94 LdStMulFrm = 10 << FormShift,
96 // Miscellaneous arithmetic instructions
97 ArithMiscFrm = 11 << FormShift,
99 // Extend instructions
100 ExtFrm = 12 << FormShift,
103 VFPUnaryFrm = 13 << FormShift,
104 VFPBinaryFrm = 14 << FormShift,
105 VFPConv1Frm = 15 << FormShift,
106 VFPConv2Frm = 16 << FormShift,
107 VFPConv3Frm = 17 << FormShift,
108 VFPConv4Frm = 18 << FormShift,
109 VFPConv5Frm = 19 << FormShift,
110 VFPLdStFrm = 20 << FormShift,
111 VFPLdStMulFrm = 21 << FormShift,
112 VFPMiscFrm = 22 << FormShift,
115 ThumbFrm = 23 << FormShift,
118 NEONFrm = 24 << FormShift,
119 NEONGetLnFrm = 25 << FormShift,
120 NEONSetLnFrm = 26 << FormShift,
121 NEONDupFrm = 27 << FormShift,
123 //===------------------------------------------------------------------===//
126 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
127 // it doesn't have a Rn operand.
130 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
131 // a 16-bit Thumb instruction if certain conditions are met.
132 Xform16Bit = 1 << 16,
134 //===------------------------------------------------------------------===//
135 // Field shifts - such shifts are used to set field while generating
136 // machine instructions.
159 /// ARMII::Op - Holds all of the instruction types required by
160 /// target specific instruction and register code. ARMBaseInstrInfo
161 /// and subclasses should return a specific opcode that implements
162 /// the instruction type.
181 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
182 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
186 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
187 return MIB.addReg(0);
191 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB) {
192 return MIB.addReg(ARM::CPSR);
195 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
197 // Can be only subclassed.
198 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
200 // Return the non-pre/post incrementing version of 'Opc'. Return 0
201 // if there is not such an opcode.
202 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
204 // Return the opcode that implements 'Op', or 0 if no opcode
205 virtual unsigned getOpcode(ARMII::Op Op) const =0;
207 // Return true if the block does not fall through.
208 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
210 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
211 MachineBasicBlock::iterator &MBBI,
212 LiveVariables *LV) const;
214 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
217 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
218 MachineBasicBlock *&FBB,
219 SmallVectorImpl<MachineOperand> &Cond,
220 bool AllowModify) const;
221 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
222 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
223 MachineBasicBlock *FBB,
224 const SmallVectorImpl<MachineOperand> &Cond) const;
227 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
229 // Predication support.
230 bool isPredicated(const MachineInstr *MI) const {
231 int PIdx = MI->findFirstPredOperandIdx();
232 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
235 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
236 int PIdx = MI->findFirstPredOperandIdx();
237 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
242 bool PredicateInstruction(MachineInstr *MI,
243 const SmallVectorImpl<MachineOperand> &Pred) const;
246 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
247 const SmallVectorImpl<MachineOperand> &Pred2) const;
249 virtual bool DefinesPredicate(MachineInstr *MI,
250 std::vector<MachineOperand> &Pred) const;
252 /// GetInstSize - Returns the size of the specified MachineInstr.
254 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
256 /// Return true if the instruction is a register to register move and return
257 /// the source and dest operands and their sub-register indices by reference.
258 virtual bool isMoveInstr(const MachineInstr &MI,
259 unsigned &SrcReg, unsigned &DstReg,
260 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
262 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
263 int &FrameIndex) const;
264 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
265 int &FrameIndex) const;
267 virtual bool copyRegToReg(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator I,
269 unsigned DestReg, unsigned SrcReg,
270 const TargetRegisterClass *DestRC,
271 const TargetRegisterClass *SrcRC) const;
273 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
274 MachineBasicBlock::iterator MBBI,
275 unsigned SrcReg, bool isKill, int FrameIndex,
276 const TargetRegisterClass *RC) const;
278 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator MBBI,
280 unsigned DestReg, int FrameIndex,
281 const TargetRegisterClass *RC) const;
283 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
284 const SmallVectorImpl<unsigned> &Ops) const;
286 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
288 const SmallVectorImpl<unsigned> &Ops,
289 int FrameIndex) const;
291 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
293 const SmallVectorImpl<unsigned> &Ops,
294 MachineInstr* LoadMI) const;