1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
24 /// ARMII - This namespace holds all of the target specific flags that
25 /// instruction info tracks.
29 //===------------------------------------------------------------------===//
32 //===------------------------------------------------------------------===//
33 // This four-bit field describes the addressing mode used.
46 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
50 AddrModeT2_pc = 14, // +/- i12 for pc relative data
51 AddrModeT2_i8s4 = 15, // i8 * 4
53 // Size* - Flags to keep track of the size of an instruction.
55 SizeMask = 7 << SizeShift,
56 SizeSpecial = 1, // 0 byte pseudo or special case.
61 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
64 IndexModeMask = 3 << IndexModeShift,
68 //===------------------------------------------------------------------===//
69 // Instruction encoding formats.
72 FormMask = 0x3f << FormShift,
74 // Pseudo instructions
75 Pseudo = 0 << FormShift,
77 // Multiply instructions
78 MulFrm = 1 << FormShift,
80 // Branch instructions
81 BrFrm = 2 << FormShift,
82 BrMiscFrm = 3 << FormShift,
84 // Data Processing instructions
85 DPFrm = 4 << FormShift,
86 DPSoRegFrm = 5 << FormShift,
89 LdFrm = 6 << FormShift,
90 StFrm = 7 << FormShift,
91 LdMiscFrm = 8 << FormShift,
92 StMiscFrm = 9 << FormShift,
93 LdStMulFrm = 10 << FormShift,
95 // Miscellaneous arithmetic instructions
96 ArithMiscFrm = 11 << FormShift,
98 // Extend instructions
99 ExtFrm = 12 << FormShift,
102 VFPUnaryFrm = 13 << FormShift,
103 VFPBinaryFrm = 14 << FormShift,
104 VFPConv1Frm = 15 << FormShift,
105 VFPConv2Frm = 16 << FormShift,
106 VFPConv3Frm = 17 << FormShift,
107 VFPConv4Frm = 18 << FormShift,
108 VFPConv5Frm = 19 << FormShift,
109 VFPLdStFrm = 20 << FormShift,
110 VFPLdStMulFrm = 21 << FormShift,
111 VFPMiscFrm = 22 << FormShift,
114 ThumbFrm = 23 << FormShift,
117 NEONFrm = 24 << FormShift,
118 NEONGetLnFrm = 25 << FormShift,
119 NEONSetLnFrm = 26 << FormShift,
120 NEONDupFrm = 27 << FormShift,
122 //===------------------------------------------------------------------===//
125 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
126 // it doesn't have a Rn operand.
129 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
130 // a 16-bit Thumb instruction if certain conditions are met.
131 Xform16Bit = 1 << 16,
133 //===------------------------------------------------------------------===//
134 // Field shifts - such shifts are used to set field while generating
135 // machine instructions.
158 /// ARMII::Op - Holds all of the instruction types required by
159 /// target specific instruction and register code. ARMBaseInstrInfo
160 /// and subclasses should return a specific opcode that implements
161 /// the instruction type.
190 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
192 // Can be only subclassed.
193 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
195 // Return the non-pre/post incrementing version of 'Opc'. Return 0
196 // if there is not such an opcode.
197 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
199 // Return the opcode that implements 'Op', or 0 if no opcode
200 virtual unsigned getOpcode(ARMII::Op Op) const =0;
202 // Return true if the block does not fall through.
203 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const =0;
205 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
206 MachineBasicBlock::iterator &MBBI,
207 LiveVariables *LV) const;
209 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
212 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
213 MachineBasicBlock *&FBB,
214 SmallVectorImpl<MachineOperand> &Cond,
215 bool AllowModify) const;
216 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
217 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
218 MachineBasicBlock *FBB,
219 const SmallVectorImpl<MachineOperand> &Cond) const;
222 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
224 // Predication support.
225 virtual bool isPredicated(const MachineInstr *MI) const;
227 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
228 int PIdx = MI->findFirstPredOperandIdx();
229 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
234 bool PredicateInstruction(MachineInstr *MI,
235 const SmallVectorImpl<MachineOperand> &Pred) const;
238 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
239 const SmallVectorImpl<MachineOperand> &Pred2) const;
241 virtual bool DefinesPredicate(MachineInstr *MI,
242 std::vector<MachineOperand> &Pred) const;
244 /// GetInstSize - Returns the size of the specified MachineInstr.
246 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
248 /// Return true if the instruction is a register to register move and return
249 /// the source and dest operands and their sub-register indices by reference.
250 virtual bool isMoveInstr(const MachineInstr &MI,
251 unsigned &SrcReg, unsigned &DstReg,
252 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
254 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
255 int &FrameIndex) const;
256 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
257 int &FrameIndex) const;
259 virtual bool copyRegToReg(MachineBasicBlock &MBB,
260 MachineBasicBlock::iterator I,
261 unsigned DestReg, unsigned SrcReg,
262 const TargetRegisterClass *DestRC,
263 const TargetRegisterClass *SrcRC) const;
264 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator MBBI,
266 unsigned SrcReg, bool isKill, int FrameIndex,
267 const TargetRegisterClass *RC) const;
269 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
270 SmallVectorImpl<MachineOperand> &Addr,
271 const TargetRegisterClass *RC,
272 SmallVectorImpl<MachineInstr*> &NewMIs) const;
274 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator MBBI,
276 unsigned DestReg, int FrameIndex,
277 const TargetRegisterClass *RC) const;
279 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
280 SmallVectorImpl<MachineOperand> &Addr,
281 const TargetRegisterClass *RC,
282 SmallVectorImpl<MachineInstr*> &NewMIs) const;
284 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
285 const SmallVectorImpl<unsigned> &Ops) const;
287 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
289 const SmallVectorImpl<unsigned> &Ops,
290 int FrameIndex) const;
292 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
294 const SmallVectorImpl<unsigned> &Ops,
295 MachineInstr* LoadMI) const;