1 //===- ARMBaseInstrInfo.h - ARM Base Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMBASEINSTRUCTIONINFO_H
15 #define ARMBASEINSTRUCTIONINFO_H
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/Target/TargetInstrInfo.h"
23 class ARMBaseRegisterInfo;
25 /// ARMII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
30 //===------------------------------------------------------------------===//
33 //===------------------------------------------------------------------===//
34 // This four-bit field describes the addressing mode used.
47 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
51 AddrModeT2_pc = 14, // +/- i12 for pc relative data
52 AddrModeT2_i8s4 = 15, // i8 * 4
54 // Size* - Flags to keep track of the size of an instruction.
56 SizeMask = 7 << SizeShift,
57 SizeSpecial = 1, // 0 byte pseudo or special case.
62 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
63 // and store ops only. Generic "updating" flag is used for ld/st multiple.
65 IndexModeMask = 3 << IndexModeShift,
70 //===------------------------------------------------------------------===//
71 // Instruction encoding formats.
74 FormMask = 0x3f << FormShift,
76 // Pseudo instructions
77 Pseudo = 0 << FormShift,
79 // Multiply instructions
80 MulFrm = 1 << FormShift,
82 // Branch instructions
83 BrFrm = 2 << FormShift,
84 BrMiscFrm = 3 << FormShift,
86 // Data Processing instructions
87 DPFrm = 4 << FormShift,
88 DPSoRegFrm = 5 << FormShift,
91 LdFrm = 6 << FormShift,
92 StFrm = 7 << FormShift,
93 LdMiscFrm = 8 << FormShift,
94 StMiscFrm = 9 << FormShift,
95 LdStMulFrm = 10 << FormShift,
97 LdStExFrm = 11 << FormShift,
99 // Miscellaneous arithmetic instructions
100 ArithMiscFrm = 12 << FormShift,
101 SatFrm = 13 << FormShift,
103 // Extend instructions
104 ExtFrm = 14 << FormShift,
107 VFPUnaryFrm = 15 << FormShift,
108 VFPBinaryFrm = 16 << FormShift,
109 VFPConv1Frm = 17 << FormShift,
110 VFPConv2Frm = 18 << FormShift,
111 VFPConv3Frm = 19 << FormShift,
112 VFPConv4Frm = 20 << FormShift,
113 VFPConv5Frm = 21 << FormShift,
114 VFPLdStFrm = 22 << FormShift,
115 VFPLdStMulFrm = 23 << FormShift,
116 VFPMiscFrm = 24 << FormShift,
119 ThumbFrm = 25 << FormShift,
121 // Miscelleaneous format
122 MiscFrm = 26 << FormShift,
125 NGetLnFrm = 27 << FormShift,
126 NSetLnFrm = 28 << FormShift,
127 NDupFrm = 29 << FormShift,
128 NLdStFrm = 30 << FormShift,
129 N1RegModImmFrm= 31 << FormShift,
130 N2RegFrm = 32 << FormShift,
131 NVCVTFrm = 33 << FormShift,
132 NVDupLnFrm = 34 << FormShift,
133 N2RegVShLFrm = 35 << FormShift,
134 N2RegVShRFrm = 36 << FormShift,
135 N3RegFrm = 37 << FormShift,
136 N3RegVShFrm = 38 << FormShift,
137 NVExtFrm = 39 << FormShift,
138 NVMulSLFrm = 40 << FormShift,
139 NVTBLFrm = 41 << FormShift,
141 //===------------------------------------------------------------------===//
144 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
145 // it doesn't have a Rn operand.
148 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
149 // a 16-bit Thumb instruction if certain conditions are met.
150 Xform16Bit = 1 << 16,
152 //===------------------------------------------------------------------===//
155 DomainMask = 3 << DomainShift,
156 DomainGeneral = 0 << DomainShift,
157 DomainVFP = 1 << DomainShift,
158 DomainNEON = 2 << DomainShift,
160 //===------------------------------------------------------------------===//
161 // Field shifts - such shifts are used to set field while generating
162 // machine instructions.
186 class ARMBaseInstrInfo : public TargetInstrInfoImpl {
187 const ARMSubtarget &Subtarget;
189 // Can be only subclassed.
190 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
192 // Return the non-pre/post incrementing version of 'Opc'. Return 0
193 // if there is not such an opcode.
194 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
196 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
197 MachineBasicBlock::iterator &MBBI,
198 LiveVariables *LV) const;
200 virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
201 const ARMSubtarget &getSubtarget() const { return Subtarget; }
203 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI,
205 const std::vector<CalleeSavedInfo> &CSI,
206 const TargetRegisterInfo *TRI) const;
209 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
210 MachineBasicBlock *&FBB,
211 SmallVectorImpl<MachineOperand> &Cond,
212 bool AllowModify = false) const;
213 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
214 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
215 MachineBasicBlock *FBB,
216 const SmallVectorImpl<MachineOperand> &Cond,
220 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
222 // Predication support.
223 bool isPredicated(const MachineInstr *MI) const {
224 int PIdx = MI->findFirstPredOperandIdx();
225 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
228 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
229 int PIdx = MI->findFirstPredOperandIdx();
230 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
235 bool PredicateInstruction(MachineInstr *MI,
236 const SmallVectorImpl<MachineOperand> &Pred) const;
239 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
240 const SmallVectorImpl<MachineOperand> &Pred2) const;
242 virtual bool DefinesPredicate(MachineInstr *MI,
243 std::vector<MachineOperand> &Pred) const;
245 virtual bool isPredicable(MachineInstr *MI) const;
247 /// GetInstSize - Returns the size of the specified MachineInstr.
249 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
251 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
252 int &FrameIndex) const;
253 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
254 int &FrameIndex) const;
256 virtual void copyPhysReg(MachineBasicBlock &MBB,
257 MachineBasicBlock::iterator I, DebugLoc DL,
258 unsigned DestReg, unsigned SrcReg,
261 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator MBBI,
263 unsigned SrcReg, bool isKill, int FrameIndex,
264 const TargetRegisterClass *RC,
265 const TargetRegisterInfo *TRI) const;
267 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MBBI,
269 unsigned DestReg, int FrameIndex,
270 const TargetRegisterClass *RC,
271 const TargetRegisterInfo *TRI) const;
273 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
279 virtual void reMaterialize(MachineBasicBlock &MBB,
280 MachineBasicBlock::iterator MI,
281 unsigned DestReg, unsigned SubIdx,
282 const MachineInstr *Orig,
283 const TargetRegisterInfo &TRI) const;
285 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
287 virtual bool produceSameValue(const MachineInstr *MI0,
288 const MachineInstr *MI1) const;
290 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
291 /// determine if two loads are loading from the same base address. It should
292 /// only return true if the base pointers are the same and the only
293 /// differences between the two addresses is the offset. It also returns the
294 /// offsets by reference.
295 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
296 int64_t &Offset1, int64_t &Offset2)const;
298 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
299 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should
300 /// be scheduled togther. On some targets if two loads are loading from
301 /// addresses in the same cache line, it's better if they are scheduled
302 /// together. This function takes two integers that represent the load offsets
303 /// from the common base address. It returns true if it decides it's desirable
304 /// to schedule the two loads together. "NumLoads" is the number of loads that
305 /// have already been scheduled after Load1.
306 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
307 int64_t Offset1, int64_t Offset2,
308 unsigned NumLoads) const;
310 virtual bool isSchedulingBoundary(const MachineInstr *MI,
311 const MachineBasicBlock *MBB,
312 const MachineFunction &MF) const;
314 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
315 unsigned NumInstrs, float Prob) const;
317 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,unsigned NumT,
318 MachineBasicBlock &FMBB,unsigned NumF,
319 float Probability) const;
321 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
323 float Probability) const {
324 return NumInstrs && NumInstrs == 1;
327 /// AnalyzeCompare - For a comparison instruction, return the source register
328 /// in SrcReg and the value it compares against in CmpValue. Return true if
329 /// the comparison instruction can be analyzed.
330 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
331 int &CmpMask, int &CmpValue) const;
333 /// OptimizeCompareInstr - Convert the instruction to set the zero flag so
334 /// that we can remove a "comparison with zero".
335 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
336 int CmpMask, int CmpValue,
337 MachineBasicBlock::iterator &MII) const;
339 virtual unsigned getNumMicroOps(const MachineInstr *MI,
340 const InstrItineraryData *ItinData) const;
344 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
345 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
349 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
350 return MIB.addReg(0);
354 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
355 bool isDead = false) {
356 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
360 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
361 return MIB.addReg(0);
365 bool isUncondBranchOpcode(int Opc) {
366 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
370 bool isCondBranchOpcode(int Opc) {
371 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
375 bool isJumpTableBranchOpcode(int Opc) {
376 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
377 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
381 bool isIndirectBranchOpcode(int Opc) {
382 return Opc == ARM::BRIND || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
385 /// getInstrPredicate - If instruction is predicated, returns its predicate
386 /// condition, otherwise returns AL. It also returns the condition code
387 /// register by reference.
388 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
390 int getMatchingCondBranchOpcode(int Opc);
392 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
393 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
395 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
396 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
397 unsigned DestReg, unsigned BaseReg, int NumBytes,
398 ARMCC::CondCodes Pred, unsigned PredReg,
399 const ARMBaseInstrInfo &TII);
401 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
402 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
403 unsigned DestReg, unsigned BaseReg, int NumBytes,
404 ARMCC::CondCodes Pred, unsigned PredReg,
405 const ARMBaseInstrInfo &TII);
408 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
409 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
410 /// offset could not be handled directly in MI, and return the left-over
411 /// portion by reference.
412 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
413 unsigned FrameReg, int &Offset,
414 const ARMBaseInstrInfo &TII);
416 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
417 unsigned FrameReg, int &Offset,
418 const ARMBaseInstrInfo &TII);
420 } // End llvm namespace