1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
50 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
58 llvm_unreachable("Unknown ARM register!");
59 case R0: case D0: case Q0: return 0;
60 case R1: case D1: case Q1: return 1;
61 case R2: case D2: case Q2: return 2;
62 case R3: case D3: case Q3: return 3;
63 case R4: case D4: case Q4: return 4;
64 case R5: case D5: case Q5: return 5;
65 case R6: case D6: case Q6: return 6;
66 case R7: case D7: case Q7: return 7;
67 case R8: case D8: case Q8: return 8;
68 case R9: case D9: case Q9: return 9;
69 case R10: case D10: case Q10: return 10;
70 case R11: case D11: case Q11: return 11;
71 case R12: case D12: case Q12: return 12;
72 case SP: case D13: case Q13: return 13;
73 case LR: case D14: case Q14: return 14;
74 case PC: case D15: case Q15: return 15;
93 case S0: case S1: case S2: case S3:
94 case S4: case S5: case S6: case S7:
95 case S8: case S9: case S10: case S11:
96 case S12: case S13: case S14: case S15:
97 case S16: case S17: case S18: case S19:
98 case S20: case S21: case S22: case S23:
99 case S24: case S25: case S26: case S27:
100 case S28: case S29: case S30: case S31: {
104 default: return 0; // Avoid compile time warning.
142 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143 const ARMSubtarget &sti)
144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 static const unsigned CalleeSavedRegs[] = {
152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
160 static const unsigned DarwinCalleeSavedRegs[] = {
161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
164 ARM::R11, ARM::R10, ARM::R8,
166 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
173 BitVector ARMBaseRegisterInfo::
174 getReservedRegs(const MachineFunction &MF) const {
175 // FIXME: avoid re-calculating this everytime.
176 BitVector Reserved(getNumRegs());
177 Reserved.set(ARM::SP);
178 Reserved.set(ARM::PC);
179 Reserved.set(ARM::FPSCR);
181 Reserved.set(FramePtr);
182 // Some targets reserve R9.
183 if (STI.isR9Reserved())
184 Reserved.set(ARM::R9);
188 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
189 unsigned Reg) const {
197 if (FramePtr == Reg && hasFP(MF))
201 return STI.isR9Reserved();
207 const TargetRegisterClass *
208 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
209 const TargetRegisterClass *B,
210 unsigned SubIdx) const {
218 if (A->getSize() == 8) {
219 if (B == &ARM::SPR_8RegClass)
220 return &ARM::DPR_8RegClass;
221 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
222 if (A == &ARM::DPR_8RegClass)
224 return &ARM::DPR_VFP2RegClass;
227 if (A->getSize() == 16) {
228 if (B == &ARM::SPR_8RegClass)
229 return &ARM::QPR_8RegClass;
230 return &ARM::QPR_VFP2RegClass;
233 if (A->getSize() == 32) {
234 if (B == &ARM::SPR_8RegClass)
235 return 0; // Do not allow coalescing!
236 return &ARM::QQPR_VFP2RegClass;
239 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
240 return 0; // Do not allow coalescing!
247 if (A->getSize() == 16) {
248 if (B == &ARM::DPR_VFP2RegClass)
249 return &ARM::QPR_VFP2RegClass;
250 if (B == &ARM::DPR_8RegClass)
251 return 0; // Do not allow coalescing!
255 if (A->getSize() == 32) {
256 if (B == &ARM::DPR_VFP2RegClass)
257 return &ARM::QQPR_VFP2RegClass;
258 if (B == &ARM::DPR_8RegClass)
259 return 0; // Do not allow coalescing!
263 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
264 if (B != &ARM::DPRRegClass)
265 return 0; // Do not allow coalescing!
272 // D sub-registers of QQQQ registers.
273 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
275 return 0; // Do not allow coalescing!
281 if (A->getSize() == 32) {
282 if (B == &ARM::QPR_VFP2RegClass)
283 return &ARM::QQPR_VFP2RegClass;
284 if (B == &ARM::QPR_8RegClass)
285 return 0; // Do not allow coalescing!
289 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
290 if (B == &ARM::QPRRegClass)
292 return 0; // Do not allow coalescing!
296 // Q sub-registers of QQQQ registers.
297 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
299 return 0; // Do not allow coalescing!
306 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
307 SmallVectorImpl<unsigned> &SubIndices,
308 unsigned &NewSubIdx) const {
310 unsigned Size = RC->getSize() * 8;
314 NewSubIdx = 0; // Whole register.
315 unsigned NumRegs = SubIndices.size();
317 // 8 D registers -> 1 QQQQ register.
318 return (Size == 512 &&
319 SubIndices[0] == ARM::dsub_0 &&
320 SubIndices[1] == ARM::dsub_1 &&
321 SubIndices[2] == ARM::dsub_2 &&
322 SubIndices[3] == ARM::dsub_3 &&
323 SubIndices[4] == ARM::dsub_4 &&
324 SubIndices[5] == ARM::dsub_5 &&
325 SubIndices[6] == ARM::dsub_6 &&
326 SubIndices[7] == ARM::dsub_7);
327 } else if (NumRegs == 4) {
328 if (SubIndices[0] == ARM::qsub_0) {
329 // 4 Q registers -> 1 QQQQ register.
330 return (Size == 512 &&
331 SubIndices[1] == ARM::qsub_1 &&
332 SubIndices[2] == ARM::qsub_2 &&
333 SubIndices[3] == ARM::qsub_3);
334 } else if (SubIndices[0] == ARM::dsub_0) {
335 // 4 D registers -> 1 QQ register.
337 SubIndices[1] == ARM::dsub_1 &&
338 SubIndices[2] == ARM::dsub_2 &&
339 SubIndices[3] == ARM::dsub_3) {
341 NewSubIdx = ARM::qqsub_0;
344 } else if (SubIndices[0] == ARM::dsub_4) {
345 // 4 D registers -> 1 QQ register (2nd).
347 SubIndices[1] == ARM::dsub_5 &&
348 SubIndices[2] == ARM::dsub_6 &&
349 SubIndices[3] == ARM::dsub_7) {
350 NewSubIdx = ARM::qqsub_1;
353 } else if (SubIndices[0] == ARM::ssub_0) {
354 // 4 S registers -> 1 Q register.
356 SubIndices[1] == ARM::ssub_1 &&
357 SubIndices[2] == ARM::ssub_2 &&
358 SubIndices[3] == ARM::ssub_3) {
360 NewSubIdx = ARM::qsub_0;
364 } else if (NumRegs == 2) {
365 if (SubIndices[0] == ARM::qsub_0) {
366 // 2 Q registers -> 1 QQ register.
367 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
369 NewSubIdx = ARM::qqsub_0;
372 } else if (SubIndices[0] == ARM::qsub_2) {
373 // 2 Q registers -> 1 QQ register (2nd).
374 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
375 NewSubIdx = ARM::qqsub_1;
378 } else if (SubIndices[0] == ARM::dsub_0) {
379 // 2 D registers -> 1 Q register.
380 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
382 NewSubIdx = ARM::qsub_0;
385 } else if (SubIndices[0] == ARM::dsub_2) {
386 // 2 D registers -> 1 Q register (2nd).
387 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
388 NewSubIdx = ARM::qsub_1;
391 } else if (SubIndices[0] == ARM::dsub_4) {
392 // 2 D registers -> 1 Q register (3rd).
393 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
394 NewSubIdx = ARM::qsub_2;
397 } else if (SubIndices[0] == ARM::dsub_6) {
398 // 2 D registers -> 1 Q register (3rd).
399 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
400 NewSubIdx = ARM::qsub_3;
403 } else if (SubIndices[0] == ARM::ssub_0) {
404 // 2 S registers -> 1 D register.
405 if (SubIndices[1] == ARM::ssub_1) {
407 NewSubIdx = ARM::dsub_0;
410 } else if (SubIndices[0] == ARM::ssub_2) {
411 // 2 S registers -> 1 D register (2nd).
412 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
413 NewSubIdx = ARM::dsub_1;
422 const TargetRegisterClass *
423 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
424 return ARM::GPRRegisterClass;
427 /// getAllocationOrder - Returns the register allocation order for a specified
428 /// register class in the form of a pair of TargetRegisterClass iterators.
429 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
430 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
431 unsigned HintType, unsigned HintReg,
432 const MachineFunction &MF) const {
433 // Alternative register allocation orders when favoring even / odd registers
434 // of register pairs.
436 // No FP, R9 is available.
437 static const unsigned GPREven1[] = {
438 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
439 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
442 static const unsigned GPROdd1[] = {
443 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
444 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
448 // FP is R7, R9 is available.
449 static const unsigned GPREven2[] = {
450 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
451 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
454 static const unsigned GPROdd2[] = {
455 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
456 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
460 // FP is R11, R9 is available.
461 static const unsigned GPREven3[] = {
462 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
463 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
466 static const unsigned GPROdd3[] = {
467 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
468 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
472 // No FP, R9 is not available.
473 static const unsigned GPREven4[] = {
474 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
475 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
478 static const unsigned GPROdd4[] = {
479 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
480 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
484 // FP is R7, R9 is not available.
485 static const unsigned GPREven5[] = {
486 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
487 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
490 static const unsigned GPROdd5[] = {
491 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
492 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
496 // FP is R11, R9 is not available.
497 static const unsigned GPREven6[] = {
498 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
499 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
501 static const unsigned GPROdd6[] = {
502 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
503 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
507 if (HintType == ARMRI::RegPairEven) {
508 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
509 // It's no longer possible to fulfill this hint. Return the default
511 return std::make_pair(RC->allocation_order_begin(MF),
512 RC->allocation_order_end(MF));
515 if (!STI.isR9Reserved())
516 return std::make_pair(GPREven1,
517 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
519 return std::make_pair(GPREven4,
520 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
521 } else if (FramePtr == ARM::R7) {
522 if (!STI.isR9Reserved())
523 return std::make_pair(GPREven2,
524 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
526 return std::make_pair(GPREven5,
527 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
528 } else { // FramePtr == ARM::R11
529 if (!STI.isR9Reserved())
530 return std::make_pair(GPREven3,
531 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
533 return std::make_pair(GPREven6,
534 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
536 } else if (HintType == ARMRI::RegPairOdd) {
537 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
538 // It's no longer possible to fulfill this hint. Return the default
540 return std::make_pair(RC->allocation_order_begin(MF),
541 RC->allocation_order_end(MF));
544 if (!STI.isR9Reserved())
545 return std::make_pair(GPROdd1,
546 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
548 return std::make_pair(GPROdd4,
549 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
550 } else if (FramePtr == ARM::R7) {
551 if (!STI.isR9Reserved())
552 return std::make_pair(GPROdd2,
553 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
555 return std::make_pair(GPROdd5,
556 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
557 } else { // FramePtr == ARM::R11
558 if (!STI.isR9Reserved())
559 return std::make_pair(GPROdd3,
560 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
562 return std::make_pair(GPROdd6,
563 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
566 return std::make_pair(RC->allocation_order_begin(MF),
567 RC->allocation_order_end(MF));
570 /// ResolveRegAllocHint - Resolves the specified register allocation hint
571 /// to a physical register. Returns the physical register if it is successful.
573 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
574 const MachineFunction &MF) const {
575 if (Reg == 0 || !isPhysicalRegister(Reg))
579 else if (Type == (unsigned)ARMRI::RegPairOdd)
581 return getRegisterPairOdd(Reg, MF);
582 else if (Type == (unsigned)ARMRI::RegPairEven)
584 return getRegisterPairEven(Reg, MF);
589 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
590 MachineFunction &MF) const {
591 MachineRegisterInfo *MRI = &MF.getRegInfo();
592 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
593 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
594 Hint.first == (unsigned)ARMRI::RegPairEven) &&
595 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
596 // If 'Reg' is one of the even / odd register pair and it's now changed
597 // (e.g. coalesced) into a different register. The other register of the
598 // pair allocation hint must be updated to reflect the relationship
600 unsigned OtherReg = Hint.second;
601 Hint = MRI->getRegAllocationHint(OtherReg);
602 if (Hint.second == Reg)
603 // Make sure the pair has not already divorced.
604 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
608 /// hasFP - Return true if the specified function should have a dedicated frame
609 /// pointer register. This is true if the function has variable sized allocas
610 /// or if frame pointer elimination is disabled.
612 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
613 // Mac OS X requires FP not to be clobbered for backtracing purpose.
614 if (STI.isTargetDarwin())
617 const MachineFrameInfo *MFI = MF.getFrameInfo();
618 // Always eliminate non-leaf frame pointers.
619 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
620 needsStackRealignment(MF) ||
621 MFI->hasVarSizedObjects() ||
622 MFI->isFrameAddressTaken());
625 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
626 const MachineFrameInfo *MFI = MF.getFrameInfo();
627 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
628 return (RealignStack &&
629 !AFI->isThumb1OnlyFunction() &&
630 !MFI->hasVarSizedObjects());
633 bool ARMBaseRegisterInfo::
634 needsStackRealignment(const MachineFunction &MF) const {
635 const MachineFrameInfo *MFI = MF.getFrameInfo();
636 const Function *F = MF.getFunction();
637 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
638 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
639 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
640 F->hasFnAttr(Attribute::StackAlignment));
642 // FIXME: Currently we don't support stack realignment for functions with
643 // variable-sized allocas.
644 // FIXME: It's more complicated than this...
645 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
647 "Stack realignment in presense of dynamic allocas is not supported");
649 // FIXME: This probably isn't the right place for this.
650 if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
652 "Stack realignment in thumb1 functions is not supported");
654 return requiresRealignment && canRealignStack(MF);
657 bool ARMBaseRegisterInfo::
658 cannotEliminateFrame(const MachineFunction &MF) const {
659 const MachineFrameInfo *MFI = MF.getFrameInfo();
660 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
662 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
663 || needsStackRealignment(MF);
666 /// estimateStackSize - Estimate and return the size of the frame.
667 static unsigned estimateStackSize(MachineFunction &MF) {
668 const MachineFrameInfo *FFI = MF.getFrameInfo();
670 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
671 int FixedOff = -FFI->getObjectOffset(i);
672 if (FixedOff > Offset) Offset = FixedOff;
674 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
675 if (FFI->isDeadObjectIndex(i))
677 Offset += FFI->getObjectSize(i);
678 unsigned Align = FFI->getObjectAlignment(i);
679 // Adjust to alignment boundary
680 Offset = (Offset+Align-1)/Align*Align;
682 return (unsigned)Offset;
685 /// estimateRSStackSizeLimit - Look at each instruction that references stack
686 /// frames and return the stack size limit beyond which some of these
687 /// instructions will require a scratch register during their expansion later.
689 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
690 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
691 unsigned Limit = (1 << 12) - 1;
692 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
693 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
695 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
696 if (!I->getOperand(i).isFI()) continue;
698 // When using ADDri to get the address of a stack object, 255 is the
699 // largest offset guaranteed to fit in the immediate offset.
700 if (I->getOpcode() == ARM::ADDri) {
701 Limit = std::min(Limit, (1U << 8) - 1);
705 // Otherwise check the addressing mode.
706 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
707 case ARMII::AddrMode3:
708 case ARMII::AddrModeT2_i8:
709 Limit = std::min(Limit, (1U << 8) - 1);
711 case ARMII::AddrMode5:
712 case ARMII::AddrModeT2_i8s4:
713 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
715 case ARMII::AddrModeT2_i12:
716 // i12 supports only positive offset so these will be converted to
717 // i8 opcodes. See llvm::rewriteT2FrameIndex.
718 if (hasFP(MF) && AFI->hasStackFrame())
719 Limit = std::min(Limit, (1U << 8) - 1);
721 case ARMII::AddrMode6:
722 // Addressing mode 6 (load/store) instructions can't encode an
723 // immediate offset for stack references.
728 break; // At most one FI per instruction
736 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
737 const ARMBaseInstrInfo &TII) {
739 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
741 const MachineBasicBlock &MBB = *MBBI;
742 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
744 FnSize += TII.GetInstSizeInBytes(I);
750 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
751 RegScavenger *RS) const {
752 // This tells PEI to spill the FP as if it is any other callee-save register
753 // to take advantage the eliminateFrameIndex machinery. This also ensures it
754 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
755 // to combine multiple loads / stores.
756 bool CanEliminateFrame = true;
757 bool CS1Spilled = false;
758 bool LRSpilled = false;
759 unsigned NumGPRSpills = 0;
760 SmallVector<unsigned, 4> UnspilledCS1GPRs;
761 SmallVector<unsigned, 4> UnspilledCS2GPRs;
762 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
763 MachineFrameInfo *MFI = MF.getFrameInfo();
765 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
767 // FIXME: It will be better just to find spare register here.
768 if (needsStackRealignment(MF) &&
769 AFI->isThumb2Function())
770 MF.getRegInfo().setPhysRegUsed(ARM::R4);
772 // Spill LR if Thumb1 function uses variable length argument lists.
773 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
774 MF.getRegInfo().setPhysRegUsed(ARM::LR);
776 // Don't spill FP if the frame can be eliminated. This is determined
777 // by scanning the callee-save registers to see if any is used.
778 const unsigned *CSRegs = getCalleeSavedRegs();
779 for (unsigned i = 0; CSRegs[i]; ++i) {
780 unsigned Reg = CSRegs[i];
781 bool Spilled = false;
782 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
783 AFI->setCSRegisterIsSpilled(Reg);
785 CanEliminateFrame = false;
787 // Check alias registers too.
788 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
789 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
791 CanEliminateFrame = false;
796 if (!ARM::GPRRegisterClass->contains(Reg))
802 if (!STI.isTargetDarwin()) {
809 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
824 if (!STI.isTargetDarwin()) {
825 UnspilledCS1GPRs.push_back(Reg);
835 UnspilledCS1GPRs.push_back(Reg);
838 UnspilledCS2GPRs.push_back(Reg);
844 bool ForceLRSpill = false;
845 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
846 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
847 // Force LR to be spilled if the Thumb function size is > 2048. This enables
848 // use of BL to implement far jump. If it turns out that it's not needed
849 // then the branch fix up path will undo it.
850 if (FnSize >= (1 << 11)) {
851 CanEliminateFrame = false;
856 // If any of the stack slot references may be out of range of an immediate
857 // offset, make sure a register (or a spill slot) is available for the
858 // register scavenger. Note that if we're indexing off the frame pointer, the
859 // effective stack size is 4 bytes larger since the FP points to the stack
860 // slot of the previous FP. Also, if we have variable sized objects in the
861 // function, stack slot references will often be negative, and some of
862 // our instructions are positive-offset only, so conservatively consider
863 // that case to want a spill slot (or register) as well. Similarly, if
864 // the function adjusts the stack pointer during execution and the
865 // adjustments aren't already part of our stack size estimate, our offset
866 // calculations may be off, so be conservative.
867 // FIXME: We could add logic to be more precise about negative offsets
868 // and which instructions will need a scratch register for them. Is it
869 // worth the effort and added fragility?
872 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
873 estimateRSStackSizeLimit(MF)))
874 || MFI->hasVarSizedObjects()
875 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
877 bool ExtraCSSpill = false;
878 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
879 AFI->setHasStackFrame(true);
881 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
882 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
883 if (!LRSpilled && CS1Spilled) {
884 MF.getRegInfo().setPhysRegUsed(ARM::LR);
885 AFI->setCSRegisterIsSpilled(ARM::LR);
887 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
888 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
889 ForceLRSpill = false;
894 MF.getRegInfo().setPhysRegUsed(FramePtr);
898 // If stack and double are 8-byte aligned and we are spilling an odd number
899 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
900 // the integer and double callee save areas.
901 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
902 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
903 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
904 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
905 unsigned Reg = UnspilledCS1GPRs[i];
906 // Don't spill high register if the function is thumb1
907 if (!AFI->isThumb1OnlyFunction() ||
908 isARMLowRegister(Reg) || Reg == ARM::LR) {
909 MF.getRegInfo().setPhysRegUsed(Reg);
910 AFI->setCSRegisterIsSpilled(Reg);
911 if (!isReservedReg(MF, Reg))
916 } else if (!UnspilledCS2GPRs.empty() &&
917 !AFI->isThumb1OnlyFunction()) {
918 unsigned Reg = UnspilledCS2GPRs.front();
919 MF.getRegInfo().setPhysRegUsed(Reg);
920 AFI->setCSRegisterIsSpilled(Reg);
921 if (!isReservedReg(MF, Reg))
926 // Estimate if we might need to scavenge a register at some point in order
927 // to materialize a stack offset. If so, either spill one additional
928 // callee-saved register or reserve a special spill slot to facilitate
929 // register scavenging. Thumb1 needs a spill slot for stack pointer
930 // adjustments also, even when the frame itself is small.
931 if (BigStack && !ExtraCSSpill) {
932 // If any non-reserved CS register isn't spilled, just spill one or two
933 // extra. That should take care of it!
934 unsigned NumExtras = TargetAlign / 4;
935 SmallVector<unsigned, 2> Extras;
936 while (NumExtras && !UnspilledCS1GPRs.empty()) {
937 unsigned Reg = UnspilledCS1GPRs.back();
938 UnspilledCS1GPRs.pop_back();
939 if (!isReservedReg(MF, Reg) &&
940 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
942 Extras.push_back(Reg);
946 // For non-Thumb1 functions, also check for hi-reg CS registers
947 if (!AFI->isThumb1OnlyFunction()) {
948 while (NumExtras && !UnspilledCS2GPRs.empty()) {
949 unsigned Reg = UnspilledCS2GPRs.back();
950 UnspilledCS2GPRs.pop_back();
951 if (!isReservedReg(MF, Reg)) {
952 Extras.push_back(Reg);
957 if (Extras.size() && NumExtras == 0) {
958 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
959 MF.getRegInfo().setPhysRegUsed(Extras[i]);
960 AFI->setCSRegisterIsSpilled(Extras[i]);
962 } else if (!AFI->isThumb1OnlyFunction()) {
963 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
964 // closest to SP or frame pointer.
965 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
966 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
974 MF.getRegInfo().setPhysRegUsed(ARM::LR);
975 AFI->setCSRegisterIsSpilled(ARM::LR);
976 AFI->setLRIsSpilledForFarJump(true);
980 unsigned ARMBaseRegisterInfo::getRARegister() const {
985 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
991 // Provide a base+offset reference to an FI slot for debug info. It's the
992 // same as what we use for resolving the code-gen references for now.
993 // FIXME: This can go wrong when references are SP-relative and simple call
994 // frames aren't used.
996 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
997 unsigned &FrameReg) const {
998 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
1002 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
1006 const MachineFrameInfo *MFI = MF.getFrameInfo();
1007 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1008 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1009 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1010 bool isFixed = MFI->isFixedObjectIndex(FI);
1014 if (AFI->isGPRCalleeSavedArea1Frame(FI))
1015 return Offset - AFI->getGPRCalleeSavedArea1Offset();
1016 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1017 return Offset - AFI->getGPRCalleeSavedArea2Offset();
1018 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1019 return Offset - AFI->getDPRCalleeSavedAreaOffset();
1021 // When dynamically realigning the stack, use the frame pointer for
1022 // parameters, and the stack pointer for locals.
1023 if (needsStackRealignment(MF)) {
1024 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1026 FrameReg = getFrameRegister(MF);
1032 // If there is a frame pointer, use it when we can.
1033 if (hasFP(MF) && AFI->hasStackFrame()) {
1034 // Use frame pointer to reference fixed objects. Use it for locals if
1035 // there are VLAs (and thus the SP isn't reliable as a base).
1036 if (isFixed || MFI->hasVarSizedObjects()) {
1037 FrameReg = getFrameRegister(MF);
1039 } else if (AFI->isThumb2Function()) {
1040 // In Thumb2 mode, the negative offset is very limited. Try to avoid
1041 // out of range references.
1042 if (FPOffset >= -255 && FPOffset < 0) {
1043 FrameReg = getFrameRegister(MF);
1046 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1047 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1048 FrameReg = getFrameRegister(MF);
1056 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1059 return getFrameIndexReference(MF, FI, FrameReg);
1062 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1063 llvm_unreachable("What is the exception register");
1067 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1068 llvm_unreachable("What is the exception handler register");
1072 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1073 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1076 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1077 const MachineFunction &MF) const {
1080 // Return 0 if either register of the pair is a special register.
1089 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
1091 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1093 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1165 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1166 const MachineFunction &MF) const {
1169 // Return 0 if either register of the pair is a special register.
1178 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1180 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1182 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1254 /// emitLoadConstPool - Emits a load from constpool to materialize the
1255 /// specified immediate.
1256 void ARMBaseRegisterInfo::
1257 emitLoadConstPool(MachineBasicBlock &MBB,
1258 MachineBasicBlock::iterator &MBBI,
1260 unsigned DestReg, unsigned SubIdx, int Val,
1261 ARMCC::CondCodes Pred,
1262 unsigned PredReg) const {
1263 MachineFunction &MF = *MBB.getParent();
1264 MachineConstantPool *ConstantPool = MF.getConstantPool();
1266 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1267 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1269 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1270 .addReg(DestReg, getDefRegState(true), SubIdx)
1271 .addConstantPoolIndex(Idx)
1272 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1275 bool ARMBaseRegisterInfo::
1276 requiresRegisterScavenging(const MachineFunction &MF) const {
1280 bool ARMBaseRegisterInfo::
1281 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1285 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1286 // not required, we reserve argument space for call sites in the function
1287 // immediately on entry to the current function. This eliminates the need for
1288 // add/sub sp brackets around call sites. Returns true if the call frame is
1289 // included as part of the stack frame.
1290 bool ARMBaseRegisterInfo::
1291 hasReservedCallFrame(const MachineFunction &MF) const {
1292 const MachineFrameInfo *FFI = MF.getFrameInfo();
1293 unsigned CFSize = FFI->getMaxCallFrameSize();
1294 // It's not always a good idea to include the call frame as part of the
1295 // stack frame. ARM (especially Thumb) has small immediate offset to
1296 // address the stack frame. So a large call frame can cause poor codegen
1297 // and may even makes it impossible to scavenge a register.
1298 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1301 return !MF.getFrameInfo()->hasVarSizedObjects();
1304 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1305 // call frame pseudos can be simplified. Unlike most targets, having a FP
1306 // is not sufficient here since we still may reference some objects via SP
1307 // even when FP is available in Thumb2 mode.
1308 bool ARMBaseRegisterInfo::
1309 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1310 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1314 emitSPUpdate(bool isARM,
1315 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1316 DebugLoc dl, const ARMBaseInstrInfo &TII,
1318 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1320 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1321 Pred, PredReg, TII);
1323 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1324 Pred, PredReg, TII);
1328 void ARMBaseRegisterInfo::
1329 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1330 MachineBasicBlock::iterator I) const {
1331 if (!hasReservedCallFrame(MF)) {
1332 // If we have alloca, convert as follows:
1333 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1334 // ADJCALLSTACKUP -> add, sp, sp, amount
1335 MachineInstr *Old = I;
1336 DebugLoc dl = Old->getDebugLoc();
1337 unsigned Amount = Old->getOperand(0).getImm();
1339 // We need to keep the stack aligned properly. To do this, we round the
1340 // amount of space needed for the outgoing arguments up to the next
1341 // alignment boundary.
1342 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1343 Amount = (Amount+Align-1)/Align*Align;
1345 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1346 assert(!AFI->isThumb1OnlyFunction() &&
1347 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1348 bool isARM = !AFI->isThumbFunction();
1350 // Replace the pseudo instruction with a new instruction...
1351 unsigned Opc = Old->getOpcode();
1352 int PIdx = Old->findFirstPredOperandIdx();
1353 ARMCC::CondCodes Pred = (PIdx == -1)
1354 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1355 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1356 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1357 unsigned PredReg = Old->getOperand(2).getReg();
1358 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1360 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1361 unsigned PredReg = Old->getOperand(3).getReg();
1362 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1363 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1371 int64_t ARMBaseRegisterInfo::
1372 getFrameIndexInstrOffset(MachineInstr *MI, int Idx) const {
1373 const TargetInstrDesc &Desc = MI->getDesc();
1374 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1375 int64_t InstrOffs = 0;;
1377 unsigned ImmIdx = 0;
1379 case ARMII::AddrModeT2_i8:
1380 case ARMII::AddrModeT2_i12:
1381 // i8 supports only negative, and i12 supports only positive, so
1382 // based on Offset sign, consider the appropriate instruction
1383 InstrOffs = MI->getOperand(Idx+1).getImm();
1386 case ARMII::AddrMode5: {
1387 // VFP address mode.
1388 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1389 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1390 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1391 InstrOffs = -InstrOffs;
1395 case ARMII::AddrMode2: {
1397 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1398 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1399 InstrOffs = -InstrOffs;
1402 case ARMII::AddrMode3: {
1404 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1405 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1406 InstrOffs = -InstrOffs;
1409 case ARMII::AddrModeT1_s: {
1411 InstrOffs = MI->getOperand(ImmIdx).getImm();
1416 llvm_unreachable("Unsupported addressing mode!");
1420 return InstrOffs * Scale;
1423 /// needsFrameBaseReg - Returns true if the instruction's frame index
1424 /// reference would be better served by a base register other than FP
1425 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1426 /// references it should create new base registers for.
1427 bool ARMBaseRegisterInfo::
1428 needsFrameBaseReg(MachineInstr *MI, unsigned operand) const {
1429 assert (MI->getOperand(operand).isFI() &&
1430 "needsFrameBaseReg() called on non Frame Index operand!");
1432 // It's the load/store FI references that cause issues, as it can be difficult
1433 // to materialize the offset if it won't fit in the literal field. Estimate
1434 // based on the size of the local frame and some conservative assumptions
1435 // about the rest of the stack frame (note, this is pre-regalloc, so
1436 // we don't know everything for certain yet) whether this offset is likely
1437 // to be out of range of the immediate. Return true if so.
1439 // FIXME: For testing, return true for all loads/stores and false for
1440 // everything else. We want to create lots of base regs to shake out bugs.
1441 unsigned Opc = MI->getOpcode();
1444 case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1445 case ARM::STR: case ARM::STRH: case ARM::STRB:
1446 case ARM::t2LDRi12: case ARM::t2LDRi8:
1447 case ARM::t2STRi12: case ARM::t2STRi8:
1448 case ARM::VLDRS: case ARM::VLDRD:
1449 case ARM::VSTRS: case ARM::VSTRD:
1450 case ARM::tSTRspi: case ARM::tLDRspi:
1457 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1458 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1459 void ARMBaseRegisterInfo::
1460 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1461 int FrameIdx, int64_t Offset) const {
1462 ARMFunctionInfo *AFI =
1463 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1464 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1465 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1467 MachineInstrBuilder MIB =
1468 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1469 .addFrameIndex(FrameIdx).addImm(Offset);
1470 if (!AFI->isThumb1OnlyFunction())
1471 AddDefaultCC(AddDefaultPred(MIB));
1475 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1476 unsigned BaseReg, int64_t Offset) const {
1477 MachineInstr &MI = *I;
1478 MachineBasicBlock &MBB = *MI.getParent();
1479 MachineFunction &MF = *MBB.getParent();
1480 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1481 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1484 assert(!AFI->isThumb1OnlyFunction() &&
1485 "This resolveFrameIndex does not support Thumb1!");
1487 while (!MI.getOperand(i).isFI()) {
1489 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1492 if (!AFI->isThumbFunction())
1493 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1495 assert(AFI->isThumb2Function());
1496 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1498 assert (Done && "Unable to resolve frame index!");
1501 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1502 int64_t Offset) const {
1503 const TargetInstrDesc &Desc = MI->getDesc();
1504 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1507 while (!MI->getOperand(i).isFI()) {
1509 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1512 // AddrMode4 and AddrMode6 cannot handle any offset.
1513 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1516 unsigned NumBits = 0;
1518 unsigned ImmIdx = 0;
1520 bool isSigned = true;
1522 case ARMII::AddrModeT2_i8:
1523 case ARMII::AddrModeT2_i12:
1524 // i8 supports only negative, and i12 supports only positive, so
1525 // based on Offset sign, consider the appropriate instruction
1526 InstrOffs = MI->getOperand(i+1).getImm();
1535 case ARMII::AddrMode5: {
1536 // VFP address mode.
1537 const MachineOperand &OffOp = MI->getOperand(i+1);
1538 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1539 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1540 InstrOffs = -InstrOffs;
1545 case ARMII::AddrMode2: {
1547 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1548 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1549 InstrOffs = -InstrOffs;
1553 case ARMII::AddrMode3: {
1555 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1556 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1557 InstrOffs = -InstrOffs;
1561 case ARMII::AddrModeT1_s: {
1563 InstrOffs = MI->getOperand(ImmIdx).getImm();
1570 llvm_unreachable("Unsupported addressing mode!");
1574 Offset += InstrOffs * Scale;
1575 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1576 if (isSigned && Offset < 0)
1579 unsigned Mask = (1 << NumBits) - 1;
1580 if ((unsigned)Offset <= Mask * Scale)
1587 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1588 int SPAdj, FrameIndexValue *Value,
1589 RegScavenger *RS) const {
1591 MachineInstr &MI = *II;
1592 MachineBasicBlock &MBB = *MI.getParent();
1593 MachineFunction &MF = *MBB.getParent();
1594 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1595 assert(!AFI->isThumb1OnlyFunction() &&
1596 "This eliminateFrameIndex does not support Thumb1!");
1598 while (!MI.getOperand(i).isFI()) {
1600 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1603 int FrameIndex = MI.getOperand(i).getIndex();
1606 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1608 // Special handling of dbg_value instructions.
1609 if (MI.isDebugValue()) {
1610 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1611 MI.getOperand(i+1).ChangeToImmediate(Offset);
1615 // Modify MI as necessary to handle as much of 'Offset' as possible
1617 if (!AFI->isThumbFunction())
1618 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1620 assert(AFI->isThumb2Function());
1621 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1626 // If we get here, the immediate doesn't fit into the instruction. We folded
1627 // as much as possible above, handle the rest, providing a register that is
1630 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1631 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1632 "This code isn't needed if offset already handled!");
1634 unsigned ScratchReg = 0;
1635 int PIdx = MI.findFirstPredOperandIdx();
1636 ARMCC::CondCodes Pred = (PIdx == -1)
1637 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1638 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1640 // Must be addrmode4/6.
1641 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1643 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1645 Value->first = FrameReg; // use the frame register as a kind indicator
1646 Value->second = Offset;
1648 if (!AFI->isThumbFunction())
1649 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1650 Offset, Pred, PredReg, TII);
1652 assert(AFI->isThumb2Function());
1653 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1654 Offset, Pred, PredReg, TII);
1656 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1657 if (!ReuseFrameIndexVals)
1663 /// Move iterator past the next bunch of callee save load / store ops for
1664 /// the particular spill area (1: integer area 1, 2: integer area 2,
1665 /// 3: fp area, 0: don't care).
1666 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1667 MachineBasicBlock::iterator &MBBI,
1668 int Opc1, int Opc2, unsigned Area,
1669 const ARMSubtarget &STI) {
1670 while (MBBI != MBB.end() &&
1671 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1672 MBBI->getOperand(1).isFI()) {
1675 unsigned Category = 0;
1676 switch (MBBI->getOperand(0).getReg()) {
1677 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1681 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1682 Category = STI.isTargetDarwin() ? 2 : 1;
1684 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1685 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1692 if (Done || Category != Area)
1700 void ARMBaseRegisterInfo::
1701 emitPrologue(MachineFunction &MF) const {
1702 MachineBasicBlock &MBB = MF.front();
1703 MachineBasicBlock::iterator MBBI = MBB.begin();
1704 MachineFrameInfo *MFI = MF.getFrameInfo();
1705 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1706 assert(!AFI->isThumb1OnlyFunction() &&
1707 "This emitPrologue does not support Thumb1!");
1708 bool isARM = !AFI->isThumbFunction();
1709 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1710 unsigned NumBytes = MFI->getStackSize();
1711 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1712 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1714 // Determine the sizes of each callee-save spill areas and record which frame
1715 // belongs to which callee-save spill areas.
1716 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1717 int FramePtrSpillFI = 0;
1719 // Allocate the vararg register save area. This is not counted in NumBytes.
1721 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1723 if (!AFI->hasStackFrame()) {
1725 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1729 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1730 unsigned Reg = CSI[i].getReg();
1731 int FI = CSI[i].getFrameIdx();
1738 if (Reg == FramePtr)
1739 FramePtrSpillFI = FI;
1740 AFI->addGPRCalleeSavedArea1Frame(FI);
1747 if (Reg == FramePtr)
1748 FramePtrSpillFI = FI;
1749 if (STI.isTargetDarwin()) {
1750 AFI->addGPRCalleeSavedArea2Frame(FI);
1753 AFI->addGPRCalleeSavedArea1Frame(FI);
1758 AFI->addDPRCalleeSavedAreaFrame(FI);
1763 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1764 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1765 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1767 // Set FP to point to the stack slot that contains the previous FP.
1768 // For Darwin, FP is R7, which has now been stored in spill area 1.
1769 // Otherwise, if this is not Darwin, all the callee-saved registers go
1770 // into spill area 1, including the FP in R11. In either case, it is
1771 // now safe to emit this assignment.
1772 bool HasFP = hasFP(MF);
1774 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1775 MachineInstrBuilder MIB =
1776 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1777 .addFrameIndex(FramePtrSpillFI).addImm(0);
1778 AddDefaultCC(AddDefaultPred(MIB));
1781 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1782 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1784 // Build the new SUBri to adjust SP for FP callee-save spill area.
1785 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1786 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1788 // Determine starting offsets of spill areas.
1789 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1790 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1791 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1793 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1795 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1796 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1797 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1799 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1800 NumBytes = DPRCSOffset;
1802 // Adjust SP after all the callee-save spills.
1803 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1805 AFI->setShouldRestoreSPFromFP(true);
1808 if (STI.isTargetELF() && hasFP(MF)) {
1809 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1810 AFI->getFramePtrSpillOffset());
1811 AFI->setShouldRestoreSPFromFP(true);
1814 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1815 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1816 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1818 // If we need dynamic stack realignment, do it here.
1819 if (needsStackRealignment(MF)) {
1820 unsigned MaxAlign = MFI->getMaxAlignment();
1821 assert (!AFI->isThumb1OnlyFunction());
1822 if (!AFI->isThumbFunction()) {
1823 // Emit bic sp, sp, MaxAlign
1824 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1825 TII.get(ARM::BICri), ARM::SP)
1826 .addReg(ARM::SP, RegState::Kill)
1827 .addImm(MaxAlign-1)));
1829 // We cannot use sp as source/dest register here, thus we're emitting the
1830 // following sequence:
1832 // bic r4, r4, MaxAlign
1834 // FIXME: It will be better just to find spare register here.
1835 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1836 .addReg(ARM::SP, RegState::Kill);
1837 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1838 TII.get(ARM::t2BICri), ARM::R4)
1839 .addReg(ARM::R4, RegState::Kill)
1840 .addImm(MaxAlign-1)));
1841 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1842 .addReg(ARM::R4, RegState::Kill);
1845 AFI->setShouldRestoreSPFromFP(true);
1848 // If the frame has variable sized objects then the epilogue must restore
1850 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1851 AFI->setShouldRestoreSPFromFP(true);
1854 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1855 for (unsigned i = 0; CSRegs[i]; ++i)
1856 if (Reg == CSRegs[i])
1861 static bool isCSRestore(MachineInstr *MI,
1862 const ARMBaseInstrInfo &TII,
1863 const unsigned *CSRegs) {
1864 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1865 MI->getOpcode() == (int)ARM::LDR ||
1866 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1867 MI->getOperand(1).isFI() &&
1868 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1871 void ARMBaseRegisterInfo::
1872 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1873 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1874 assert(MBBI->getDesc().isReturn() &&
1875 "Can only insert epilog into returning blocks");
1876 unsigned RetOpcode = MBBI->getOpcode();
1877 DebugLoc dl = MBBI->getDebugLoc();
1878 MachineFrameInfo *MFI = MF.getFrameInfo();
1879 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1880 assert(!AFI->isThumb1OnlyFunction() &&
1881 "This emitEpilogue does not support Thumb1!");
1882 bool isARM = !AFI->isThumbFunction();
1884 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1885 int NumBytes = (int)MFI->getStackSize();
1887 if (!AFI->hasStackFrame()) {
1889 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1891 // Unwind MBBI to point to first LDR / VLDRD.
1892 const unsigned *CSRegs = getCalleeSavedRegs();
1893 if (MBBI != MBB.begin()) {
1896 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1897 if (!isCSRestore(MBBI, TII, CSRegs))
1901 // Move SP to start of FP callee save spill area.
1902 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1903 AFI->getGPRCalleeSavedArea2Size() +
1904 AFI->getDPRCalleeSavedAreaSize());
1906 // Reset SP based on frame pointer only if the stack frame extends beyond
1907 // frame pointer stack slot or target is ELF and the function has FP.
1908 if (AFI->shouldRestoreSPFromFP()) {
1909 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1912 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1915 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1920 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1921 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1923 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1926 } else if (NumBytes)
1927 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1929 // Move SP to start of integer callee save spill area 2.
1930 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1931 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1933 // Move SP to start of integer callee save spill area 1.
1934 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1935 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1937 // Move SP to SP upon entry to the function.
1938 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1939 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1942 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1943 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1944 // Tail call return: adjust the stack pointer and jump to callee.
1945 MBBI = prior(MBB.end());
1946 MachineOperand &JumpTarget = MBBI->getOperand(0);
1948 // Jump to label or value in register.
1949 if (RetOpcode == ARM::TCRETURNdi) {
1950 BuildMI(MBB, MBBI, dl,
1951 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1952 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1953 JumpTarget.getTargetFlags());
1954 } else if (RetOpcode == ARM::TCRETURNdiND) {
1955 BuildMI(MBB, MBBI, dl,
1956 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1957 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1958 JumpTarget.getTargetFlags());
1959 } else if (RetOpcode == ARM::TCRETURNri) {
1960 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1961 addReg(JumpTarget.getReg(), RegState::Kill);
1962 } else if (RetOpcode == ARM::TCRETURNriND) {
1963 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1964 addReg(JumpTarget.getReg(), RegState::Kill);
1967 MachineInstr *NewMI = prior(MBBI);
1968 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1969 NewMI->addOperand(MBBI->getOperand(i));
1971 // Delete the pseudo instruction TCRETURN.
1976 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1979 #include "ARMGenRegisterInfo.inc"