1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47 cl::desc("Force use of virtual base registers for stack load/store"));
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50 cl::desc("Enable pre-regalloc stack frame index allocation"));
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56 const ARMSubtarget &sti)
57 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 static const unsigned CalleeSavedRegs[] = {
66 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
69 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
74 static const unsigned DarwinCalleeSavedRegs[] = {
75 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::R11, ARM::R10, ARM::R8,
80 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // FIXME: avoid re-calculating this everytime.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107 unsigned Reg) const {
108 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
116 if (hasBasePointer(MF))
121 if (FramePtr == Reg && TFI->hasFP(MF))
125 return STI.isR9Reserved();
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133 const TargetRegisterClass *B,
134 unsigned SubIdx) const {
142 if (A->getSize() == 8) {
143 if (B == &ARM::SPR_8RegClass)
144 return &ARM::DPR_8RegClass;
145 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146 if (A == &ARM::DPR_8RegClass)
148 return &ARM::DPR_VFP2RegClass;
151 if (A->getSize() == 16) {
152 if (B == &ARM::SPR_8RegClass)
153 return &ARM::QPR_8RegClass;
154 return &ARM::QPR_VFP2RegClass;
157 if (A->getSize() == 32) {
158 if (B == &ARM::SPR_8RegClass)
159 return 0; // Do not allow coalescing!
160 return &ARM::QQPR_VFP2RegClass;
163 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164 return 0; // Do not allow coalescing!
171 if (A->getSize() == 16) {
172 if (B == &ARM::DPR_VFP2RegClass)
173 return &ARM::QPR_VFP2RegClass;
174 if (B == &ARM::DPR_8RegClass)
175 return 0; // Do not allow coalescing!
179 if (A->getSize() == 32) {
180 if (B == &ARM::DPR_VFP2RegClass)
181 return &ARM::QQPR_VFP2RegClass;
182 if (B == &ARM::DPR_8RegClass)
183 return 0; // Do not allow coalescing!
187 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188 if (B != &ARM::DPRRegClass)
189 return 0; // Do not allow coalescing!
196 // D sub-registers of QQQQ registers.
197 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
205 if (A->getSize() == 32) {
206 if (B == &ARM::QPR_VFP2RegClass)
207 return &ARM::QQPR_VFP2RegClass;
208 if (B == &ARM::QPR_8RegClass)
209 return 0; // Do not allow coalescing!
213 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214 if (B == &ARM::QPRRegClass)
216 return 0; // Do not allow coalescing!
220 // Q sub-registers of QQQQ registers.
221 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
223 return 0; // Do not allow coalescing!
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231 SmallVectorImpl<unsigned> &SubIndices,
232 unsigned &NewSubIdx) const {
234 unsigned Size = RC->getSize() * 8;
238 NewSubIdx = 0; // Whole register.
239 unsigned NumRegs = SubIndices.size();
241 // 8 D registers -> 1 QQQQ register.
242 return (Size == 512 &&
243 SubIndices[0] == ARM::dsub_0 &&
244 SubIndices[1] == ARM::dsub_1 &&
245 SubIndices[2] == ARM::dsub_2 &&
246 SubIndices[3] == ARM::dsub_3 &&
247 SubIndices[4] == ARM::dsub_4 &&
248 SubIndices[5] == ARM::dsub_5 &&
249 SubIndices[6] == ARM::dsub_6 &&
250 SubIndices[7] == ARM::dsub_7);
251 } else if (NumRegs == 4) {
252 if (SubIndices[0] == ARM::qsub_0) {
253 // 4 Q registers -> 1 QQQQ register.
254 return (Size == 512 &&
255 SubIndices[1] == ARM::qsub_1 &&
256 SubIndices[2] == ARM::qsub_2 &&
257 SubIndices[3] == ARM::qsub_3);
258 } else if (SubIndices[0] == ARM::dsub_0) {
259 // 4 D registers -> 1 QQ register.
261 SubIndices[1] == ARM::dsub_1 &&
262 SubIndices[2] == ARM::dsub_2 &&
263 SubIndices[3] == ARM::dsub_3) {
265 NewSubIdx = ARM::qqsub_0;
268 } else if (SubIndices[0] == ARM::dsub_4) {
269 // 4 D registers -> 1 QQ register (2nd).
271 SubIndices[1] == ARM::dsub_5 &&
272 SubIndices[2] == ARM::dsub_6 &&
273 SubIndices[3] == ARM::dsub_7) {
274 NewSubIdx = ARM::qqsub_1;
277 } else if (SubIndices[0] == ARM::ssub_0) {
278 // 4 S registers -> 1 Q register.
280 SubIndices[1] == ARM::ssub_1 &&
281 SubIndices[2] == ARM::ssub_2 &&
282 SubIndices[3] == ARM::ssub_3) {
284 NewSubIdx = ARM::qsub_0;
288 } else if (NumRegs == 2) {
289 if (SubIndices[0] == ARM::qsub_0) {
290 // 2 Q registers -> 1 QQ register.
291 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
293 NewSubIdx = ARM::qqsub_0;
296 } else if (SubIndices[0] == ARM::qsub_2) {
297 // 2 Q registers -> 1 QQ register (2nd).
298 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299 NewSubIdx = ARM::qqsub_1;
302 } else if (SubIndices[0] == ARM::dsub_0) {
303 // 2 D registers -> 1 Q register.
304 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
306 NewSubIdx = ARM::qsub_0;
309 } else if (SubIndices[0] == ARM::dsub_2) {
310 // 2 D registers -> 1 Q register (2nd).
311 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312 NewSubIdx = ARM::qsub_1;
315 } else if (SubIndices[0] == ARM::dsub_4) {
316 // 2 D registers -> 1 Q register (3rd).
317 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318 NewSubIdx = ARM::qsub_2;
321 } else if (SubIndices[0] == ARM::dsub_6) {
322 // 2 D registers -> 1 Q register (3rd).
323 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324 NewSubIdx = ARM::qsub_3;
327 } else if (SubIndices[0] == ARM::ssub_0) {
328 // 2 S registers -> 1 D register.
329 if (SubIndices[1] == ARM::ssub_1) {
331 NewSubIdx = ARM::dsub_0;
334 } else if (SubIndices[0] == ARM::ssub_2) {
335 // 2 S registers -> 1 D register (2nd).
336 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337 NewSubIdx = ARM::dsub_1;
346 const TargetRegisterClass *
347 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
348 return ARM::GPRRegisterClass;
352 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
353 MachineFunction &MF) const {
354 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
356 switch (RC->getID()) {
359 case ARM::tGPRRegClassID:
360 return TFI->hasFP(MF) ? 4 : 5;
361 case ARM::GPRRegClassID: {
362 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
363 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
365 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
366 case ARM::DPRRegClassID:
371 /// getAllocationOrder - Returns the register allocation order for a specified
372 /// register class in the form of a pair of TargetRegisterClass iterators.
373 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
374 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
375 unsigned HintType, unsigned HintReg,
376 const MachineFunction &MF) const {
377 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
378 // Alternative register allocation orders when favoring even / odd registers
379 // of register pairs.
381 // No FP, R9 is available.
382 static const unsigned GPREven1[] = {
383 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
384 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
387 static const unsigned GPROdd1[] = {
388 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
389 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
393 // FP is R7, R9 is available.
394 static const unsigned GPREven2[] = {
395 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
396 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
399 static const unsigned GPROdd2[] = {
400 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
401 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
405 // FP is R11, R9 is available.
406 static const unsigned GPREven3[] = {
407 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
408 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
411 static const unsigned GPROdd3[] = {
412 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
413 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
417 // No FP, R9 is not available.
418 static const unsigned GPREven4[] = {
419 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
420 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
423 static const unsigned GPROdd4[] = {
424 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
425 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
429 // FP is R7, R9 is not available.
430 static const unsigned GPREven5[] = {
431 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
432 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
435 static const unsigned GPROdd5[] = {
436 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
437 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
441 // FP is R11, R9 is not available.
442 static const unsigned GPREven6[] = {
443 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
444 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
446 static const unsigned GPROdd6[] = {
447 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
448 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
451 // We only support even/odd hints for GPR and rGPR.
452 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
453 return std::make_pair(RC->allocation_order_begin(MF),
454 RC->allocation_order_end(MF));
456 if (HintType == ARMRI::RegPairEven) {
457 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
458 // It's no longer possible to fulfill this hint. Return the default
460 return std::make_pair(RC->allocation_order_begin(MF),
461 RC->allocation_order_end(MF));
463 if (!TFI->hasFP(MF)) {
464 if (!STI.isR9Reserved())
465 return std::make_pair(GPREven1,
466 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
468 return std::make_pair(GPREven4,
469 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
470 } else if (FramePtr == ARM::R7) {
471 if (!STI.isR9Reserved())
472 return std::make_pair(GPREven2,
473 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
475 return std::make_pair(GPREven5,
476 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
477 } else { // FramePtr == ARM::R11
478 if (!STI.isR9Reserved())
479 return std::make_pair(GPREven3,
480 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
482 return std::make_pair(GPREven6,
483 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
485 } else if (HintType == ARMRI::RegPairOdd) {
486 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
487 // It's no longer possible to fulfill this hint. Return the default
489 return std::make_pair(RC->allocation_order_begin(MF),
490 RC->allocation_order_end(MF));
492 if (!TFI->hasFP(MF)) {
493 if (!STI.isR9Reserved())
494 return std::make_pair(GPROdd1,
495 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
497 return std::make_pair(GPROdd4,
498 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
499 } else if (FramePtr == ARM::R7) {
500 if (!STI.isR9Reserved())
501 return std::make_pair(GPROdd2,
502 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
504 return std::make_pair(GPROdd5,
505 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
506 } else { // FramePtr == ARM::R11
507 if (!STI.isR9Reserved())
508 return std::make_pair(GPROdd3,
509 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
511 return std::make_pair(GPROdd6,
512 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
515 return std::make_pair(RC->allocation_order_begin(MF),
516 RC->allocation_order_end(MF));
519 /// ResolveRegAllocHint - Resolves the specified register allocation hint
520 /// to a physical register. Returns the physical register if it is successful.
522 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
523 const MachineFunction &MF) const {
524 if (Reg == 0 || !isPhysicalRegister(Reg))
528 else if (Type == (unsigned)ARMRI::RegPairOdd)
530 return getRegisterPairOdd(Reg, MF);
531 else if (Type == (unsigned)ARMRI::RegPairEven)
533 return getRegisterPairEven(Reg, MF);
538 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
539 MachineFunction &MF) const {
540 MachineRegisterInfo *MRI = &MF.getRegInfo();
541 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
542 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
543 Hint.first == (unsigned)ARMRI::RegPairEven) &&
544 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
545 // If 'Reg' is one of the even / odd register pair and it's now changed
546 // (e.g. coalesced) into a different register. The other register of the
547 // pair allocation hint must be updated to reflect the relationship
549 unsigned OtherReg = Hint.second;
550 Hint = MRI->getRegAllocationHint(OtherReg);
551 if (Hint.second == Reg)
552 // Make sure the pair has not already divorced.
553 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
557 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
558 const MachineFrameInfo *MFI = MF.getFrameInfo();
559 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
561 if (!EnableBasePointer)
564 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
567 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
568 // negative range for ldr/str (255), and thumb1 is positive offsets only.
569 // It's going to be better to use the SP or Base Pointer instead. When there
570 // are variable sized objects, we can't reference off of the SP, so we
571 // reserve a Base Pointer.
572 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
573 // Conservatively estimate whether the negative offset from the frame
574 // pointer will be sufficient to reach. If a function has a smallish
575 // frame, it's less likely to have lots of spills and callee saved
576 // space, so it's all more likely to be within range of the frame pointer.
577 // If it's wrong, the scavenger will still enable access to work, it just
579 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
587 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
588 const MachineFrameInfo *MFI = MF.getFrameInfo();
589 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
590 // We can't realign the stack if:
591 // 1. Dynamic stack realignment is explicitly disabled,
592 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
593 // 3. There are VLAs in the function and the base pointer is disabled.
594 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
595 (!MFI->hasVarSizedObjects() || EnableBasePointer));
598 bool ARMBaseRegisterInfo::
599 needsStackRealignment(const MachineFunction &MF) const {
600 const MachineFrameInfo *MFI = MF.getFrameInfo();
601 const Function *F = MF.getFunction();
602 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
603 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
604 F->hasFnAttr(Attribute::StackAlignment));
606 return requiresRealignment && canRealignStack(MF);
609 bool ARMBaseRegisterInfo::
610 cannotEliminateFrame(const MachineFunction &MF) const {
611 const MachineFrameInfo *MFI = MF.getFrameInfo();
612 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
614 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
615 || needsStackRealignment(MF);
618 unsigned ARMBaseRegisterInfo::getRARegister() const {
623 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
624 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
631 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
632 llvm_unreachable("What is the exception register");
636 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
637 llvm_unreachable("What is the exception handler register");
641 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
642 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
645 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
646 const MachineFunction &MF) const {
649 // Return 0 if either register of the pair is a special register.
658 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
661 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
663 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
735 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
736 const MachineFunction &MF) const {
739 // Return 0 if either register of the pair is a special register.
748 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
751 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
753 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
825 /// emitLoadConstPool - Emits a load from constpool to materialize the
826 /// specified immediate.
827 void ARMBaseRegisterInfo::
828 emitLoadConstPool(MachineBasicBlock &MBB,
829 MachineBasicBlock::iterator &MBBI,
831 unsigned DestReg, unsigned SubIdx, int Val,
832 ARMCC::CondCodes Pred,
833 unsigned PredReg, unsigned MIFlags) const {
834 MachineFunction &MF = *MBB.getParent();
835 MachineConstantPool *ConstantPool = MF.getConstantPool();
837 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
838 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
840 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
841 .addReg(DestReg, getDefRegState(true), SubIdx)
842 .addConstantPoolIndex(Idx)
843 .addImm(0).addImm(Pred).addReg(PredReg)
844 .setMIFlags(MIFlags);
847 bool ARMBaseRegisterInfo::
848 requiresRegisterScavenging(const MachineFunction &MF) const {
852 bool ARMBaseRegisterInfo::
853 requiresFrameIndexScavenging(const MachineFunction &MF) const {
857 bool ARMBaseRegisterInfo::
858 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
859 return EnableLocalStackAlloc;
863 emitSPUpdate(bool isARM,
864 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
865 DebugLoc dl, const ARMBaseInstrInfo &TII,
867 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
869 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
872 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
877 void ARMBaseRegisterInfo::
878 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
879 MachineBasicBlock::iterator I) const {
880 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
881 if (!TFI->hasReservedCallFrame(MF)) {
882 // If we have alloca, convert as follows:
883 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
884 // ADJCALLSTACKUP -> add, sp, sp, amount
885 MachineInstr *Old = I;
886 DebugLoc dl = Old->getDebugLoc();
887 unsigned Amount = Old->getOperand(0).getImm();
889 // We need to keep the stack aligned properly. To do this, we round the
890 // amount of space needed for the outgoing arguments up to the next
891 // alignment boundary.
892 unsigned Align = TFI->getStackAlignment();
893 Amount = (Amount+Align-1)/Align*Align;
895 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
896 assert(!AFI->isThumb1OnlyFunction() &&
897 "This eliminateCallFramePseudoInstr does not support Thumb1!");
898 bool isARM = !AFI->isThumbFunction();
900 // Replace the pseudo instruction with a new instruction...
901 unsigned Opc = Old->getOpcode();
902 int PIdx = Old->findFirstPredOperandIdx();
903 ARMCC::CondCodes Pred = (PIdx == -1)
904 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
905 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
906 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
907 unsigned PredReg = Old->getOperand(2).getReg();
908 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
910 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
911 unsigned PredReg = Old->getOperand(3).getReg();
912 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
913 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
920 int64_t ARMBaseRegisterInfo::
921 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
922 const TargetInstrDesc &Desc = MI->getDesc();
923 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
924 int64_t InstrOffs = 0;;
928 case ARMII::AddrModeT2_i8:
929 case ARMII::AddrModeT2_i12:
930 case ARMII::AddrMode_i12:
931 InstrOffs = MI->getOperand(Idx+1).getImm();
934 case ARMII::AddrMode5: {
936 const MachineOperand &OffOp = MI->getOperand(Idx+1);
937 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
938 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
939 InstrOffs = -InstrOffs;
943 case ARMII::AddrMode2: {
945 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
946 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
947 InstrOffs = -InstrOffs;
950 case ARMII::AddrMode3: {
952 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
953 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
954 InstrOffs = -InstrOffs;
957 case ARMII::AddrModeT1_s: {
959 InstrOffs = MI->getOperand(ImmIdx).getImm();
964 llvm_unreachable("Unsupported addressing mode!");
968 return InstrOffs * Scale;
971 /// needsFrameBaseReg - Returns true if the instruction's frame index
972 /// reference would be better served by a base register other than FP
973 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
974 /// references it should create new base registers for.
975 bool ARMBaseRegisterInfo::
976 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
977 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
978 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
981 // It's the load/store FI references that cause issues, as it can be difficult
982 // to materialize the offset if it won't fit in the literal field. Estimate
983 // based on the size of the local frame and some conservative assumptions
984 // about the rest of the stack frame (note, this is pre-regalloc, so
985 // we don't know everything for certain yet) whether this offset is likely
986 // to be out of range of the immediate. Return true if so.
988 // We only generate virtual base registers for loads and stores, so
989 // return false for everything else.
990 unsigned Opc = MI->getOpcode();
992 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
993 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
994 case ARM::t2LDRi12: case ARM::t2LDRi8:
995 case ARM::t2STRi12: case ARM::t2STRi8:
996 case ARM::VLDRS: case ARM::VLDRD:
997 case ARM::VSTRS: case ARM::VSTRD:
998 case ARM::tSTRspi: case ARM::tLDRspi:
999 if (ForceAllBaseRegAlloc)
1006 // Without a virtual base register, if the function has variable sized
1007 // objects, all fixed-size local references will be via the frame pointer,
1008 // Approximate the offset and see if it's legal for the instruction.
1009 // Note that the incoming offset is based on the SP value at function entry,
1010 // so it'll be negative.
1011 MachineFunction &MF = *MI->getParent()->getParent();
1012 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1013 MachineFrameInfo *MFI = MF.getFrameInfo();
1014 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1016 // Estimate an offset from the frame pointer.
1017 // Conservatively assume all callee-saved registers get pushed. R4-R6
1018 // will be earlier than the FP, so we ignore those.
1020 int64_t FPOffset = Offset - 8;
1021 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1022 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1024 // Estimate an offset from the stack pointer.
1025 // The incoming offset is relating to the SP at the start of the function,
1026 // but when we access the local it'll be relative to the SP after local
1027 // allocation, so adjust our SP-relative offset by that allocation size.
1029 Offset += MFI->getLocalFrameSize();
1030 // Assume that we'll have at least some spill slots allocated.
1031 // FIXME: This is a total SWAG number. We should run some statistics
1032 // and pick a real one.
1033 Offset += 128; // 128 bytes of spill slots
1035 // If there is a frame pointer, try using it.
1036 // The FP is only available if there is no dynamic realignment. We
1037 // don't know for sure yet whether we'll need that, so we guess based
1038 // on whether there are any local variables that would trigger it.
1039 unsigned StackAlign = TFI->getStackAlignment();
1040 if (TFI->hasFP(MF) &&
1041 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1042 if (isFrameOffsetLegal(MI, FPOffset))
1045 // If we can reference via the stack pointer, try that.
1046 // FIXME: This (and the code that resolves the references) can be improved
1047 // to only disallow SP relative references in the live range of
1048 // the VLA(s). In practice, it's unclear how much difference that
1049 // would make, but it may be worth doing.
1050 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1053 // The offset likely isn't legal, we want to allocate a virtual base register.
1057 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1058 /// be a pointer to FrameIdx at the beginning of the basic block.
1059 void ARMBaseRegisterInfo::
1060 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1061 unsigned BaseReg, int FrameIdx,
1062 int64_t Offset) const {
1063 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1064 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1065 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1067 MachineBasicBlock::iterator Ins = MBB->begin();
1068 DebugLoc DL; // Defaults to "unknown"
1069 if (Ins != MBB->end())
1070 DL = Ins->getDebugLoc();
1072 MachineInstrBuilder MIB =
1073 BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)
1074 .addFrameIndex(FrameIdx).addImm(Offset);
1076 if (!AFI->isThumb1OnlyFunction())
1077 AddDefaultCC(AddDefaultPred(MIB));
1081 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1082 unsigned BaseReg, int64_t Offset) const {
1083 MachineInstr &MI = *I;
1084 MachineBasicBlock &MBB = *MI.getParent();
1085 MachineFunction &MF = *MBB.getParent();
1086 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1087 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1090 assert(!AFI->isThumb1OnlyFunction() &&
1091 "This resolveFrameIndex does not support Thumb1!");
1093 while (!MI.getOperand(i).isFI()) {
1095 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1098 if (!AFI->isThumbFunction())
1099 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1101 assert(AFI->isThumb2Function());
1102 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1104 assert (Done && "Unable to resolve frame index!");
1107 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1108 int64_t Offset) const {
1109 const TargetInstrDesc &Desc = MI->getDesc();
1110 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1113 while (!MI->getOperand(i).isFI()) {
1115 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1118 // AddrMode4 and AddrMode6 cannot handle any offset.
1119 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1122 unsigned NumBits = 0;
1124 bool isSigned = true;
1126 case ARMII::AddrModeT2_i8:
1127 case ARMII::AddrModeT2_i12:
1128 // i8 supports only negative, and i12 supports only positive, so
1129 // based on Offset sign, consider the appropriate instruction
1138 case ARMII::AddrMode5:
1139 // VFP address mode.
1143 case ARMII::AddrMode_i12:
1144 case ARMII::AddrMode2:
1147 case ARMII::AddrMode3:
1150 case ARMII::AddrModeT1_s:
1156 llvm_unreachable("Unsupported addressing mode!");
1160 Offset += getFrameIndexInstrOffset(MI, i);
1161 // Make sure the offset is encodable for instructions that scale the
1163 if ((Offset & (Scale-1)) != 0)
1166 if (isSigned && Offset < 0)
1169 unsigned Mask = (1 << NumBits) - 1;
1170 if ((unsigned)Offset <= Mask * Scale)
1177 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1178 int SPAdj, RegScavenger *RS) const {
1180 MachineInstr &MI = *II;
1181 MachineBasicBlock &MBB = *MI.getParent();
1182 MachineFunction &MF = *MBB.getParent();
1183 const ARMFrameLowering *TFI =
1184 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1185 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1186 assert(!AFI->isThumb1OnlyFunction() &&
1187 "This eliminateFrameIndex does not support Thumb1!");
1189 while (!MI.getOperand(i).isFI()) {
1191 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1194 int FrameIndex = MI.getOperand(i).getIndex();
1197 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1199 // Special handling of dbg_value instructions.
1200 if (MI.isDebugValue()) {
1201 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1202 MI.getOperand(i+1).ChangeToImmediate(Offset);
1206 // Modify MI as necessary to handle as much of 'Offset' as possible
1208 if (!AFI->isThumbFunction())
1209 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1211 assert(AFI->isThumb2Function());
1212 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1217 // If we get here, the immediate doesn't fit into the instruction. We folded
1218 // as much as possible above, handle the rest, providing a register that is
1221 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1222 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1223 "This code isn't needed if offset already handled!");
1225 unsigned ScratchReg = 0;
1226 int PIdx = MI.findFirstPredOperandIdx();
1227 ARMCC::CondCodes Pred = (PIdx == -1)
1228 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1229 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1231 // Must be addrmode4/6.
1232 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1234 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1235 if (!AFI->isThumbFunction())
1236 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1237 Offset, Pred, PredReg, TII);
1239 assert(AFI->isThumb2Function());
1240 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1241 Offset, Pred, PredReg, TII);
1243 // Update the original instruction to use the scratch register.
1244 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1245 if (MI.getOpcode() == ARM::t2ADDrSPi)
1246 MI.setDesc(TII.get(ARM::t2ADDri));
1247 else if (MI.getOpcode() == ARM::t2SUBrSPi)
1248 MI.setDesc(TII.get(ARM::t2SUBri));
1252 #include "ARMGenRegisterInfo.inc"