1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RegisterScavenging.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/CommandLine.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
47 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
48 cl::desc("Force use of virtual base registers for stack load/store"));
50 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
51 cl::desc("Enable pre-regalloc stack frame index allocation"));
53 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &sti)
58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
66 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
70 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
72 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
75 BitVector ARMBaseRegisterInfo::
76 getReservedRegs(const MachineFunction &MF) const {
77 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79 // FIXME: avoid re-calculating this every time.
80 BitVector Reserved(getNumRegs());
81 Reserved.set(ARM::SP);
82 Reserved.set(ARM::PC);
83 Reserved.set(ARM::FPSCR);
85 Reserved.set(FramePtr);
86 if (hasBasePointer(MF))
87 Reserved.set(BasePtr);
88 // Some targets reserve R9.
89 if (STI.isR9Reserved())
90 Reserved.set(ARM::R9);
91 // Reserve D16-D31 if the subtarget doesn't support them.
92 if (!STI.hasVFP3() || STI.hasD16()) {
93 assert(ARM::D31 == ARM::D16 + 15);
94 for (unsigned i = 0; i != 16; ++i)
95 Reserved.set(ARM::D16 + i);
100 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
101 unsigned Reg) const {
102 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
110 if (hasBasePointer(MF))
115 if (FramePtr == Reg && TFI->hasFP(MF))
119 return STI.isR9Reserved();
126 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
127 SmallVectorImpl<unsigned> &SubIndices,
128 unsigned &NewSubIdx) const {
130 unsigned Size = RC->getSize() * 8;
134 NewSubIdx = 0; // Whole register.
135 unsigned NumRegs = SubIndices.size();
137 // 8 D registers -> 1 QQQQ register.
138 return (Size == 512 &&
139 SubIndices[0] == ARM::dsub_0 &&
140 SubIndices[1] == ARM::dsub_1 &&
141 SubIndices[2] == ARM::dsub_2 &&
142 SubIndices[3] == ARM::dsub_3 &&
143 SubIndices[4] == ARM::dsub_4 &&
144 SubIndices[5] == ARM::dsub_5 &&
145 SubIndices[6] == ARM::dsub_6 &&
146 SubIndices[7] == ARM::dsub_7);
147 } else if (NumRegs == 4) {
148 if (SubIndices[0] == ARM::qsub_0) {
149 // 4 Q registers -> 1 QQQQ register.
150 return (Size == 512 &&
151 SubIndices[1] == ARM::qsub_1 &&
152 SubIndices[2] == ARM::qsub_2 &&
153 SubIndices[3] == ARM::qsub_3);
154 } else if (SubIndices[0] == ARM::dsub_0) {
155 // 4 D registers -> 1 QQ register.
157 SubIndices[1] == ARM::dsub_1 &&
158 SubIndices[2] == ARM::dsub_2 &&
159 SubIndices[3] == ARM::dsub_3) {
161 NewSubIdx = ARM::qqsub_0;
164 } else if (SubIndices[0] == ARM::dsub_4) {
165 // 4 D registers -> 1 QQ register (2nd).
167 SubIndices[1] == ARM::dsub_5 &&
168 SubIndices[2] == ARM::dsub_6 &&
169 SubIndices[3] == ARM::dsub_7) {
170 NewSubIdx = ARM::qqsub_1;
173 } else if (SubIndices[0] == ARM::ssub_0) {
174 // 4 S registers -> 1 Q register.
176 SubIndices[1] == ARM::ssub_1 &&
177 SubIndices[2] == ARM::ssub_2 &&
178 SubIndices[3] == ARM::ssub_3) {
180 NewSubIdx = ARM::qsub_0;
184 } else if (NumRegs == 2) {
185 if (SubIndices[0] == ARM::qsub_0) {
186 // 2 Q registers -> 1 QQ register.
187 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
189 NewSubIdx = ARM::qqsub_0;
192 } else if (SubIndices[0] == ARM::qsub_2) {
193 // 2 Q registers -> 1 QQ register (2nd).
194 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
195 NewSubIdx = ARM::qqsub_1;
198 } else if (SubIndices[0] == ARM::dsub_0) {
199 // 2 D registers -> 1 Q register.
200 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
202 NewSubIdx = ARM::qsub_0;
205 } else if (SubIndices[0] == ARM::dsub_2) {
206 // 2 D registers -> 1 Q register (2nd).
207 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
208 NewSubIdx = ARM::qsub_1;
211 } else if (SubIndices[0] == ARM::dsub_4) {
212 // 2 D registers -> 1 Q register (3rd).
213 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
214 NewSubIdx = ARM::qsub_2;
217 } else if (SubIndices[0] == ARM::dsub_6) {
218 // 2 D registers -> 1 Q register (3rd).
219 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
220 NewSubIdx = ARM::qsub_3;
223 } else if (SubIndices[0] == ARM::ssub_0) {
224 // 2 S registers -> 1 D register.
225 if (SubIndices[1] == ARM::ssub_1) {
227 NewSubIdx = ARM::dsub_0;
230 } else if (SubIndices[0] == ARM::ssub_2) {
231 // 2 S registers -> 1 D register (2nd).
232 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
233 NewSubIdx = ARM::dsub_1;
241 const TargetRegisterClass*
242 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
244 const TargetRegisterClass *Super = RC;
245 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
247 switch (Super->getID()) {
248 case ARM::GPRRegClassID:
249 case ARM::SPRRegClassID:
250 case ARM::DPRRegClassID:
251 case ARM::QPRRegClassID:
252 case ARM::QQPRRegClassID:
253 case ARM::QQQQPRRegClassID:
261 const TargetRegisterClass *
262 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
264 return &ARM::GPRRegClass;
267 const TargetRegisterClass *
268 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
269 if (RC == &ARM::CCRRegClass)
270 return 0; // Can't copy CCR registers.
275 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
276 MachineFunction &MF) const {
277 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
279 switch (RC->getID()) {
282 case ARM::tGPRRegClassID:
283 return TFI->hasFP(MF) ? 4 : 5;
284 case ARM::GPRRegClassID: {
285 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
286 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
288 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
289 case ARM::DPRRegClassID:
294 /// getRawAllocationOrder - Returns the register allocation order for a
295 /// specified register class with a target-dependent hint.
297 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
298 unsigned HintType, unsigned HintReg,
299 const MachineFunction &MF) const {
300 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
301 // Alternative register allocation orders when favoring even / odd registers
302 // of register pairs.
304 // No FP, R9 is available.
305 static const uint16_t GPREven1[] = {
306 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
307 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
310 static const uint16_t GPROdd1[] = {
311 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
312 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
316 // FP is R7, R9 is available.
317 static const uint16_t GPREven2[] = {
318 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
322 static const uint16_t GPROdd2[] = {
323 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
328 // FP is R11, R9 is available.
329 static const uint16_t GPREven3[] = {
330 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
331 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
334 static const uint16_t GPROdd3[] = {
335 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
336 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
340 // No FP, R9 is not available.
341 static const uint16_t GPREven4[] = {
342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
343 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
346 static const uint16_t GPROdd4[] = {
347 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
348 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
352 // FP is R7, R9 is not available.
353 static const uint16_t GPREven5[] = {
354 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
358 static const uint16_t GPROdd5[] = {
359 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
364 // FP is R11, R9 is not available.
365 static const uint16_t GPREven6[] = {
366 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
367 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
369 static const uint16_t GPROdd6[] = {
370 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
371 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
374 // We only support even/odd hints for GPR and rGPR.
375 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
376 return RC->getRawAllocationOrder(MF);
378 if (HintType == ARMRI::RegPairEven) {
379 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
380 // It's no longer possible to fulfill this hint. Return the default
382 return RC->getRawAllocationOrder(MF);
384 if (!TFI->hasFP(MF)) {
385 if (!STI.isR9Reserved())
386 return makeArrayRef(GPREven1);
388 return makeArrayRef(GPREven4);
389 } else if (FramePtr == ARM::R7) {
390 if (!STI.isR9Reserved())
391 return makeArrayRef(GPREven2);
393 return makeArrayRef(GPREven5);
394 } else { // FramePtr == ARM::R11
395 if (!STI.isR9Reserved())
396 return makeArrayRef(GPREven3);
398 return makeArrayRef(GPREven6);
400 } else if (HintType == ARMRI::RegPairOdd) {
401 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
402 // It's no longer possible to fulfill this hint. Return the default
404 return RC->getRawAllocationOrder(MF);
406 if (!TFI->hasFP(MF)) {
407 if (!STI.isR9Reserved())
408 return makeArrayRef(GPROdd1);
410 return makeArrayRef(GPROdd4);
411 } else if (FramePtr == ARM::R7) {
412 if (!STI.isR9Reserved())
413 return makeArrayRef(GPROdd2);
415 return makeArrayRef(GPROdd5);
416 } else { // FramePtr == ARM::R11
417 if (!STI.isR9Reserved())
418 return makeArrayRef(GPROdd3);
420 return makeArrayRef(GPROdd6);
423 return RC->getRawAllocationOrder(MF);
426 /// ResolveRegAllocHint - Resolves the specified register allocation hint
427 /// to a physical register. Returns the physical register if it is successful.
429 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
430 const MachineFunction &MF) const {
431 if (Reg == 0 || !isPhysicalRegister(Reg))
435 else if (Type == (unsigned)ARMRI::RegPairOdd)
437 return getRegisterPairOdd(Reg, MF);
438 else if (Type == (unsigned)ARMRI::RegPairEven)
440 return getRegisterPairEven(Reg, MF);
445 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
446 MachineFunction &MF) const {
447 MachineRegisterInfo *MRI = &MF.getRegInfo();
448 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
449 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
450 Hint.first == (unsigned)ARMRI::RegPairEven) &&
451 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
452 // If 'Reg' is one of the even / odd register pair and it's now changed
453 // (e.g. coalesced) into a different register. The other register of the
454 // pair allocation hint must be updated to reflect the relationship
456 unsigned OtherReg = Hint.second;
457 Hint = MRI->getRegAllocationHint(OtherReg);
458 if (Hint.second == Reg)
459 // Make sure the pair has not already divorced.
460 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
465 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
466 // CortexA9 has a Write-after-write hazard for NEON registers.
467 if (!STI.isCortexA9())
470 switch (RC->getID()) {
471 case ARM::DPRRegClassID:
472 case ARM::DPR_8RegClassID:
473 case ARM::DPR_VFP2RegClassID:
474 case ARM::QPRRegClassID:
475 case ARM::QPR_8RegClassID:
476 case ARM::QPR_VFP2RegClassID:
477 case ARM::SPRRegClassID:
478 case ARM::SPR_8RegClassID:
479 // Avoid reusing S, D, and Q registers.
480 // Don't increase register pressure for QQ and QQQQ.
487 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
488 const MachineFrameInfo *MFI = MF.getFrameInfo();
489 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
492 if (!EnableBasePointer)
495 // When outgoing call frames are so large that we adjust the stack pointer
496 // around the call, we can no longer use the stack pointer to reach the
497 // emergency spill slot.
498 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
501 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
502 // negative range for ldr/str (255), and thumb1 is positive offsets only.
503 // It's going to be better to use the SP or Base Pointer instead. When there
504 // are variable sized objects, we can't reference off of the SP, so we
505 // reserve a Base Pointer.
506 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
507 // Conservatively estimate whether the negative offset from the frame
508 // pointer will be sufficient to reach. If a function has a smallish
509 // frame, it's less likely to have lots of spills and callee saved
510 // space, so it's all more likely to be within range of the frame pointer.
511 // If it's wrong, the scavenger will still enable access to work, it just
513 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
521 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
522 const MachineRegisterInfo *MRI = &MF.getRegInfo();
523 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
524 // We can't realign the stack if:
525 // 1. Dynamic stack realignment is explicitly disabled,
526 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
527 // 3. There are VLAs in the function and the base pointer is disabled.
528 if (!MF.getTarget().Options.RealignStack)
530 if (AFI->isThumb1OnlyFunction())
532 // Stack realignment requires a frame pointer. If we already started
533 // register allocation with frame pointer elimination, it is too late now.
534 if (!MRI->canReserveReg(FramePtr))
536 // We may also need a base pointer if there are dynamic allocas or stack
537 // pointer adjustments around calls.
538 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
540 if (!EnableBasePointer)
542 // A base pointer is required and allowed. Check that it isn't too late to
544 return MRI->canReserveReg(BasePtr);
547 bool ARMBaseRegisterInfo::
548 needsStackRealignment(const MachineFunction &MF) const {
549 const MachineFrameInfo *MFI = MF.getFrameInfo();
550 const Function *F = MF.getFunction();
551 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
552 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
553 F->hasFnAttr(Attribute::StackAlignment));
555 return requiresRealignment && canRealignStack(MF);
558 bool ARMBaseRegisterInfo::
559 cannotEliminateFrame(const MachineFunction &MF) const {
560 const MachineFrameInfo *MFI = MF.getFrameInfo();
561 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
563 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
564 || needsStackRealignment(MF);
568 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
569 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
576 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
577 llvm_unreachable("What is the exception register");
580 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
581 llvm_unreachable("What is the exception handler register");
584 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
585 const MachineFunction &MF) const {
588 // Return 0 if either register of the pair is a special register.
590 case ARM::R1: return ARM::R0;
591 case ARM::R3: return ARM::R2;
592 case ARM::R5: return ARM::R4;
594 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
596 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
597 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
599 case ARM::S1: return ARM::S0;
600 case ARM::S3: return ARM::S2;
601 case ARM::S5: return ARM::S4;
602 case ARM::S7: return ARM::S6;
603 case ARM::S9: return ARM::S8;
604 case ARM::S11: return ARM::S10;
605 case ARM::S13: return ARM::S12;
606 case ARM::S15: return ARM::S14;
607 case ARM::S17: return ARM::S16;
608 case ARM::S19: return ARM::S18;
609 case ARM::S21: return ARM::S20;
610 case ARM::S23: return ARM::S22;
611 case ARM::S25: return ARM::S24;
612 case ARM::S27: return ARM::S26;
613 case ARM::S29: return ARM::S28;
614 case ARM::S31: return ARM::S30;
616 case ARM::D1: return ARM::D0;
617 case ARM::D3: return ARM::D2;
618 case ARM::D5: return ARM::D4;
619 case ARM::D7: return ARM::D6;
620 case ARM::D9: return ARM::D8;
621 case ARM::D11: return ARM::D10;
622 case ARM::D13: return ARM::D12;
623 case ARM::D15: return ARM::D14;
624 case ARM::D17: return ARM::D16;
625 case ARM::D19: return ARM::D18;
626 case ARM::D21: return ARM::D20;
627 case ARM::D23: return ARM::D22;
628 case ARM::D25: return ARM::D24;
629 case ARM::D27: return ARM::D26;
630 case ARM::D29: return ARM::D28;
631 case ARM::D31: return ARM::D30;
637 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
638 const MachineFunction &MF) const {
641 // Return 0 if either register of the pair is a special register.
643 case ARM::R0: return ARM::R1;
644 case ARM::R2: return ARM::R3;
645 case ARM::R4: return ARM::R5;
647 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
649 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
650 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
652 case ARM::S0: return ARM::S1;
653 case ARM::S2: return ARM::S3;
654 case ARM::S4: return ARM::S5;
655 case ARM::S6: return ARM::S7;
656 case ARM::S8: return ARM::S9;
657 case ARM::S10: return ARM::S11;
658 case ARM::S12: return ARM::S13;
659 case ARM::S14: return ARM::S15;
660 case ARM::S16: return ARM::S17;
661 case ARM::S18: return ARM::S19;
662 case ARM::S20: return ARM::S21;
663 case ARM::S22: return ARM::S23;
664 case ARM::S24: return ARM::S25;
665 case ARM::S26: return ARM::S27;
666 case ARM::S28: return ARM::S29;
667 case ARM::S30: return ARM::S31;
669 case ARM::D0: return ARM::D1;
670 case ARM::D2: return ARM::D3;
671 case ARM::D4: return ARM::D5;
672 case ARM::D6: return ARM::D7;
673 case ARM::D8: return ARM::D9;
674 case ARM::D10: return ARM::D11;
675 case ARM::D12: return ARM::D13;
676 case ARM::D14: return ARM::D15;
677 case ARM::D16: return ARM::D17;
678 case ARM::D18: return ARM::D19;
679 case ARM::D20: return ARM::D21;
680 case ARM::D22: return ARM::D23;
681 case ARM::D24: return ARM::D25;
682 case ARM::D26: return ARM::D27;
683 case ARM::D28: return ARM::D29;
684 case ARM::D30: return ARM::D31;
690 /// emitLoadConstPool - Emits a load from constpool to materialize the
691 /// specified immediate.
692 void ARMBaseRegisterInfo::
693 emitLoadConstPool(MachineBasicBlock &MBB,
694 MachineBasicBlock::iterator &MBBI,
696 unsigned DestReg, unsigned SubIdx, int Val,
697 ARMCC::CondCodes Pred,
698 unsigned PredReg, unsigned MIFlags) const {
699 MachineFunction &MF = *MBB.getParent();
700 MachineConstantPool *ConstantPool = MF.getConstantPool();
702 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
703 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
705 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
706 .addReg(DestReg, getDefRegState(true), SubIdx)
707 .addConstantPoolIndex(Idx)
708 .addImm(0).addImm(Pred).addReg(PredReg)
709 .setMIFlags(MIFlags);
712 bool ARMBaseRegisterInfo::
713 requiresRegisterScavenging(const MachineFunction &MF) const {
717 bool ARMBaseRegisterInfo::
718 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
722 bool ARMBaseRegisterInfo::
723 requiresFrameIndexScavenging(const MachineFunction &MF) const {
727 bool ARMBaseRegisterInfo::
728 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
729 return EnableLocalStackAlloc;
733 emitSPUpdate(bool isARM,
734 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
735 DebugLoc dl, const ARMBaseInstrInfo &TII,
737 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
739 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
742 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
747 void ARMBaseRegisterInfo::
748 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator I) const {
750 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
751 if (!TFI->hasReservedCallFrame(MF)) {
752 // If we have alloca, convert as follows:
753 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
754 // ADJCALLSTACKUP -> add, sp, sp, amount
755 MachineInstr *Old = I;
756 DebugLoc dl = Old->getDebugLoc();
757 unsigned Amount = Old->getOperand(0).getImm();
759 // We need to keep the stack aligned properly. To do this, we round the
760 // amount of space needed for the outgoing arguments up to the next
761 // alignment boundary.
762 unsigned Align = TFI->getStackAlignment();
763 Amount = (Amount+Align-1)/Align*Align;
765 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
766 assert(!AFI->isThumb1OnlyFunction() &&
767 "This eliminateCallFramePseudoInstr does not support Thumb1!");
768 bool isARM = !AFI->isThumbFunction();
770 // Replace the pseudo instruction with a new instruction...
771 unsigned Opc = Old->getOpcode();
772 int PIdx = Old->findFirstPredOperandIdx();
773 ARMCC::CondCodes Pred = (PIdx == -1)
774 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
775 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
776 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
777 unsigned PredReg = Old->getOperand(2).getReg();
778 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
780 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
781 unsigned PredReg = Old->getOperand(3).getReg();
782 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
783 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
790 int64_t ARMBaseRegisterInfo::
791 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
792 const MCInstrDesc &Desc = MI->getDesc();
793 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
794 int64_t InstrOffs = 0;
798 case ARMII::AddrModeT2_i8:
799 case ARMII::AddrModeT2_i12:
800 case ARMII::AddrMode_i12:
801 InstrOffs = MI->getOperand(Idx+1).getImm();
804 case ARMII::AddrMode5: {
806 const MachineOperand &OffOp = MI->getOperand(Idx+1);
807 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
808 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
809 InstrOffs = -InstrOffs;
813 case ARMII::AddrMode2: {
815 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
816 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
817 InstrOffs = -InstrOffs;
820 case ARMII::AddrMode3: {
822 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
823 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
824 InstrOffs = -InstrOffs;
827 case ARMII::AddrModeT1_s: {
829 InstrOffs = MI->getOperand(ImmIdx).getImm();
834 llvm_unreachable("Unsupported addressing mode!");
837 return InstrOffs * Scale;
840 /// needsFrameBaseReg - Returns true if the instruction's frame index
841 /// reference would be better served by a base register other than FP
842 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
843 /// references it should create new base registers for.
844 bool ARMBaseRegisterInfo::
845 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
846 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
847 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
850 // It's the load/store FI references that cause issues, as it can be difficult
851 // to materialize the offset if it won't fit in the literal field. Estimate
852 // based on the size of the local frame and some conservative assumptions
853 // about the rest of the stack frame (note, this is pre-regalloc, so
854 // we don't know everything for certain yet) whether this offset is likely
855 // to be out of range of the immediate. Return true if so.
857 // We only generate virtual base registers for loads and stores, so
858 // return false for everything else.
859 unsigned Opc = MI->getOpcode();
861 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
862 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
863 case ARM::t2LDRi12: case ARM::t2LDRi8:
864 case ARM::t2STRi12: case ARM::t2STRi8:
865 case ARM::VLDRS: case ARM::VLDRD:
866 case ARM::VSTRS: case ARM::VSTRD:
867 case ARM::tSTRspi: case ARM::tLDRspi:
868 if (ForceAllBaseRegAlloc)
875 // Without a virtual base register, if the function has variable sized
876 // objects, all fixed-size local references will be via the frame pointer,
877 // Approximate the offset and see if it's legal for the instruction.
878 // Note that the incoming offset is based on the SP value at function entry,
879 // so it'll be negative.
880 MachineFunction &MF = *MI->getParent()->getParent();
881 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
882 MachineFrameInfo *MFI = MF.getFrameInfo();
883 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
885 // Estimate an offset from the frame pointer.
886 // Conservatively assume all callee-saved registers get pushed. R4-R6
887 // will be earlier than the FP, so we ignore those.
889 int64_t FPOffset = Offset - 8;
890 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
891 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
893 // Estimate an offset from the stack pointer.
894 // The incoming offset is relating to the SP at the start of the function,
895 // but when we access the local it'll be relative to the SP after local
896 // allocation, so adjust our SP-relative offset by that allocation size.
898 Offset += MFI->getLocalFrameSize();
899 // Assume that we'll have at least some spill slots allocated.
900 // FIXME: This is a total SWAG number. We should run some statistics
901 // and pick a real one.
902 Offset += 128; // 128 bytes of spill slots
904 // If there is a frame pointer, try using it.
905 // The FP is only available if there is no dynamic realignment. We
906 // don't know for sure yet whether we'll need that, so we guess based
907 // on whether there are any local variables that would trigger it.
908 unsigned StackAlign = TFI->getStackAlignment();
909 if (TFI->hasFP(MF) &&
910 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
911 if (isFrameOffsetLegal(MI, FPOffset))
914 // If we can reference via the stack pointer, try that.
915 // FIXME: This (and the code that resolves the references) can be improved
916 // to only disallow SP relative references in the live range of
917 // the VLA(s). In practice, it's unclear how much difference that
918 // would make, but it may be worth doing.
919 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
922 // The offset likely isn't legal, we want to allocate a virtual base register.
926 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
927 /// be a pointer to FrameIdx at the beginning of the basic block.
928 void ARMBaseRegisterInfo::
929 materializeFrameBaseRegister(MachineBasicBlock *MBB,
930 unsigned BaseReg, int FrameIdx,
931 int64_t Offset) const {
932 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
933 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
934 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
936 MachineBasicBlock::iterator Ins = MBB->begin();
937 DebugLoc DL; // Defaults to "unknown"
938 if (Ins != MBB->end())
939 DL = Ins->getDebugLoc();
941 const MCInstrDesc &MCID = TII.get(ADDriOpc);
942 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
943 const MachineFunction &MF = *MBB->getParent();
944 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
946 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
947 .addFrameIndex(FrameIdx).addImm(Offset));
949 if (!AFI->isThumb1OnlyFunction())
954 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
955 unsigned BaseReg, int64_t Offset) const {
956 MachineInstr &MI = *I;
957 MachineBasicBlock &MBB = *MI.getParent();
958 MachineFunction &MF = *MBB.getParent();
959 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
960 int Off = Offset; // ARM doesn't need the general 64-bit offsets
963 assert(!AFI->isThumb1OnlyFunction() &&
964 "This resolveFrameIndex does not support Thumb1!");
966 while (!MI.getOperand(i).isFI()) {
968 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
971 if (!AFI->isThumbFunction())
972 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
974 assert(AFI->isThumb2Function());
975 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
977 assert (Done && "Unable to resolve frame index!");
981 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
982 int64_t Offset) const {
983 const MCInstrDesc &Desc = MI->getDesc();
984 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
987 while (!MI->getOperand(i).isFI()) {
989 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
992 // AddrMode4 and AddrMode6 cannot handle any offset.
993 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
996 unsigned NumBits = 0;
998 bool isSigned = true;
1000 case ARMII::AddrModeT2_i8:
1001 case ARMII::AddrModeT2_i12:
1002 // i8 supports only negative, and i12 supports only positive, so
1003 // based on Offset sign, consider the appropriate instruction
1012 case ARMII::AddrMode5:
1013 // VFP address mode.
1017 case ARMII::AddrMode_i12:
1018 case ARMII::AddrMode2:
1021 case ARMII::AddrMode3:
1024 case ARMII::AddrModeT1_s:
1030 llvm_unreachable("Unsupported addressing mode!");
1033 Offset += getFrameIndexInstrOffset(MI, i);
1034 // Make sure the offset is encodable for instructions that scale the
1036 if ((Offset & (Scale-1)) != 0)
1039 if (isSigned && Offset < 0)
1042 unsigned Mask = (1 << NumBits) - 1;
1043 if ((unsigned)Offset <= Mask * Scale)
1050 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1051 int SPAdj, RegScavenger *RS) const {
1053 MachineInstr &MI = *II;
1054 MachineBasicBlock &MBB = *MI.getParent();
1055 MachineFunction &MF = *MBB.getParent();
1056 const ARMFrameLowering *TFI =
1057 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1058 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1059 assert(!AFI->isThumb1OnlyFunction() &&
1060 "This eliminateFrameIndex does not support Thumb1!");
1062 while (!MI.getOperand(i).isFI()) {
1064 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1067 int FrameIndex = MI.getOperand(i).getIndex();
1070 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1072 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
1073 // call frame setup/destroy instructions have already been eliminated. That
1074 // means the stack pointer cannot be used to access the emergency spill slot
1075 // when !hasReservedCallFrame().
1077 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1078 assert(TFI->hasReservedCallFrame(MF) &&
1079 "Cannot use SP to access the emergency spill slot in "
1080 "functions without a reserved call frame");
1081 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
1082 "Cannot use SP to access the emergency spill slot in "
1083 "functions with variable sized frame objects");
1087 // Special handling of dbg_value instructions.
1088 if (MI.isDebugValue()) {
1089 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1090 MI.getOperand(i+1).ChangeToImmediate(Offset);
1094 // Modify MI as necessary to handle as much of 'Offset' as possible
1096 if (!AFI->isThumbFunction())
1097 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1099 assert(AFI->isThumb2Function());
1100 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1105 // If we get here, the immediate doesn't fit into the instruction. We folded
1106 // as much as possible above, handle the rest, providing a register that is
1109 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1110 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1111 "This code isn't needed if offset already handled!");
1113 unsigned ScratchReg = 0;
1114 int PIdx = MI.findFirstPredOperandIdx();
1115 ARMCC::CondCodes Pred = (PIdx == -1)
1116 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1117 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1119 // Must be addrmode4/6.
1120 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1122 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
1123 if (!AFI->isThumbFunction())
1124 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1125 Offset, Pred, PredReg, TII);
1127 assert(AFI->isThumb2Function());
1128 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1129 Offset, Pred, PredReg, TII);
1131 // Update the original instruction to use the scratch register.
1132 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);