1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameInfo.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47 cl::desc("Force use of virtual base registers for stack load/store"));
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50 cl::desc("Enable pre-regalloc stack frame index allocation"));
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56 const ARMSubtarget &sti)
57 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 static const unsigned CalleeSavedRegs[] = {
66 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
69 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
74 static const unsigned DarwinCalleeSavedRegs[] = {
75 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::R11, ARM::R10, ARM::R8,
80 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
91 // FIXME: avoid re-calculating this everytime.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107 unsigned Reg) const {
108 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
116 if (hasBasePointer(MF))
121 if (FramePtr == Reg && TFI->hasFP(MF))
125 return STI.isR9Reserved();
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133 const TargetRegisterClass *B,
134 unsigned SubIdx) const {
142 if (A->getSize() == 8) {
143 if (B == &ARM::SPR_8RegClass)
144 return &ARM::DPR_8RegClass;
145 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146 if (A == &ARM::DPR_8RegClass)
148 return &ARM::DPR_VFP2RegClass;
151 if (A->getSize() == 16) {
152 if (B == &ARM::SPR_8RegClass)
153 return &ARM::QPR_8RegClass;
154 return &ARM::QPR_VFP2RegClass;
157 if (A->getSize() == 32) {
158 if (B == &ARM::SPR_8RegClass)
159 return 0; // Do not allow coalescing!
160 return &ARM::QQPR_VFP2RegClass;
163 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164 return 0; // Do not allow coalescing!
171 if (A->getSize() == 16) {
172 if (B == &ARM::DPR_VFP2RegClass)
173 return &ARM::QPR_VFP2RegClass;
174 if (B == &ARM::DPR_8RegClass)
175 return 0; // Do not allow coalescing!
179 if (A->getSize() == 32) {
180 if (B == &ARM::DPR_VFP2RegClass)
181 return &ARM::QQPR_VFP2RegClass;
182 if (B == &ARM::DPR_8RegClass)
183 return 0; // Do not allow coalescing!
187 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188 if (B != &ARM::DPRRegClass)
189 return 0; // Do not allow coalescing!
196 // D sub-registers of QQQQ registers.
197 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
205 if (A->getSize() == 32) {
206 if (B == &ARM::QPR_VFP2RegClass)
207 return &ARM::QQPR_VFP2RegClass;
208 if (B == &ARM::QPR_8RegClass)
209 return 0; // Do not allow coalescing!
213 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214 if (B == &ARM::QPRRegClass)
216 return 0; // Do not allow coalescing!
220 // Q sub-registers of QQQQ registers.
221 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
223 return 0; // Do not allow coalescing!
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231 SmallVectorImpl<unsigned> &SubIndices,
232 unsigned &NewSubIdx) const {
234 unsigned Size = RC->getSize() * 8;
238 NewSubIdx = 0; // Whole register.
239 unsigned NumRegs = SubIndices.size();
241 // 8 D registers -> 1 QQQQ register.
242 return (Size == 512 &&
243 SubIndices[0] == ARM::dsub_0 &&
244 SubIndices[1] == ARM::dsub_1 &&
245 SubIndices[2] == ARM::dsub_2 &&
246 SubIndices[3] == ARM::dsub_3 &&
247 SubIndices[4] == ARM::dsub_4 &&
248 SubIndices[5] == ARM::dsub_5 &&
249 SubIndices[6] == ARM::dsub_6 &&
250 SubIndices[7] == ARM::dsub_7);
251 } else if (NumRegs == 4) {
252 if (SubIndices[0] == ARM::qsub_0) {
253 // 4 Q registers -> 1 QQQQ register.
254 return (Size == 512 &&
255 SubIndices[1] == ARM::qsub_1 &&
256 SubIndices[2] == ARM::qsub_2 &&
257 SubIndices[3] == ARM::qsub_3);
258 } else if (SubIndices[0] == ARM::dsub_0) {
259 // 4 D registers -> 1 QQ register.
261 SubIndices[1] == ARM::dsub_1 &&
262 SubIndices[2] == ARM::dsub_2 &&
263 SubIndices[3] == ARM::dsub_3) {
265 NewSubIdx = ARM::qqsub_0;
268 } else if (SubIndices[0] == ARM::dsub_4) {
269 // 4 D registers -> 1 QQ register (2nd).
271 SubIndices[1] == ARM::dsub_5 &&
272 SubIndices[2] == ARM::dsub_6 &&
273 SubIndices[3] == ARM::dsub_7) {
274 NewSubIdx = ARM::qqsub_1;
277 } else if (SubIndices[0] == ARM::ssub_0) {
278 // 4 S registers -> 1 Q register.
280 SubIndices[1] == ARM::ssub_1 &&
281 SubIndices[2] == ARM::ssub_2 &&
282 SubIndices[3] == ARM::ssub_3) {
284 NewSubIdx = ARM::qsub_0;
288 } else if (NumRegs == 2) {
289 if (SubIndices[0] == ARM::qsub_0) {
290 // 2 Q registers -> 1 QQ register.
291 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
293 NewSubIdx = ARM::qqsub_0;
296 } else if (SubIndices[0] == ARM::qsub_2) {
297 // 2 Q registers -> 1 QQ register (2nd).
298 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299 NewSubIdx = ARM::qqsub_1;
302 } else if (SubIndices[0] == ARM::dsub_0) {
303 // 2 D registers -> 1 Q register.
304 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
306 NewSubIdx = ARM::qsub_0;
309 } else if (SubIndices[0] == ARM::dsub_2) {
310 // 2 D registers -> 1 Q register (2nd).
311 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312 NewSubIdx = ARM::qsub_1;
315 } else if (SubIndices[0] == ARM::dsub_4) {
316 // 2 D registers -> 1 Q register (3rd).
317 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318 NewSubIdx = ARM::qsub_2;
321 } else if (SubIndices[0] == ARM::dsub_6) {
322 // 2 D registers -> 1 Q register (3rd).
323 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324 NewSubIdx = ARM::qsub_3;
327 } else if (SubIndices[0] == ARM::ssub_0) {
328 // 2 S registers -> 1 D register.
329 if (SubIndices[1] == ARM::ssub_1) {
331 NewSubIdx = ARM::dsub_0;
334 } else if (SubIndices[0] == ARM::ssub_2) {
335 // 2 S registers -> 1 D register (2nd).
336 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337 NewSubIdx = ARM::dsub_1;
346 const TargetRegisterClass *
347 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
348 return ARM::GPRRegisterClass;
351 /// getAllocationOrder - Returns the register allocation order for a specified
352 /// register class in the form of a pair of TargetRegisterClass iterators.
353 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
354 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
355 unsigned HintType, unsigned HintReg,
356 const MachineFunction &MF) const {
357 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
358 // Alternative register allocation orders when favoring even / odd registers
359 // of register pairs.
361 // No FP, R9 is available.
362 static const unsigned GPREven1[] = {
363 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
364 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
367 static const unsigned GPROdd1[] = {
368 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
369 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
373 // FP is R7, R9 is available.
374 static const unsigned GPREven2[] = {
375 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
376 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
379 static const unsigned GPROdd2[] = {
380 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
381 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
385 // FP is R11, R9 is available.
386 static const unsigned GPREven3[] = {
387 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
388 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
391 static const unsigned GPROdd3[] = {
392 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
393 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
397 // No FP, R9 is not available.
398 static const unsigned GPREven4[] = {
399 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
400 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
403 static const unsigned GPROdd4[] = {
404 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
405 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
409 // FP is R7, R9 is not available.
410 static const unsigned GPREven5[] = {
411 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
412 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
415 static const unsigned GPROdd5[] = {
416 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
417 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
421 // FP is R11, R9 is not available.
422 static const unsigned GPREven6[] = {
423 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
424 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
426 static const unsigned GPROdd6[] = {
427 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
428 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
432 if (HintType == ARMRI::RegPairEven) {
433 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
434 // It's no longer possible to fulfill this hint. Return the default
436 return std::make_pair(RC->allocation_order_begin(MF),
437 RC->allocation_order_end(MF));
439 if (!TFI->hasFP(MF)) {
440 if (!STI.isR9Reserved())
441 return std::make_pair(GPREven1,
442 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
444 return std::make_pair(GPREven4,
445 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
446 } else if (FramePtr == ARM::R7) {
447 if (!STI.isR9Reserved())
448 return std::make_pair(GPREven2,
449 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
451 return std::make_pair(GPREven5,
452 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
453 } else { // FramePtr == ARM::R11
454 if (!STI.isR9Reserved())
455 return std::make_pair(GPREven3,
456 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
458 return std::make_pair(GPREven6,
459 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
461 } else if (HintType == ARMRI::RegPairOdd) {
462 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
463 // It's no longer possible to fulfill this hint. Return the default
465 return std::make_pair(RC->allocation_order_begin(MF),
466 RC->allocation_order_end(MF));
468 if (!TFI->hasFP(MF)) {
469 if (!STI.isR9Reserved())
470 return std::make_pair(GPROdd1,
471 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
473 return std::make_pair(GPROdd4,
474 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
475 } else if (FramePtr == ARM::R7) {
476 if (!STI.isR9Reserved())
477 return std::make_pair(GPROdd2,
478 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
480 return std::make_pair(GPROdd5,
481 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
482 } else { // FramePtr == ARM::R11
483 if (!STI.isR9Reserved())
484 return std::make_pair(GPROdd3,
485 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
487 return std::make_pair(GPROdd6,
488 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
491 return std::make_pair(RC->allocation_order_begin(MF),
492 RC->allocation_order_end(MF));
495 /// ResolveRegAllocHint - Resolves the specified register allocation hint
496 /// to a physical register. Returns the physical register if it is successful.
498 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
499 const MachineFunction &MF) const {
500 if (Reg == 0 || !isPhysicalRegister(Reg))
504 else if (Type == (unsigned)ARMRI::RegPairOdd)
506 return getRegisterPairOdd(Reg, MF);
507 else if (Type == (unsigned)ARMRI::RegPairEven)
509 return getRegisterPairEven(Reg, MF);
514 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
515 MachineFunction &MF) const {
516 MachineRegisterInfo *MRI = &MF.getRegInfo();
517 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
518 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
519 Hint.first == (unsigned)ARMRI::RegPairEven) &&
520 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
521 // If 'Reg' is one of the even / odd register pair and it's now changed
522 // (e.g. coalesced) into a different register. The other register of the
523 // pair allocation hint must be updated to reflect the relationship
525 unsigned OtherReg = Hint.second;
526 Hint = MRI->getRegAllocationHint(OtherReg);
527 if (Hint.second == Reg)
528 // Make sure the pair has not already divorced.
529 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
533 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
534 const MachineFrameInfo *MFI = MF.getFrameInfo();
535 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
537 if (!EnableBasePointer)
540 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
543 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
544 // negative range for ldr/str (255), and thumb1 is positive offsets only.
545 // It's going to be better to use the SP or Base Pointer instead. When there
546 // are variable sized objects, we can't reference off of the SP, so we
547 // reserve a Base Pointer.
548 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
549 // Conservatively estimate whether the negative offset from the frame
550 // pointer will be sufficient to reach. If a function has a smallish
551 // frame, it's less likely to have lots of spills and callee saved
552 // space, so it's all more likely to be within range of the frame pointer.
553 // If it's wrong, the scavenger will still enable access to work, it just
555 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
563 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
564 const MachineFrameInfo *MFI = MF.getFrameInfo();
565 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
566 // We can't realign the stack if:
567 // 1. Dynamic stack realignment is explicitly disabled,
568 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
569 // 3. There are VLAs in the function and the base pointer is disabled.
570 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
571 (!MFI->hasVarSizedObjects() || EnableBasePointer));
574 bool ARMBaseRegisterInfo::
575 needsStackRealignment(const MachineFunction &MF) const {
576 const MachineFrameInfo *MFI = MF.getFrameInfo();
577 const Function *F = MF.getFunction();
578 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
579 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
580 F->hasFnAttr(Attribute::StackAlignment));
582 return requiresRealignment && canRealignStack(MF);
585 bool ARMBaseRegisterInfo::
586 cannotEliminateFrame(const MachineFunction &MF) const {
587 const MachineFrameInfo *MFI = MF.getFrameInfo();
588 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
590 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
591 || needsStackRealignment(MF);
594 unsigned ARMBaseRegisterInfo::getRARegister() const {
599 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
600 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
607 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
608 llvm_unreachable("What is the exception register");
612 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
613 llvm_unreachable("What is the exception handler register");
617 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
618 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
621 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
622 const MachineFunction &MF) const {
625 // Return 0 if either register of the pair is a special register.
634 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
637 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
639 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
711 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
712 const MachineFunction &MF) const {
715 // Return 0 if either register of the pair is a special register.
724 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
727 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
729 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
801 /// emitLoadConstPool - Emits a load from constpool to materialize the
802 /// specified immediate.
803 void ARMBaseRegisterInfo::
804 emitLoadConstPool(MachineBasicBlock &MBB,
805 MachineBasicBlock::iterator &MBBI,
807 unsigned DestReg, unsigned SubIdx, int Val,
808 ARMCC::CondCodes Pred,
809 unsigned PredReg) const {
810 MachineFunction &MF = *MBB.getParent();
811 MachineConstantPool *ConstantPool = MF.getConstantPool();
813 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
814 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
816 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
817 .addReg(DestReg, getDefRegState(true), SubIdx)
818 .addConstantPoolIndex(Idx)
819 .addImm(0).addImm(Pred).addReg(PredReg);
822 bool ARMBaseRegisterInfo::
823 requiresRegisterScavenging(const MachineFunction &MF) const {
827 bool ARMBaseRegisterInfo::
828 requiresFrameIndexScavenging(const MachineFunction &MF) const {
832 bool ARMBaseRegisterInfo::
833 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
834 return EnableLocalStackAlloc;
838 emitSPUpdate(bool isARM,
839 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
840 DebugLoc dl, const ARMBaseInstrInfo &TII,
842 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
844 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
847 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
852 void ARMBaseRegisterInfo::
853 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
854 MachineBasicBlock::iterator I) const {
855 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
856 if (!TFI->hasReservedCallFrame(MF)) {
857 // If we have alloca, convert as follows:
858 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
859 // ADJCALLSTACKUP -> add, sp, sp, amount
860 MachineInstr *Old = I;
861 DebugLoc dl = Old->getDebugLoc();
862 unsigned Amount = Old->getOperand(0).getImm();
864 // We need to keep the stack aligned properly. To do this, we round the
865 // amount of space needed for the outgoing arguments up to the next
866 // alignment boundary.
867 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
868 Amount = (Amount+Align-1)/Align*Align;
870 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
871 assert(!AFI->isThumb1OnlyFunction() &&
872 "This eliminateCallFramePseudoInstr does not support Thumb1!");
873 bool isARM = !AFI->isThumbFunction();
875 // Replace the pseudo instruction with a new instruction...
876 unsigned Opc = Old->getOpcode();
877 int PIdx = Old->findFirstPredOperandIdx();
878 ARMCC::CondCodes Pred = (PIdx == -1)
879 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
880 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
881 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
882 unsigned PredReg = Old->getOperand(2).getReg();
883 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
885 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
886 unsigned PredReg = Old->getOperand(3).getReg();
887 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
888 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
895 int64_t ARMBaseRegisterInfo::
896 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
897 const TargetInstrDesc &Desc = MI->getDesc();
898 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
899 int64_t InstrOffs = 0;;
903 case ARMII::AddrModeT2_i8:
904 case ARMII::AddrModeT2_i12:
905 case ARMII::AddrMode_i12:
906 InstrOffs = MI->getOperand(Idx+1).getImm();
909 case ARMII::AddrMode5: {
911 const MachineOperand &OffOp = MI->getOperand(Idx+1);
912 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
913 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
914 InstrOffs = -InstrOffs;
918 case ARMII::AddrMode2: {
920 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
921 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
922 InstrOffs = -InstrOffs;
925 case ARMII::AddrMode3: {
927 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
928 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
929 InstrOffs = -InstrOffs;
932 case ARMII::AddrModeT1_s: {
934 InstrOffs = MI->getOperand(ImmIdx).getImm();
939 llvm_unreachable("Unsupported addressing mode!");
943 return InstrOffs * Scale;
946 /// needsFrameBaseReg - Returns true if the instruction's frame index
947 /// reference would be better served by a base register other than FP
948 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
949 /// references it should create new base registers for.
950 bool ARMBaseRegisterInfo::
951 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
952 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
953 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
956 // It's the load/store FI references that cause issues, as it can be difficult
957 // to materialize the offset if it won't fit in the literal field. Estimate
958 // based on the size of the local frame and some conservative assumptions
959 // about the rest of the stack frame (note, this is pre-regalloc, so
960 // we don't know everything for certain yet) whether this offset is likely
961 // to be out of range of the immediate. Return true if so.
963 // We only generate virtual base registers for loads and stores, so
964 // return false for everything else.
965 unsigned Opc = MI->getOpcode();
967 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
968 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
969 case ARM::t2LDRi12: case ARM::t2LDRi8:
970 case ARM::t2STRi12: case ARM::t2STRi8:
971 case ARM::VLDRS: case ARM::VLDRD:
972 case ARM::VSTRS: case ARM::VSTRD:
973 case ARM::tSTRspi: case ARM::tLDRspi:
974 if (ForceAllBaseRegAlloc)
981 // Without a virtual base register, if the function has variable sized
982 // objects, all fixed-size local references will be via the frame pointer,
983 // Approximate the offset and see if it's legal for the instruction.
984 // Note that the incoming offset is based on the SP value at function entry,
985 // so it'll be negative.
986 MachineFunction &MF = *MI->getParent()->getParent();
987 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
988 MachineFrameInfo *MFI = MF.getFrameInfo();
989 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
991 // Estimate an offset from the frame pointer.
992 // Conservatively assume all callee-saved registers get pushed. R4-R6
993 // will be earlier than the FP, so we ignore those.
995 int64_t FPOffset = Offset - 8;
996 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
997 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
999 // Estimate an offset from the stack pointer.
1000 // The incoming offset is relating to the SP at the start of the function,
1001 // but when we access the local it'll be relative to the SP after local
1002 // allocation, so adjust our SP-relative offset by that allocation size.
1004 Offset += MFI->getLocalFrameSize();
1005 // Assume that we'll have at least some spill slots allocated.
1006 // FIXME: This is a total SWAG number. We should run some statistics
1007 // and pick a real one.
1008 Offset += 128; // 128 bytes of spill slots
1010 // If there is a frame pointer, try using it.
1011 // The FP is only available if there is no dynamic realignment. We
1012 // don't know for sure yet whether we'll need that, so we guess based
1013 // on whether there are any local variables that would trigger it.
1014 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1015 if (TFI->hasFP(MF) &&
1016 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1017 if (isFrameOffsetLegal(MI, FPOffset))
1020 // If we can reference via the stack pointer, try that.
1021 // FIXME: This (and the code that resolves the references) can be improved
1022 // to only disallow SP relative references in the live range of
1023 // the VLA(s). In practice, it's unclear how much difference that
1024 // would make, but it may be worth doing.
1025 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1028 // The offset likely isn't legal, we want to allocate a virtual base register.
1032 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1033 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1034 void ARMBaseRegisterInfo::
1035 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1036 int FrameIdx, int64_t Offset) const {
1037 ARMFunctionInfo *AFI =
1038 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1039 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1040 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1042 MachineInstrBuilder MIB =
1043 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1044 .addFrameIndex(FrameIdx).addImm(Offset);
1045 if (!AFI->isThumb1OnlyFunction())
1046 AddDefaultCC(AddDefaultPred(MIB));
1050 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1051 unsigned BaseReg, int64_t Offset) const {
1052 MachineInstr &MI = *I;
1053 MachineBasicBlock &MBB = *MI.getParent();
1054 MachineFunction &MF = *MBB.getParent();
1055 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1056 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1059 assert(!AFI->isThumb1OnlyFunction() &&
1060 "This resolveFrameIndex does not support Thumb1!");
1062 while (!MI.getOperand(i).isFI()) {
1064 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1067 if (!AFI->isThumbFunction())
1068 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1070 assert(AFI->isThumb2Function());
1071 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1073 assert (Done && "Unable to resolve frame index!");
1076 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1077 int64_t Offset) const {
1078 const TargetInstrDesc &Desc = MI->getDesc();
1079 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1082 while (!MI->getOperand(i).isFI()) {
1084 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1087 // AddrMode4 and AddrMode6 cannot handle any offset.
1088 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1091 unsigned NumBits = 0;
1093 bool isSigned = true;
1095 case ARMII::AddrModeT2_i8:
1096 case ARMII::AddrModeT2_i12:
1097 // i8 supports only negative, and i12 supports only positive, so
1098 // based on Offset sign, consider the appropriate instruction
1107 case ARMII::AddrMode5:
1108 // VFP address mode.
1112 case ARMII::AddrMode_i12:
1113 case ARMII::AddrMode2:
1116 case ARMII::AddrMode3:
1119 case ARMII::AddrModeT1_s:
1125 llvm_unreachable("Unsupported addressing mode!");
1129 Offset += getFrameIndexInstrOffset(MI, i);
1130 // Make sure the offset is encodable for instructions that scale the
1132 if ((Offset & (Scale-1)) != 0)
1135 if (isSigned && Offset < 0)
1138 unsigned Mask = (1 << NumBits) - 1;
1139 if ((unsigned)Offset <= Mask * Scale)
1146 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1147 int SPAdj, RegScavenger *RS) const {
1149 MachineInstr &MI = *II;
1150 MachineBasicBlock &MBB = *MI.getParent();
1151 MachineFunction &MF = *MBB.getParent();
1152 const ARMFrameInfo *TFI =
1153 static_cast<const ARMFrameInfo*>(MF.getTarget().getFrameInfo());
1154 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1155 assert(!AFI->isThumb1OnlyFunction() &&
1156 "This eliminateFrameIndex does not support Thumb1!");
1158 while (!MI.getOperand(i).isFI()) {
1160 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1163 int FrameIndex = MI.getOperand(i).getIndex();
1166 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1168 // Special handling of dbg_value instructions.
1169 if (MI.isDebugValue()) {
1170 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1171 MI.getOperand(i+1).ChangeToImmediate(Offset);
1175 // Modify MI as necessary to handle as much of 'Offset' as possible
1177 if (!AFI->isThumbFunction())
1178 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1180 assert(AFI->isThumb2Function());
1181 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1186 // If we get here, the immediate doesn't fit into the instruction. We folded
1187 // as much as possible above, handle the rest, providing a register that is
1190 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1191 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1192 "This code isn't needed if offset already handled!");
1194 unsigned ScratchReg = 0;
1195 int PIdx = MI.findFirstPredOperandIdx();
1196 ARMCC::CondCodes Pred = (PIdx == -1)
1197 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1198 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1200 // Must be addrmode4/6.
1201 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1203 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1204 if (!AFI->isThumbFunction())
1205 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1206 Offset, Pred, PredReg, TII);
1208 assert(AFI->isThumb2Function());
1209 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1210 Offset, Pred, PredReg, TII);
1212 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1216 #include "ARMGenRegisterInfo.inc"