1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameInfo.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47 cl::desc("Force use of virtual base registers for stack load/store"));
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50 cl::desc("Enable pre-regalloc stack frame index allocation"));
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56 const ARMSubtarget &sti)
57 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 static const unsigned CalleeSavedRegs[] = {
66 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
69 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
74 static const unsigned DarwinCalleeSavedRegs[] = {
75 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::R11, ARM::R10, ARM::R8,
80 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
91 // FIXME: avoid re-calculating this everytime.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107 unsigned Reg) const {
108 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
116 if (hasBasePointer(MF))
121 if (FramePtr == Reg && TFI->hasFP(MF))
125 return STI.isR9Reserved();
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133 const TargetRegisterClass *B,
134 unsigned SubIdx) const {
142 if (A->getSize() == 8) {
143 if (B == &ARM::SPR_8RegClass)
144 return &ARM::DPR_8RegClass;
145 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146 if (A == &ARM::DPR_8RegClass)
148 return &ARM::DPR_VFP2RegClass;
151 if (A->getSize() == 16) {
152 if (B == &ARM::SPR_8RegClass)
153 return &ARM::QPR_8RegClass;
154 return &ARM::QPR_VFP2RegClass;
157 if (A->getSize() == 32) {
158 if (B == &ARM::SPR_8RegClass)
159 return 0; // Do not allow coalescing!
160 return &ARM::QQPR_VFP2RegClass;
163 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164 return 0; // Do not allow coalescing!
171 if (A->getSize() == 16) {
172 if (B == &ARM::DPR_VFP2RegClass)
173 return &ARM::QPR_VFP2RegClass;
174 if (B == &ARM::DPR_8RegClass)
175 return 0; // Do not allow coalescing!
179 if (A->getSize() == 32) {
180 if (B == &ARM::DPR_VFP2RegClass)
181 return &ARM::QQPR_VFP2RegClass;
182 if (B == &ARM::DPR_8RegClass)
183 return 0; // Do not allow coalescing!
187 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188 if (B != &ARM::DPRRegClass)
189 return 0; // Do not allow coalescing!
196 // D sub-registers of QQQQ registers.
197 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
205 if (A->getSize() == 32) {
206 if (B == &ARM::QPR_VFP2RegClass)
207 return &ARM::QQPR_VFP2RegClass;
208 if (B == &ARM::QPR_8RegClass)
209 return 0; // Do not allow coalescing!
213 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214 if (B == &ARM::QPRRegClass)
216 return 0; // Do not allow coalescing!
220 // Q sub-registers of QQQQ registers.
221 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
223 return 0; // Do not allow coalescing!
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231 SmallVectorImpl<unsigned> &SubIndices,
232 unsigned &NewSubIdx) const {
234 unsigned Size = RC->getSize() * 8;
238 NewSubIdx = 0; // Whole register.
239 unsigned NumRegs = SubIndices.size();
241 // 8 D registers -> 1 QQQQ register.
242 return (Size == 512 &&
243 SubIndices[0] == ARM::dsub_0 &&
244 SubIndices[1] == ARM::dsub_1 &&
245 SubIndices[2] == ARM::dsub_2 &&
246 SubIndices[3] == ARM::dsub_3 &&
247 SubIndices[4] == ARM::dsub_4 &&
248 SubIndices[5] == ARM::dsub_5 &&
249 SubIndices[6] == ARM::dsub_6 &&
250 SubIndices[7] == ARM::dsub_7);
251 } else if (NumRegs == 4) {
252 if (SubIndices[0] == ARM::qsub_0) {
253 // 4 Q registers -> 1 QQQQ register.
254 return (Size == 512 &&
255 SubIndices[1] == ARM::qsub_1 &&
256 SubIndices[2] == ARM::qsub_2 &&
257 SubIndices[3] == ARM::qsub_3);
258 } else if (SubIndices[0] == ARM::dsub_0) {
259 // 4 D registers -> 1 QQ register.
261 SubIndices[1] == ARM::dsub_1 &&
262 SubIndices[2] == ARM::dsub_2 &&
263 SubIndices[3] == ARM::dsub_3) {
265 NewSubIdx = ARM::qqsub_0;
268 } else if (SubIndices[0] == ARM::dsub_4) {
269 // 4 D registers -> 1 QQ register (2nd).
271 SubIndices[1] == ARM::dsub_5 &&
272 SubIndices[2] == ARM::dsub_6 &&
273 SubIndices[3] == ARM::dsub_7) {
274 NewSubIdx = ARM::qqsub_1;
277 } else if (SubIndices[0] == ARM::ssub_0) {
278 // 4 S registers -> 1 Q register.
280 SubIndices[1] == ARM::ssub_1 &&
281 SubIndices[2] == ARM::ssub_2 &&
282 SubIndices[3] == ARM::ssub_3) {
284 NewSubIdx = ARM::qsub_0;
288 } else if (NumRegs == 2) {
289 if (SubIndices[0] == ARM::qsub_0) {
290 // 2 Q registers -> 1 QQ register.
291 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
293 NewSubIdx = ARM::qqsub_0;
296 } else if (SubIndices[0] == ARM::qsub_2) {
297 // 2 Q registers -> 1 QQ register (2nd).
298 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299 NewSubIdx = ARM::qqsub_1;
302 } else if (SubIndices[0] == ARM::dsub_0) {
303 // 2 D registers -> 1 Q register.
304 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
306 NewSubIdx = ARM::qsub_0;
309 } else if (SubIndices[0] == ARM::dsub_2) {
310 // 2 D registers -> 1 Q register (2nd).
311 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312 NewSubIdx = ARM::qsub_1;
315 } else if (SubIndices[0] == ARM::dsub_4) {
316 // 2 D registers -> 1 Q register (3rd).
317 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318 NewSubIdx = ARM::qsub_2;
321 } else if (SubIndices[0] == ARM::dsub_6) {
322 // 2 D registers -> 1 Q register (3rd).
323 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324 NewSubIdx = ARM::qsub_3;
327 } else if (SubIndices[0] == ARM::ssub_0) {
328 // 2 S registers -> 1 D register.
329 if (SubIndices[1] == ARM::ssub_1) {
331 NewSubIdx = ARM::dsub_0;
334 } else if (SubIndices[0] == ARM::ssub_2) {
335 // 2 S registers -> 1 D register (2nd).
336 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337 NewSubIdx = ARM::dsub_1;
346 const TargetRegisterClass *
347 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
348 return ARM::GPRRegisterClass;
351 /// getAllocationOrder - Returns the register allocation order for a specified
352 /// register class in the form of a pair of TargetRegisterClass iterators.
353 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
354 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
355 unsigned HintType, unsigned HintReg,
356 const MachineFunction &MF) const {
357 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
358 // Alternative register allocation orders when favoring even / odd registers
359 // of register pairs.
361 // No FP, R9 is available.
362 static const unsigned GPREven1[] = {
363 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
364 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
367 static const unsigned GPROdd1[] = {
368 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
369 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
373 // FP is R7, R9 is available.
374 static const unsigned GPREven2[] = {
375 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
376 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
379 static const unsigned GPROdd2[] = {
380 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
381 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
385 // FP is R11, R9 is available.
386 static const unsigned GPREven3[] = {
387 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
388 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
391 static const unsigned GPROdd3[] = {
392 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
393 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
397 // No FP, R9 is not available.
398 static const unsigned GPREven4[] = {
399 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
400 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
403 static const unsigned GPROdd4[] = {
404 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
405 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
409 // FP is R7, R9 is not available.
410 static const unsigned GPREven5[] = {
411 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
412 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
415 static const unsigned GPROdd5[] = {
416 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
417 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
421 // FP is R11, R9 is not available.
422 static const unsigned GPREven6[] = {
423 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
424 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
426 static const unsigned GPROdd6[] = {
427 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
428 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
432 if (HintType == ARMRI::RegPairEven) {
433 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
434 // It's no longer possible to fulfill this hint. Return the default
436 return std::make_pair(RC->allocation_order_begin(MF),
437 RC->allocation_order_end(MF));
439 if (!TFI->hasFP(MF)) {
440 if (!STI.isR9Reserved())
441 return std::make_pair(GPREven1,
442 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
444 return std::make_pair(GPREven4,
445 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
446 } else if (FramePtr == ARM::R7) {
447 if (!STI.isR9Reserved())
448 return std::make_pair(GPREven2,
449 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
451 return std::make_pair(GPREven5,
452 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
453 } else { // FramePtr == ARM::R11
454 if (!STI.isR9Reserved())
455 return std::make_pair(GPREven3,
456 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
458 return std::make_pair(GPREven6,
459 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
461 } else if (HintType == ARMRI::RegPairOdd) {
462 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
463 // It's no longer possible to fulfill this hint. Return the default
465 return std::make_pair(RC->allocation_order_begin(MF),
466 RC->allocation_order_end(MF));
468 if (!TFI->hasFP(MF)) {
469 if (!STI.isR9Reserved())
470 return std::make_pair(GPROdd1,
471 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
473 return std::make_pair(GPROdd4,
474 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
475 } else if (FramePtr == ARM::R7) {
476 if (!STI.isR9Reserved())
477 return std::make_pair(GPROdd2,
478 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
480 return std::make_pair(GPROdd5,
481 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
482 } else { // FramePtr == ARM::R11
483 if (!STI.isR9Reserved())
484 return std::make_pair(GPROdd3,
485 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
487 return std::make_pair(GPROdd6,
488 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
491 return std::make_pair(RC->allocation_order_begin(MF),
492 RC->allocation_order_end(MF));
495 /// ResolveRegAllocHint - Resolves the specified register allocation hint
496 /// to a physical register. Returns the physical register if it is successful.
498 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
499 const MachineFunction &MF) const {
500 if (Reg == 0 || !isPhysicalRegister(Reg))
504 else if (Type == (unsigned)ARMRI::RegPairOdd)
506 return getRegisterPairOdd(Reg, MF);
507 else if (Type == (unsigned)ARMRI::RegPairEven)
509 return getRegisterPairEven(Reg, MF);
514 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
515 MachineFunction &MF) const {
516 MachineRegisterInfo *MRI = &MF.getRegInfo();
517 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
518 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
519 Hint.first == (unsigned)ARMRI::RegPairEven) &&
520 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
521 // If 'Reg' is one of the even / odd register pair and it's now changed
522 // (e.g. coalesced) into a different register. The other register of the
523 // pair allocation hint must be updated to reflect the relationship
525 unsigned OtherReg = Hint.second;
526 Hint = MRI->getRegAllocationHint(OtherReg);
527 if (Hint.second == Reg)
528 // Make sure the pair has not already divorced.
529 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
533 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
534 const MachineFrameInfo *MFI = MF.getFrameInfo();
535 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
537 if (!EnableBasePointer)
540 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
543 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
544 // negative range for ldr/str (255), and thumb1 is positive offsets only.
545 // It's going to be better to use the SP or Base Pointer instead. When there
546 // are variable sized objects, we can't reference off of the SP, so we
547 // reserve a Base Pointer.
548 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
549 // Conservatively estimate whether the negative offset from the frame
550 // pointer will be sufficient to reach. If a function has a smallish
551 // frame, it's less likely to have lots of spills and callee saved
552 // space, so it's all more likely to be within range of the frame pointer.
553 // If it's wrong, the scavenger will still enable access to work, it just
555 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
563 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
564 const MachineFrameInfo *MFI = MF.getFrameInfo();
565 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
566 // We can't realign the stack if:
567 // 1. Dynamic stack realignment is explicitly disabled,
568 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
569 // 3. There are VLAs in the function and the base pointer is disabled.
570 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
571 (!MFI->hasVarSizedObjects() || EnableBasePointer));
574 bool ARMBaseRegisterInfo::
575 needsStackRealignment(const MachineFunction &MF) const {
576 const MachineFrameInfo *MFI = MF.getFrameInfo();
577 const Function *F = MF.getFunction();
578 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
579 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
580 F->hasFnAttr(Attribute::StackAlignment));
582 return requiresRealignment && canRealignStack(MF);
585 bool ARMBaseRegisterInfo::
586 cannotEliminateFrame(const MachineFunction &MF) const {
587 const MachineFrameInfo *MFI = MF.getFrameInfo();
588 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
590 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
591 || needsStackRealignment(MF);
594 /// estimateStackSize - Estimate and return the size of the frame.
595 static unsigned estimateStackSize(MachineFunction &MF) {
596 const MachineFrameInfo *FFI = MF.getFrameInfo();
598 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
599 int FixedOff = -FFI->getObjectOffset(i);
600 if (FixedOff > Offset) Offset = FixedOff;
602 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
603 if (FFI->isDeadObjectIndex(i))
605 Offset += FFI->getObjectSize(i);
606 unsigned Align = FFI->getObjectAlignment(i);
607 // Adjust to alignment boundary
608 Offset = (Offset+Align-1)/Align*Align;
610 return (unsigned)Offset;
613 /// estimateRSStackSizeLimit - Look at each instruction that references stack
614 /// frames and return the stack size limit beyond which some of these
615 /// instructions will require a scratch register during their expansion later.
617 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
618 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
619 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
620 unsigned Limit = (1 << 12) - 1;
621 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
622 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
624 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
625 if (!I->getOperand(i).isFI()) continue;
627 // When using ADDri to get the address of a stack object, 255 is the
628 // largest offset guaranteed to fit in the immediate offset.
629 if (I->getOpcode() == ARM::ADDri) {
630 Limit = std::min(Limit, (1U << 8) - 1);
634 // Otherwise check the addressing mode.
635 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
636 case ARMII::AddrMode3:
637 case ARMII::AddrModeT2_i8:
638 Limit = std::min(Limit, (1U << 8) - 1);
640 case ARMII::AddrMode5:
641 case ARMII::AddrModeT2_i8s4:
642 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
644 case ARMII::AddrModeT2_i12:
645 // i12 supports only positive offset so these will be converted to
646 // i8 opcodes. See llvm::rewriteT2FrameIndex.
647 if (TFI->hasFP(MF) && AFI->hasStackFrame())
648 Limit = std::min(Limit, (1U << 8) - 1);
650 case ARMII::AddrMode4:
651 case ARMII::AddrMode6:
652 // Addressing modes 4 & 6 (load/store) instructions can't encode an
653 // immediate offset for stack references.
658 break; // At most one FI per instruction
666 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
667 const ARMBaseInstrInfo &TII) {
669 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
671 const MachineBasicBlock &MBB = *MBBI;
672 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
674 FnSize += TII.GetInstSizeInBytes(I);
680 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
681 RegScavenger *RS) const {
682 // This tells PEI to spill the FP as if it is any other callee-save register
683 // to take advantage the eliminateFrameIndex machinery. This also ensures it
684 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
685 // to combine multiple loads / stores.
686 bool CanEliminateFrame = true;
687 bool CS1Spilled = false;
688 bool LRSpilled = false;
689 unsigned NumGPRSpills = 0;
690 SmallVector<unsigned, 4> UnspilledCS1GPRs;
691 SmallVector<unsigned, 4> UnspilledCS2GPRs;
692 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
693 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
694 MachineFrameInfo *MFI = MF.getFrameInfo();
696 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
697 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
698 // since it's always posible to restore sp from fp in a single instruction.
699 // FIXME: It will be better just to find spare register here.
700 if (AFI->isThumb2Function() &&
701 (MFI->hasVarSizedObjects() || needsStackRealignment(MF)))
702 MF.getRegInfo().setPhysRegUsed(ARM::R4);
704 // Spill LR if Thumb1 function uses variable length argument lists.
705 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
706 MF.getRegInfo().setPhysRegUsed(ARM::LR);
708 // Spill the BasePtr if it's used.
709 if (hasBasePointer(MF))
710 MF.getRegInfo().setPhysRegUsed(BasePtr);
712 // Don't spill FP if the frame can be eliminated. This is determined
713 // by scanning the callee-save registers to see if any is used.
714 const unsigned *CSRegs = getCalleeSavedRegs();
715 for (unsigned i = 0; CSRegs[i]; ++i) {
716 unsigned Reg = CSRegs[i];
717 bool Spilled = false;
718 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
719 AFI->setCSRegisterIsSpilled(Reg);
721 CanEliminateFrame = false;
723 // Check alias registers too.
724 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
725 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
727 CanEliminateFrame = false;
732 if (!ARM::GPRRegisterClass->contains(Reg))
738 if (!STI.isTargetDarwin()) {
745 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
760 if (!STI.isTargetDarwin()) {
761 UnspilledCS1GPRs.push_back(Reg);
771 UnspilledCS1GPRs.push_back(Reg);
774 UnspilledCS2GPRs.push_back(Reg);
780 bool ForceLRSpill = false;
781 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
782 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
783 // Force LR to be spilled if the Thumb function size is > 2048. This enables
784 // use of BL to implement far jump. If it turns out that it's not needed
785 // then the branch fix up path will undo it.
786 if (FnSize >= (1 << 11)) {
787 CanEliminateFrame = false;
792 // If any of the stack slot references may be out of range of an immediate
793 // offset, make sure a register (or a spill slot) is available for the
794 // register scavenger. Note that if we're indexing off the frame pointer, the
795 // effective stack size is 4 bytes larger since the FP points to the stack
796 // slot of the previous FP. Also, if we have variable sized objects in the
797 // function, stack slot references will often be negative, and some of
798 // our instructions are positive-offset only, so conservatively consider
799 // that case to want a spill slot (or register) as well. Similarly, if
800 // the function adjusts the stack pointer during execution and the
801 // adjustments aren't already part of our stack size estimate, our offset
802 // calculations may be off, so be conservative.
803 // FIXME: We could add logic to be more precise about negative offsets
804 // and which instructions will need a scratch register for them. Is it
805 // worth the effort and added fragility?
808 (estimateStackSize(MF) + ((TFI->hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
809 estimateRSStackSizeLimit(MF)))
810 || MFI->hasVarSizedObjects()
811 || (MFI->adjustsStack() && !TFI->canSimplifyCallFramePseudos(MF));
813 bool ExtraCSSpill = false;
814 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
815 AFI->setHasStackFrame(true);
817 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
818 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
819 if (!LRSpilled && CS1Spilled) {
820 MF.getRegInfo().setPhysRegUsed(ARM::LR);
821 AFI->setCSRegisterIsSpilled(ARM::LR);
823 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
824 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
825 ForceLRSpill = false;
829 if (TFI->hasFP(MF)) {
830 MF.getRegInfo().setPhysRegUsed(FramePtr);
834 // If stack and double are 8-byte aligned and we are spilling an odd number
835 // of GPRs, spill one extra callee save GPR so we won't have to pad between
836 // the integer and double callee save areas.
837 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
838 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
839 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
840 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
841 unsigned Reg = UnspilledCS1GPRs[i];
842 // Don't spill high register if the function is thumb1
843 if (!AFI->isThumb1OnlyFunction() ||
844 isARMLowRegister(Reg) || Reg == ARM::LR) {
845 MF.getRegInfo().setPhysRegUsed(Reg);
846 AFI->setCSRegisterIsSpilled(Reg);
847 if (!isReservedReg(MF, Reg))
852 } else if (!UnspilledCS2GPRs.empty() &&
853 !AFI->isThumb1OnlyFunction()) {
854 unsigned Reg = UnspilledCS2GPRs.front();
855 MF.getRegInfo().setPhysRegUsed(Reg);
856 AFI->setCSRegisterIsSpilled(Reg);
857 if (!isReservedReg(MF, Reg))
862 // Estimate if we might need to scavenge a register at some point in order
863 // to materialize a stack offset. If so, either spill one additional
864 // callee-saved register or reserve a special spill slot to facilitate
865 // register scavenging. Thumb1 needs a spill slot for stack pointer
866 // adjustments also, even when the frame itself is small.
867 if (BigStack && !ExtraCSSpill) {
868 // If any non-reserved CS register isn't spilled, just spill one or two
869 // extra. That should take care of it!
870 unsigned NumExtras = TargetAlign / 4;
871 SmallVector<unsigned, 2> Extras;
872 while (NumExtras && !UnspilledCS1GPRs.empty()) {
873 unsigned Reg = UnspilledCS1GPRs.back();
874 UnspilledCS1GPRs.pop_back();
875 if (!isReservedReg(MF, Reg) &&
876 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
878 Extras.push_back(Reg);
882 // For non-Thumb1 functions, also check for hi-reg CS registers
883 if (!AFI->isThumb1OnlyFunction()) {
884 while (NumExtras && !UnspilledCS2GPRs.empty()) {
885 unsigned Reg = UnspilledCS2GPRs.back();
886 UnspilledCS2GPRs.pop_back();
887 if (!isReservedReg(MF, Reg)) {
888 Extras.push_back(Reg);
893 if (Extras.size() && NumExtras == 0) {
894 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
895 MF.getRegInfo().setPhysRegUsed(Extras[i]);
896 AFI->setCSRegisterIsSpilled(Extras[i]);
898 } else if (!AFI->isThumb1OnlyFunction()) {
899 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
900 // closest to SP or frame pointer.
901 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
902 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
910 MF.getRegInfo().setPhysRegUsed(ARM::LR);
911 AFI->setCSRegisterIsSpilled(ARM::LR);
912 AFI->setLRIsSpilledForFarJump(true);
916 unsigned ARMBaseRegisterInfo::getRARegister() const {
921 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
922 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
929 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
930 llvm_unreachable("What is the exception register");
934 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
935 llvm_unreachable("What is the exception handler register");
939 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
940 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
943 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
944 const MachineFunction &MF) const {
947 // Return 0 if either register of the pair is a special register.
956 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
959 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
961 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1033 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1034 const MachineFunction &MF) const {
1037 // Return 0 if either register of the pair is a special register.
1046 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1049 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1051 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1123 /// emitLoadConstPool - Emits a load from constpool to materialize the
1124 /// specified immediate.
1125 void ARMBaseRegisterInfo::
1126 emitLoadConstPool(MachineBasicBlock &MBB,
1127 MachineBasicBlock::iterator &MBBI,
1129 unsigned DestReg, unsigned SubIdx, int Val,
1130 ARMCC::CondCodes Pred,
1131 unsigned PredReg) const {
1132 MachineFunction &MF = *MBB.getParent();
1133 MachineConstantPool *ConstantPool = MF.getConstantPool();
1135 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1136 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1138 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1139 .addReg(DestReg, getDefRegState(true), SubIdx)
1140 .addConstantPoolIndex(Idx)
1141 .addImm(0).addImm(Pred).addReg(PredReg);
1144 bool ARMBaseRegisterInfo::
1145 requiresRegisterScavenging(const MachineFunction &MF) const {
1149 bool ARMBaseRegisterInfo::
1150 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1154 bool ARMBaseRegisterInfo::
1155 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1156 return EnableLocalStackAlloc;
1160 emitSPUpdate(bool isARM,
1161 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1162 DebugLoc dl, const ARMBaseInstrInfo &TII,
1164 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1166 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1167 Pred, PredReg, TII);
1169 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1170 Pred, PredReg, TII);
1174 void ARMBaseRegisterInfo::
1175 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1176 MachineBasicBlock::iterator I) const {
1177 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1178 if (!TFI->hasReservedCallFrame(MF)) {
1179 // If we have alloca, convert as follows:
1180 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1181 // ADJCALLSTACKUP -> add, sp, sp, amount
1182 MachineInstr *Old = I;
1183 DebugLoc dl = Old->getDebugLoc();
1184 unsigned Amount = Old->getOperand(0).getImm();
1186 // We need to keep the stack aligned properly. To do this, we round the
1187 // amount of space needed for the outgoing arguments up to the next
1188 // alignment boundary.
1189 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1190 Amount = (Amount+Align-1)/Align*Align;
1192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1193 assert(!AFI->isThumb1OnlyFunction() &&
1194 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1195 bool isARM = !AFI->isThumbFunction();
1197 // Replace the pseudo instruction with a new instruction...
1198 unsigned Opc = Old->getOpcode();
1199 int PIdx = Old->findFirstPredOperandIdx();
1200 ARMCC::CondCodes Pred = (PIdx == -1)
1201 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1202 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1203 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1204 unsigned PredReg = Old->getOperand(2).getReg();
1205 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1207 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1208 unsigned PredReg = Old->getOperand(3).getReg();
1209 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1210 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1217 int64_t ARMBaseRegisterInfo::
1218 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1219 const TargetInstrDesc &Desc = MI->getDesc();
1220 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1221 int64_t InstrOffs = 0;;
1223 unsigned ImmIdx = 0;
1225 case ARMII::AddrModeT2_i8:
1226 case ARMII::AddrModeT2_i12:
1227 case ARMII::AddrMode_i12:
1228 InstrOffs = MI->getOperand(Idx+1).getImm();
1231 case ARMII::AddrMode5: {
1232 // VFP address mode.
1233 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1234 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1235 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1236 InstrOffs = -InstrOffs;
1240 case ARMII::AddrMode2: {
1242 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1243 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1244 InstrOffs = -InstrOffs;
1247 case ARMII::AddrMode3: {
1249 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1250 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1251 InstrOffs = -InstrOffs;
1254 case ARMII::AddrModeT1_s: {
1256 InstrOffs = MI->getOperand(ImmIdx).getImm();
1261 llvm_unreachable("Unsupported addressing mode!");
1265 return InstrOffs * Scale;
1268 /// needsFrameBaseReg - Returns true if the instruction's frame index
1269 /// reference would be better served by a base register other than FP
1270 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1271 /// references it should create new base registers for.
1272 bool ARMBaseRegisterInfo::
1273 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1274 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1275 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1278 // It's the load/store FI references that cause issues, as it can be difficult
1279 // to materialize the offset if it won't fit in the literal field. Estimate
1280 // based on the size of the local frame and some conservative assumptions
1281 // about the rest of the stack frame (note, this is pre-regalloc, so
1282 // we don't know everything for certain yet) whether this offset is likely
1283 // to be out of range of the immediate. Return true if so.
1285 // We only generate virtual base registers for loads and stores, so
1286 // return false for everything else.
1287 unsigned Opc = MI->getOpcode();
1289 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1290 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1291 case ARM::t2LDRi12: case ARM::t2LDRi8:
1292 case ARM::t2STRi12: case ARM::t2STRi8:
1293 case ARM::VLDRS: case ARM::VLDRD:
1294 case ARM::VSTRS: case ARM::VSTRD:
1295 case ARM::tSTRspi: case ARM::tLDRspi:
1296 if (ForceAllBaseRegAlloc)
1303 // Without a virtual base register, if the function has variable sized
1304 // objects, all fixed-size local references will be via the frame pointer,
1305 // Approximate the offset and see if it's legal for the instruction.
1306 // Note that the incoming offset is based on the SP value at function entry,
1307 // so it'll be negative.
1308 MachineFunction &MF = *MI->getParent()->getParent();
1309 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1310 MachineFrameInfo *MFI = MF.getFrameInfo();
1311 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1313 // Estimate an offset from the frame pointer.
1314 // Conservatively assume all callee-saved registers get pushed. R4-R6
1315 // will be earlier than the FP, so we ignore those.
1317 int64_t FPOffset = Offset - 8;
1318 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1319 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1321 // Estimate an offset from the stack pointer.
1322 // The incoming offset is relating to the SP at the start of the function,
1323 // but when we access the local it'll be relative to the SP after local
1324 // allocation, so adjust our SP-relative offset by that allocation size.
1326 Offset += MFI->getLocalFrameSize();
1327 // Assume that we'll have at least some spill slots allocated.
1328 // FIXME: This is a total SWAG number. We should run some statistics
1329 // and pick a real one.
1330 Offset += 128; // 128 bytes of spill slots
1332 // If there is a frame pointer, try using it.
1333 // The FP is only available if there is no dynamic realignment. We
1334 // don't know for sure yet whether we'll need that, so we guess based
1335 // on whether there are any local variables that would trigger it.
1336 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1337 if (TFI->hasFP(MF) &&
1338 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1339 if (isFrameOffsetLegal(MI, FPOffset))
1342 // If we can reference via the stack pointer, try that.
1343 // FIXME: This (and the code that resolves the references) can be improved
1344 // to only disallow SP relative references in the live range of
1345 // the VLA(s). In practice, it's unclear how much difference that
1346 // would make, but it may be worth doing.
1347 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1350 // The offset likely isn't legal, we want to allocate a virtual base register.
1354 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1355 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1356 void ARMBaseRegisterInfo::
1357 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1358 int FrameIdx, int64_t Offset) const {
1359 ARMFunctionInfo *AFI =
1360 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1361 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1362 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1364 MachineInstrBuilder MIB =
1365 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1366 .addFrameIndex(FrameIdx).addImm(Offset);
1367 if (!AFI->isThumb1OnlyFunction())
1368 AddDefaultCC(AddDefaultPred(MIB));
1372 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1373 unsigned BaseReg, int64_t Offset) const {
1374 MachineInstr &MI = *I;
1375 MachineBasicBlock &MBB = *MI.getParent();
1376 MachineFunction &MF = *MBB.getParent();
1377 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1378 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1381 assert(!AFI->isThumb1OnlyFunction() &&
1382 "This resolveFrameIndex does not support Thumb1!");
1384 while (!MI.getOperand(i).isFI()) {
1386 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1389 if (!AFI->isThumbFunction())
1390 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1392 assert(AFI->isThumb2Function());
1393 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1395 assert (Done && "Unable to resolve frame index!");
1398 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1399 int64_t Offset) const {
1400 const TargetInstrDesc &Desc = MI->getDesc();
1401 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1404 while (!MI->getOperand(i).isFI()) {
1406 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1409 // AddrMode4 and AddrMode6 cannot handle any offset.
1410 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1413 unsigned NumBits = 0;
1415 bool isSigned = true;
1417 case ARMII::AddrModeT2_i8:
1418 case ARMII::AddrModeT2_i12:
1419 // i8 supports only negative, and i12 supports only positive, so
1420 // based on Offset sign, consider the appropriate instruction
1429 case ARMII::AddrMode5:
1430 // VFP address mode.
1434 case ARMII::AddrMode_i12:
1435 case ARMII::AddrMode2:
1438 case ARMII::AddrMode3:
1441 case ARMII::AddrModeT1_s:
1447 llvm_unreachable("Unsupported addressing mode!");
1451 Offset += getFrameIndexInstrOffset(MI, i);
1452 // Make sure the offset is encodable for instructions that scale the
1454 if ((Offset & (Scale-1)) != 0)
1457 if (isSigned && Offset < 0)
1460 unsigned Mask = (1 << NumBits) - 1;
1461 if ((unsigned)Offset <= Mask * Scale)
1468 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1469 int SPAdj, RegScavenger *RS) const {
1471 MachineInstr &MI = *II;
1472 MachineBasicBlock &MBB = *MI.getParent();
1473 MachineFunction &MF = *MBB.getParent();
1474 const ARMFrameInfo *TFI =
1475 static_cast<const ARMFrameInfo*>(MF.getTarget().getFrameInfo());
1476 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1477 assert(!AFI->isThumb1OnlyFunction() &&
1478 "This eliminateFrameIndex does not support Thumb1!");
1480 while (!MI.getOperand(i).isFI()) {
1482 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1485 int FrameIndex = MI.getOperand(i).getIndex();
1488 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1490 // Special handling of dbg_value instructions.
1491 if (MI.isDebugValue()) {
1492 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1493 MI.getOperand(i+1).ChangeToImmediate(Offset);
1497 // Modify MI as necessary to handle as much of 'Offset' as possible
1499 if (!AFI->isThumbFunction())
1500 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1502 assert(AFI->isThumb2Function());
1503 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1508 // If we get here, the immediate doesn't fit into the instruction. We folded
1509 // as much as possible above, handle the rest, providing a register that is
1512 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1513 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1514 "This code isn't needed if offset already handled!");
1516 unsigned ScratchReg = 0;
1517 int PIdx = MI.findFirstPredOperandIdx();
1518 ARMCC::CondCodes Pred = (PIdx == -1)
1519 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1520 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1522 // Must be addrmode4/6.
1523 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1525 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1526 if (!AFI->isThumbFunction())
1527 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1528 Offset, Pred, PredReg, TII);
1530 assert(AFI->isThumb2Function());
1531 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1532 Offset, Pred, PredReg, TII);
1534 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1538 #include "ARMGenRegisterInfo.inc"