1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "ARMGenRegisterInfo.inc"
48 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49 cl::desc("Force use of virtual base registers for stack load/store"));
51 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58 const ARMSubtarget &sti)
59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66 static const unsigned CalleeSavedRegs[] = {
67 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
68 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
70 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
71 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
75 static const unsigned iOSCalleeSavedRegs[] = {
76 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved
78 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
79 ARM::R11, ARM::R10, ARM::R8,
81 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
82 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
85 return (STI.isTargetIOS()) ? iOSCalleeSavedRegs : CalleeSavedRegs;
88 BitVector ARMBaseRegisterInfo::
89 getReservedRegs(const MachineFunction &MF) const {
90 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
92 // FIXME: avoid re-calculating this every time.
93 BitVector Reserved(getNumRegs());
94 Reserved.set(ARM::SP);
95 Reserved.set(ARM::PC);
96 Reserved.set(ARM::FPSCR);
98 Reserved.set(FramePtr);
99 if (hasBasePointer(MF))
100 Reserved.set(BasePtr);
101 // Some targets reserve R9.
102 if (STI.isR9Reserved())
103 Reserved.set(ARM::R9);
104 // Reserve D16-D31 if the subtarget doesn't support them.
105 if (!STI.hasVFP3() || STI.hasD16()) {
106 assert(ARM::D31 == ARM::D16 + 15);
107 for (unsigned i = 0; i != 16; ++i)
108 Reserved.set(ARM::D16 + i);
113 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
114 unsigned Reg) const {
115 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
123 if (hasBasePointer(MF))
128 if (FramePtr == Reg && TFI->hasFP(MF))
132 return STI.isR9Reserved();
139 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
140 SmallVectorImpl<unsigned> &SubIndices,
141 unsigned &NewSubIdx) const {
143 unsigned Size = RC->getSize() * 8;
147 NewSubIdx = 0; // Whole register.
148 unsigned NumRegs = SubIndices.size();
150 // 8 D registers -> 1 QQQQ register.
151 return (Size == 512 &&
152 SubIndices[0] == ARM::dsub_0 &&
153 SubIndices[1] == ARM::dsub_1 &&
154 SubIndices[2] == ARM::dsub_2 &&
155 SubIndices[3] == ARM::dsub_3 &&
156 SubIndices[4] == ARM::dsub_4 &&
157 SubIndices[5] == ARM::dsub_5 &&
158 SubIndices[6] == ARM::dsub_6 &&
159 SubIndices[7] == ARM::dsub_7);
160 } else if (NumRegs == 4) {
161 if (SubIndices[0] == ARM::qsub_0) {
162 // 4 Q registers -> 1 QQQQ register.
163 return (Size == 512 &&
164 SubIndices[1] == ARM::qsub_1 &&
165 SubIndices[2] == ARM::qsub_2 &&
166 SubIndices[3] == ARM::qsub_3);
167 } else if (SubIndices[0] == ARM::dsub_0) {
168 // 4 D registers -> 1 QQ register.
170 SubIndices[1] == ARM::dsub_1 &&
171 SubIndices[2] == ARM::dsub_2 &&
172 SubIndices[3] == ARM::dsub_3) {
174 NewSubIdx = ARM::qqsub_0;
177 } else if (SubIndices[0] == ARM::dsub_4) {
178 // 4 D registers -> 1 QQ register (2nd).
180 SubIndices[1] == ARM::dsub_5 &&
181 SubIndices[2] == ARM::dsub_6 &&
182 SubIndices[3] == ARM::dsub_7) {
183 NewSubIdx = ARM::qqsub_1;
186 } else if (SubIndices[0] == ARM::ssub_0) {
187 // 4 S registers -> 1 Q register.
189 SubIndices[1] == ARM::ssub_1 &&
190 SubIndices[2] == ARM::ssub_2 &&
191 SubIndices[3] == ARM::ssub_3) {
193 NewSubIdx = ARM::qsub_0;
197 } else if (NumRegs == 2) {
198 if (SubIndices[0] == ARM::qsub_0) {
199 // 2 Q registers -> 1 QQ register.
200 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
202 NewSubIdx = ARM::qqsub_0;
205 } else if (SubIndices[0] == ARM::qsub_2) {
206 // 2 Q registers -> 1 QQ register (2nd).
207 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
208 NewSubIdx = ARM::qqsub_1;
211 } else if (SubIndices[0] == ARM::dsub_0) {
212 // 2 D registers -> 1 Q register.
213 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
215 NewSubIdx = ARM::qsub_0;
218 } else if (SubIndices[0] == ARM::dsub_2) {
219 // 2 D registers -> 1 Q register (2nd).
220 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
221 NewSubIdx = ARM::qsub_1;
224 } else if (SubIndices[0] == ARM::dsub_4) {
225 // 2 D registers -> 1 Q register (3rd).
226 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
227 NewSubIdx = ARM::qsub_2;
230 } else if (SubIndices[0] == ARM::dsub_6) {
231 // 2 D registers -> 1 Q register (3rd).
232 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
233 NewSubIdx = ARM::qsub_3;
236 } else if (SubIndices[0] == ARM::ssub_0) {
237 // 2 S registers -> 1 D register.
238 if (SubIndices[1] == ARM::ssub_1) {
240 NewSubIdx = ARM::dsub_0;
243 } else if (SubIndices[0] == ARM::ssub_2) {
244 // 2 S registers -> 1 D register (2nd).
245 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
246 NewSubIdx = ARM::dsub_1;
254 const TargetRegisterClass*
255 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
257 const TargetRegisterClass *Super = RC;
258 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
260 switch (Super->getID()) {
261 case ARM::GPRRegClassID:
262 case ARM::SPRRegClassID:
263 case ARM::DPRRegClassID:
264 case ARM::QPRRegClassID:
265 case ARM::QQPRRegClassID:
266 case ARM::QQQQPRRegClassID:
274 const TargetRegisterClass *
275 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
276 return ARM::GPRRegisterClass;
279 const TargetRegisterClass *
280 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
281 if (RC == &ARM::CCRRegClass)
282 return 0; // Can't copy CCR registers.
287 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
288 MachineFunction &MF) const {
289 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
291 switch (RC->getID()) {
294 case ARM::tGPRRegClassID:
295 return TFI->hasFP(MF) ? 4 : 5;
296 case ARM::GPRRegClassID: {
297 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
298 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
300 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
301 case ARM::DPRRegClassID:
306 /// getRawAllocationOrder - Returns the register allocation order for a
307 /// specified register class with a target-dependent hint.
309 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
310 unsigned HintType, unsigned HintReg,
311 const MachineFunction &MF) const {
312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
313 // Alternative register allocation orders when favoring even / odd registers
314 // of register pairs.
316 // No FP, R9 is available.
317 static const unsigned GPREven1[] = {
318 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
322 static const unsigned GPROdd1[] = {
323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
328 // FP is R7, R9 is available.
329 static const unsigned GPREven2[] = {
330 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
334 static const unsigned GPROdd2[] = {
335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
340 // FP is R11, R9 is available.
341 static const unsigned GPREven3[] = {
342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
346 static const unsigned GPROdd3[] = {
347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
352 // No FP, R9 is not available.
353 static const unsigned GPREven4[] = {
354 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
358 static const unsigned GPROdd4[] = {
359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
364 // FP is R7, R9 is not available.
365 static const unsigned GPREven5[] = {
366 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
370 static const unsigned GPROdd5[] = {
371 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
372 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
376 // FP is R11, R9 is not available.
377 static const unsigned GPREven6[] = {
378 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
379 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
381 static const unsigned GPROdd6[] = {
382 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
383 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
386 // We only support even/odd hints for GPR and rGPR.
387 if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
388 return RC->getRawAllocationOrder(MF);
390 if (HintType == ARMRI::RegPairEven) {
391 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
392 // It's no longer possible to fulfill this hint. Return the default
394 return RC->getRawAllocationOrder(MF);
396 if (!TFI->hasFP(MF)) {
397 if (!STI.isR9Reserved())
398 return makeArrayRef(GPREven1);
400 return makeArrayRef(GPREven4);
401 } else if (FramePtr == ARM::R7) {
402 if (!STI.isR9Reserved())
403 return makeArrayRef(GPREven2);
405 return makeArrayRef(GPREven5);
406 } else { // FramePtr == ARM::R11
407 if (!STI.isR9Reserved())
408 return makeArrayRef(GPREven3);
410 return makeArrayRef(GPREven6);
412 } else if (HintType == ARMRI::RegPairOdd) {
413 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
414 // It's no longer possible to fulfill this hint. Return the default
416 return RC->getRawAllocationOrder(MF);
418 if (!TFI->hasFP(MF)) {
419 if (!STI.isR9Reserved())
420 return makeArrayRef(GPROdd1);
422 return makeArrayRef(GPROdd4);
423 } else if (FramePtr == ARM::R7) {
424 if (!STI.isR9Reserved())
425 return makeArrayRef(GPROdd2);
427 return makeArrayRef(GPROdd5);
428 } else { // FramePtr == ARM::R11
429 if (!STI.isR9Reserved())
430 return makeArrayRef(GPROdd3);
432 return makeArrayRef(GPROdd6);
435 return RC->getRawAllocationOrder(MF);
438 /// ResolveRegAllocHint - Resolves the specified register allocation hint
439 /// to a physical register. Returns the physical register if it is successful.
441 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
442 const MachineFunction &MF) const {
443 if (Reg == 0 || !isPhysicalRegister(Reg))
447 else if (Type == (unsigned)ARMRI::RegPairOdd)
449 return getRegisterPairOdd(Reg, MF);
450 else if (Type == (unsigned)ARMRI::RegPairEven)
452 return getRegisterPairEven(Reg, MF);
457 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
458 MachineFunction &MF) const {
459 MachineRegisterInfo *MRI = &MF.getRegInfo();
460 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
461 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
462 Hint.first == (unsigned)ARMRI::RegPairEven) &&
463 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
464 // If 'Reg' is one of the even / odd register pair and it's now changed
465 // (e.g. coalesced) into a different register. The other register of the
466 // pair allocation hint must be updated to reflect the relationship
468 unsigned OtherReg = Hint.second;
469 Hint = MRI->getRegAllocationHint(OtherReg);
470 if (Hint.second == Reg)
471 // Make sure the pair has not already divorced.
472 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
477 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
478 // CortexA9 has a Write-after-write hazard for NEON registers.
479 if (!STI.isCortexA9())
482 switch (RC->getID()) {
483 case ARM::DPRRegClassID:
484 case ARM::DPR_8RegClassID:
485 case ARM::DPR_VFP2RegClassID:
486 case ARM::QPRRegClassID:
487 case ARM::QPR_8RegClassID:
488 case ARM::QPR_VFP2RegClassID:
489 case ARM::SPRRegClassID:
490 case ARM::SPR_8RegClassID:
491 // Avoid reusing S, D, and Q registers.
492 // Don't increase register pressure for QQ and QQQQ.
499 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
500 const MachineFrameInfo *MFI = MF.getFrameInfo();
501 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
503 if (!EnableBasePointer)
506 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
509 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
510 // negative range for ldr/str (255), and thumb1 is positive offsets only.
511 // It's going to be better to use the SP or Base Pointer instead. When there
512 // are variable sized objects, we can't reference off of the SP, so we
513 // reserve a Base Pointer.
514 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
515 // Conservatively estimate whether the negative offset from the frame
516 // pointer will be sufficient to reach. If a function has a smallish
517 // frame, it's less likely to have lots of spills and callee saved
518 // space, so it's all more likely to be within range of the frame pointer.
519 // If it's wrong, the scavenger will still enable access to work, it just
521 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
529 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
530 const MachineFrameInfo *MFI = MF.getFrameInfo();
531 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
532 // We can't realign the stack if:
533 // 1. Dynamic stack realignment is explicitly disabled,
534 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
535 // 3. There are VLAs in the function and the base pointer is disabled.
536 return (MF.getTarget().Options.RealignStack && !AFI->isThumb1OnlyFunction() &&
537 (!MFI->hasVarSizedObjects() || EnableBasePointer));
540 bool ARMBaseRegisterInfo::
541 needsStackRealignment(const MachineFunction &MF) const {
542 const MachineFrameInfo *MFI = MF.getFrameInfo();
543 const Function *F = MF.getFunction();
544 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
545 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
546 F->hasFnAttr(Attribute::StackAlignment));
548 return requiresRealignment && canRealignStack(MF);
551 bool ARMBaseRegisterInfo::
552 cannotEliminateFrame(const MachineFunction &MF) const {
553 const MachineFrameInfo *MFI = MF.getFrameInfo();
554 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
556 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
557 || needsStackRealignment(MF);
561 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
562 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
569 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
570 llvm_unreachable("What is the exception register");
574 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
575 llvm_unreachable("What is the exception handler register");
579 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
580 const MachineFunction &MF) const {
583 // Return 0 if either register of the pair is a special register.
585 case ARM::R1: return ARM::R0;
586 case ARM::R3: return ARM::R2;
587 case ARM::R5: return ARM::R4;
589 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
591 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
592 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
594 case ARM::S1: return ARM::S0;
595 case ARM::S3: return ARM::S2;
596 case ARM::S5: return ARM::S4;
597 case ARM::S7: return ARM::S6;
598 case ARM::S9: return ARM::S8;
599 case ARM::S11: return ARM::S10;
600 case ARM::S13: return ARM::S12;
601 case ARM::S15: return ARM::S14;
602 case ARM::S17: return ARM::S16;
603 case ARM::S19: return ARM::S18;
604 case ARM::S21: return ARM::S20;
605 case ARM::S23: return ARM::S22;
606 case ARM::S25: return ARM::S24;
607 case ARM::S27: return ARM::S26;
608 case ARM::S29: return ARM::S28;
609 case ARM::S31: return ARM::S30;
611 case ARM::D1: return ARM::D0;
612 case ARM::D3: return ARM::D2;
613 case ARM::D5: return ARM::D4;
614 case ARM::D7: return ARM::D6;
615 case ARM::D9: return ARM::D8;
616 case ARM::D11: return ARM::D10;
617 case ARM::D13: return ARM::D12;
618 case ARM::D15: return ARM::D14;
619 case ARM::D17: return ARM::D16;
620 case ARM::D19: return ARM::D18;
621 case ARM::D21: return ARM::D20;
622 case ARM::D23: return ARM::D22;
623 case ARM::D25: return ARM::D24;
624 case ARM::D27: return ARM::D26;
625 case ARM::D29: return ARM::D28;
626 case ARM::D31: return ARM::D30;
632 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
633 const MachineFunction &MF) const {
636 // Return 0 if either register of the pair is a special register.
638 case ARM::R0: return ARM::R1;
639 case ARM::R2: return ARM::R3;
640 case ARM::R4: return ARM::R5;
642 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
644 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
645 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
647 case ARM::S0: return ARM::S1;
648 case ARM::S2: return ARM::S3;
649 case ARM::S4: return ARM::S5;
650 case ARM::S6: return ARM::S7;
651 case ARM::S8: return ARM::S9;
652 case ARM::S10: return ARM::S11;
653 case ARM::S12: return ARM::S13;
654 case ARM::S14: return ARM::S15;
655 case ARM::S16: return ARM::S17;
656 case ARM::S18: return ARM::S19;
657 case ARM::S20: return ARM::S21;
658 case ARM::S22: return ARM::S23;
659 case ARM::S24: return ARM::S25;
660 case ARM::S26: return ARM::S27;
661 case ARM::S28: return ARM::S29;
662 case ARM::S30: return ARM::S31;
664 case ARM::D0: return ARM::D1;
665 case ARM::D2: return ARM::D3;
666 case ARM::D4: return ARM::D5;
667 case ARM::D6: return ARM::D7;
668 case ARM::D8: return ARM::D9;
669 case ARM::D10: return ARM::D11;
670 case ARM::D12: return ARM::D13;
671 case ARM::D14: return ARM::D15;
672 case ARM::D16: return ARM::D17;
673 case ARM::D18: return ARM::D19;
674 case ARM::D20: return ARM::D21;
675 case ARM::D22: return ARM::D23;
676 case ARM::D24: return ARM::D25;
677 case ARM::D26: return ARM::D27;
678 case ARM::D28: return ARM::D29;
679 case ARM::D30: return ARM::D31;
685 /// emitLoadConstPool - Emits a load from constpool to materialize the
686 /// specified immediate.
687 void ARMBaseRegisterInfo::
688 emitLoadConstPool(MachineBasicBlock &MBB,
689 MachineBasicBlock::iterator &MBBI,
691 unsigned DestReg, unsigned SubIdx, int Val,
692 ARMCC::CondCodes Pred,
693 unsigned PredReg, unsigned MIFlags) const {
694 MachineFunction &MF = *MBB.getParent();
695 MachineConstantPool *ConstantPool = MF.getConstantPool();
697 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
698 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
700 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
701 .addReg(DestReg, getDefRegState(true), SubIdx)
702 .addConstantPoolIndex(Idx)
703 .addImm(0).addImm(Pred).addReg(PredReg)
704 .setMIFlags(MIFlags);
707 bool ARMBaseRegisterInfo::
708 requiresRegisterScavenging(const MachineFunction &MF) const {
712 bool ARMBaseRegisterInfo::
713 requiresFrameIndexScavenging(const MachineFunction &MF) const {
717 bool ARMBaseRegisterInfo::
718 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
719 return EnableLocalStackAlloc;
723 emitSPUpdate(bool isARM,
724 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
725 DebugLoc dl, const ARMBaseInstrInfo &TII,
727 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
729 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
732 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
737 void ARMBaseRegisterInfo::
738 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
739 MachineBasicBlock::iterator I) const {
740 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
741 if (!TFI->hasReservedCallFrame(MF)) {
742 // If we have alloca, convert as follows:
743 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
744 // ADJCALLSTACKUP -> add, sp, sp, amount
745 MachineInstr *Old = I;
746 DebugLoc dl = Old->getDebugLoc();
747 unsigned Amount = Old->getOperand(0).getImm();
749 // We need to keep the stack aligned properly. To do this, we round the
750 // amount of space needed for the outgoing arguments up to the next
751 // alignment boundary.
752 unsigned Align = TFI->getStackAlignment();
753 Amount = (Amount+Align-1)/Align*Align;
755 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
756 assert(!AFI->isThumb1OnlyFunction() &&
757 "This eliminateCallFramePseudoInstr does not support Thumb1!");
758 bool isARM = !AFI->isThumbFunction();
760 // Replace the pseudo instruction with a new instruction...
761 unsigned Opc = Old->getOpcode();
762 int PIdx = Old->findFirstPredOperandIdx();
763 ARMCC::CondCodes Pred = (PIdx == -1)
764 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
765 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
766 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
767 unsigned PredReg = Old->getOperand(2).getReg();
768 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
770 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
771 unsigned PredReg = Old->getOperand(3).getReg();
772 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
773 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
780 int64_t ARMBaseRegisterInfo::
781 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
782 const MCInstrDesc &Desc = MI->getDesc();
783 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
784 int64_t InstrOffs = 0;;
788 case ARMII::AddrModeT2_i8:
789 case ARMII::AddrModeT2_i12:
790 case ARMII::AddrMode_i12:
791 InstrOffs = MI->getOperand(Idx+1).getImm();
794 case ARMII::AddrMode5: {
796 const MachineOperand &OffOp = MI->getOperand(Idx+1);
797 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
798 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
799 InstrOffs = -InstrOffs;
803 case ARMII::AddrMode2: {
805 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
806 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
807 InstrOffs = -InstrOffs;
810 case ARMII::AddrMode3: {
812 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
813 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
814 InstrOffs = -InstrOffs;
817 case ARMII::AddrModeT1_s: {
819 InstrOffs = MI->getOperand(ImmIdx).getImm();
824 llvm_unreachable("Unsupported addressing mode!");
828 return InstrOffs * Scale;
831 /// needsFrameBaseReg - Returns true if the instruction's frame index
832 /// reference would be better served by a base register other than FP
833 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
834 /// references it should create new base registers for.
835 bool ARMBaseRegisterInfo::
836 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
837 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
838 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
841 // It's the load/store FI references that cause issues, as it can be difficult
842 // to materialize the offset if it won't fit in the literal field. Estimate
843 // based on the size of the local frame and some conservative assumptions
844 // about the rest of the stack frame (note, this is pre-regalloc, so
845 // we don't know everything for certain yet) whether this offset is likely
846 // to be out of range of the immediate. Return true if so.
848 // We only generate virtual base registers for loads and stores, so
849 // return false for everything else.
850 unsigned Opc = MI->getOpcode();
852 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
853 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
854 case ARM::t2LDRi12: case ARM::t2LDRi8:
855 case ARM::t2STRi12: case ARM::t2STRi8:
856 case ARM::VLDRS: case ARM::VLDRD:
857 case ARM::VSTRS: case ARM::VSTRD:
858 case ARM::tSTRspi: case ARM::tLDRspi:
859 if (ForceAllBaseRegAlloc)
866 // Without a virtual base register, if the function has variable sized
867 // objects, all fixed-size local references will be via the frame pointer,
868 // Approximate the offset and see if it's legal for the instruction.
869 // Note that the incoming offset is based on the SP value at function entry,
870 // so it'll be negative.
871 MachineFunction &MF = *MI->getParent()->getParent();
872 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
873 MachineFrameInfo *MFI = MF.getFrameInfo();
874 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
876 // Estimate an offset from the frame pointer.
877 // Conservatively assume all callee-saved registers get pushed. R4-R6
878 // will be earlier than the FP, so we ignore those.
880 int64_t FPOffset = Offset - 8;
881 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
882 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
884 // Estimate an offset from the stack pointer.
885 // The incoming offset is relating to the SP at the start of the function,
886 // but when we access the local it'll be relative to the SP after local
887 // allocation, so adjust our SP-relative offset by that allocation size.
889 Offset += MFI->getLocalFrameSize();
890 // Assume that we'll have at least some spill slots allocated.
891 // FIXME: This is a total SWAG number. We should run some statistics
892 // and pick a real one.
893 Offset += 128; // 128 bytes of spill slots
895 // If there is a frame pointer, try using it.
896 // The FP is only available if there is no dynamic realignment. We
897 // don't know for sure yet whether we'll need that, so we guess based
898 // on whether there are any local variables that would trigger it.
899 unsigned StackAlign = TFI->getStackAlignment();
900 if (TFI->hasFP(MF) &&
901 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
902 if (isFrameOffsetLegal(MI, FPOffset))
905 // If we can reference via the stack pointer, try that.
906 // FIXME: This (and the code that resolves the references) can be improved
907 // to only disallow SP relative references in the live range of
908 // the VLA(s). In practice, it's unclear how much difference that
909 // would make, but it may be worth doing.
910 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
913 // The offset likely isn't legal, we want to allocate a virtual base register.
917 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
918 /// be a pointer to FrameIdx at the beginning of the basic block.
919 void ARMBaseRegisterInfo::
920 materializeFrameBaseRegister(MachineBasicBlock *MBB,
921 unsigned BaseReg, int FrameIdx,
922 int64_t Offset) const {
923 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
924 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
925 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
927 MachineBasicBlock::iterator Ins = MBB->begin();
928 DebugLoc DL; // Defaults to "unknown"
929 if (Ins != MBB->end())
930 DL = Ins->getDebugLoc();
932 const MCInstrDesc &MCID = TII.get(ADDriOpc);
933 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
934 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
936 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
937 .addFrameIndex(FrameIdx).addImm(Offset));
939 if (!AFI->isThumb1OnlyFunction())
944 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
945 unsigned BaseReg, int64_t Offset) const {
946 MachineInstr &MI = *I;
947 MachineBasicBlock &MBB = *MI.getParent();
948 MachineFunction &MF = *MBB.getParent();
949 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
950 int Off = Offset; // ARM doesn't need the general 64-bit offsets
953 assert(!AFI->isThumb1OnlyFunction() &&
954 "This resolveFrameIndex does not support Thumb1!");
956 while (!MI.getOperand(i).isFI()) {
958 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
961 if (!AFI->isThumbFunction())
962 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
964 assert(AFI->isThumb2Function());
965 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
967 assert (Done && "Unable to resolve frame index!");
971 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
972 int64_t Offset) const {
973 const MCInstrDesc &Desc = MI->getDesc();
974 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
977 while (!MI->getOperand(i).isFI()) {
979 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
982 // AddrMode4 and AddrMode6 cannot handle any offset.
983 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
986 unsigned NumBits = 0;
988 bool isSigned = true;
990 case ARMII::AddrModeT2_i8:
991 case ARMII::AddrModeT2_i12:
992 // i8 supports only negative, and i12 supports only positive, so
993 // based on Offset sign, consider the appropriate instruction
1002 case ARMII::AddrMode5:
1003 // VFP address mode.
1007 case ARMII::AddrMode_i12:
1008 case ARMII::AddrMode2:
1011 case ARMII::AddrMode3:
1014 case ARMII::AddrModeT1_s:
1020 llvm_unreachable("Unsupported addressing mode!");
1024 Offset += getFrameIndexInstrOffset(MI, i);
1025 // Make sure the offset is encodable for instructions that scale the
1027 if ((Offset & (Scale-1)) != 0)
1030 if (isSigned && Offset < 0)
1033 unsigned Mask = (1 << NumBits) - 1;
1034 if ((unsigned)Offset <= Mask * Scale)
1041 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1042 int SPAdj, RegScavenger *RS) const {
1044 MachineInstr &MI = *II;
1045 MachineBasicBlock &MBB = *MI.getParent();
1046 MachineFunction &MF = *MBB.getParent();
1047 const ARMFrameLowering *TFI =
1048 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1049 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1050 assert(!AFI->isThumb1OnlyFunction() &&
1051 "This eliminateFrameIndex does not support Thumb1!");
1053 while (!MI.getOperand(i).isFI()) {
1055 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1058 int FrameIndex = MI.getOperand(i).getIndex();
1061 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1063 // Special handling of dbg_value instructions.
1064 if (MI.isDebugValue()) {
1065 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1066 MI.getOperand(i+1).ChangeToImmediate(Offset);
1070 // Modify MI as necessary to handle as much of 'Offset' as possible
1072 if (!AFI->isThumbFunction())
1073 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1075 assert(AFI->isThumb2Function());
1076 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1081 // If we get here, the immediate doesn't fit into the instruction. We folded
1082 // as much as possible above, handle the rest, providing a register that is
1085 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1086 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1087 "This code isn't needed if offset already handled!");
1089 unsigned ScratchReg = 0;
1090 int PIdx = MI.findFirstPredOperandIdx();
1091 ARMCC::CondCodes Pred = (PIdx == -1)
1092 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1093 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1095 // Must be addrmode4/6.
1096 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1098 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1099 if (!AFI->isThumbFunction())
1100 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1101 Offset, Pred, PredReg, TII);
1103 assert(AFI->isThumb2Function());
1104 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1105 Offset, Pred, PredReg, TII);
1107 // Update the original instruction to use the scratch register.
1108 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);