1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/Constants.h"
31 #include "llvm/DerivedTypes.h"
32 #include "llvm/Function.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
47 const ARMSubtarget &sti)
48 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
49 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
54 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
58 const Function *F = MF->getFunction();
59 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
63 return CSR_GHC_SaveList;
66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
67 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
72 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
73 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
74 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
78 ARMBaseRegisterInfo::getNoPreservedMask() const {
79 return CSR_NoRegs_RegMask;
82 BitVector ARMBaseRegisterInfo::
83 getReservedRegs(const MachineFunction &MF) const {
84 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
86 // FIXME: avoid re-calculating this every time.
87 BitVector Reserved(getNumRegs());
88 Reserved.set(ARM::SP);
89 Reserved.set(ARM::PC);
90 Reserved.set(ARM::FPSCR);
92 Reserved.set(FramePtr);
93 if (hasBasePointer(MF))
94 Reserved.set(BasePtr);
95 // Some targets reserve R9.
96 if (STI.isR9Reserved())
97 Reserved.set(ARM::R9);
98 // Reserve D16-D31 if the subtarget doesn't support them.
99 if (!STI.hasVFP3() || STI.hasD16()) {
100 assert(ARM::D31 == ARM::D16 + 15);
101 for (unsigned i = 0; i != 16; ++i)
102 Reserved.set(ARM::D16 + i);
104 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
105 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
106 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
107 if (Reserved.test(*SI)) Reserved.set(*I);
112 const TargetRegisterClass*
113 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
115 const TargetRegisterClass *Super = RC;
116 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
118 switch (Super->getID()) {
119 case ARM::GPRRegClassID:
120 case ARM::SPRRegClassID:
121 case ARM::DPRRegClassID:
122 case ARM::QPRRegClassID:
123 case ARM::QQPRRegClassID:
124 case ARM::QQQQPRRegClassID:
125 case ARM::GPRPairRegClassID:
133 const TargetRegisterClass *
134 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
136 return &ARM::GPRRegClass;
139 const TargetRegisterClass *
140 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
141 if (RC == &ARM::CCRRegClass)
142 return 0; // Can't copy CCR registers.
147 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
148 MachineFunction &MF) const {
149 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
151 switch (RC->getID()) {
154 case ARM::tGPRRegClassID:
155 return TFI->hasFP(MF) ? 4 : 5;
156 case ARM::GPRRegClassID: {
157 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
158 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
160 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
161 case ARM::DPRRegClassID:
166 // Get the other register in a GPRPair.
167 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
168 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
169 if (ARM::GPRPairRegClass.contains(*Supers))
170 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
174 // Resolve the RegPairEven / RegPairOdd register allocator hints.
176 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
177 ArrayRef<MCPhysReg> Order,
178 SmallVectorImpl<MCPhysReg> &Hints,
179 const MachineFunction &MF,
180 const VirtRegMap *VRM) const {
181 const MachineRegisterInfo &MRI = MF.getRegInfo();
182 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
185 switch (Hint.first) {
186 case ARMRI::RegPairEven:
189 case ARMRI::RegPairOdd:
193 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
197 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
198 // Check if the other part of the pair has already been assigned, and provide
199 // the paired register as the first hint.
200 unsigned PairedPhys = 0;
201 if (VRM && VRM->hasPhys(Hint.second)) {
202 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
203 if (PairedPhys && MRI.isReserved(PairedPhys))
207 // First prefer the paired physreg.
209 Hints.push_back(PairedPhys);
211 // Then prefer even or odd registers.
212 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
213 unsigned Reg = Order[I];
214 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
216 // Don't provide hints that are paired to a reserved register.
217 unsigned Paired = getPairedGPR(Reg, !Odd, this);
218 if (!Paired || MRI.isReserved(Paired))
220 Hints.push_back(Reg);
225 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
226 MachineFunction &MF) const {
227 MachineRegisterInfo *MRI = &MF.getRegInfo();
228 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
229 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
230 Hint.first == (unsigned)ARMRI::RegPairEven) &&
231 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
232 // If 'Reg' is one of the even / odd register pair and it's now changed
233 // (e.g. coalesced) into a different register. The other register of the
234 // pair allocation hint must be updated to reflect the relationship
236 unsigned OtherReg = Hint.second;
237 Hint = MRI->getRegAllocationHint(OtherReg);
238 if (Hint.second == Reg)
239 // Make sure the pair has not already divorced.
240 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
245 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
246 // CortexA9 has a Write-after-write hazard for NEON registers.
250 switch (RC->getID()) {
251 case ARM::DPRRegClassID:
252 case ARM::DPR_8RegClassID:
253 case ARM::DPR_VFP2RegClassID:
254 case ARM::QPRRegClassID:
255 case ARM::QPR_8RegClassID:
256 case ARM::QPR_VFP2RegClassID:
257 case ARM::SPRRegClassID:
258 case ARM::SPR_8RegClassID:
259 // Avoid reusing S, D, and Q registers.
260 // Don't increase register pressure for QQ and QQQQ.
267 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
268 const MachineFrameInfo *MFI = MF.getFrameInfo();
269 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
270 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
272 // When outgoing call frames are so large that we adjust the stack pointer
273 // around the call, we can no longer use the stack pointer to reach the
274 // emergency spill slot.
275 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
278 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
279 // negative range for ldr/str (255), and thumb1 is positive offsets only.
280 // It's going to be better to use the SP or Base Pointer instead. When there
281 // are variable sized objects, we can't reference off of the SP, so we
282 // reserve a Base Pointer.
283 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
284 // Conservatively estimate whether the negative offset from the frame
285 // pointer will be sufficient to reach. If a function has a smallish
286 // frame, it's less likely to have lots of spills and callee saved
287 // space, so it's all more likely to be within range of the frame pointer.
288 // If it's wrong, the scavenger will still enable access to work, it just
290 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
298 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
299 const MachineRegisterInfo *MRI = &MF.getRegInfo();
300 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
301 // We can't realign the stack if:
302 // 1. Dynamic stack realignment is explicitly disabled,
303 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
304 // 3. There are VLAs in the function and the base pointer is disabled.
305 if (!MF.getTarget().Options.RealignStack)
307 if (AFI->isThumb1OnlyFunction())
309 // Stack realignment requires a frame pointer. If we already started
310 // register allocation with frame pointer elimination, it is too late now.
311 if (!MRI->canReserveReg(FramePtr))
313 // We may also need a base pointer if there are dynamic allocas or stack
314 // pointer adjustments around calls.
315 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
317 // A base pointer is required and allowed. Check that it isn't too late to
319 return MRI->canReserveReg(BasePtr);
322 bool ARMBaseRegisterInfo::
323 needsStackRealignment(const MachineFunction &MF) const {
324 const MachineFrameInfo *MFI = MF.getFrameInfo();
325 const Function *F = MF.getFunction();
326 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
327 bool requiresRealignment =
328 ((MFI->getMaxAlignment() > StackAlign) ||
329 F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
331 return requiresRealignment && canRealignStack(MF);
334 bool ARMBaseRegisterInfo::
335 cannotEliminateFrame(const MachineFunction &MF) const {
336 const MachineFrameInfo *MFI = MF.getFrameInfo();
337 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
339 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
340 || needsStackRealignment(MF);
344 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
345 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
352 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
353 llvm_unreachable("What is the exception register");
356 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
357 llvm_unreachable("What is the exception handler register");
360 /// emitLoadConstPool - Emits a load from constpool to materialize the
361 /// specified immediate.
362 void ARMBaseRegisterInfo::
363 emitLoadConstPool(MachineBasicBlock &MBB,
364 MachineBasicBlock::iterator &MBBI,
366 unsigned DestReg, unsigned SubIdx, int Val,
367 ARMCC::CondCodes Pred,
368 unsigned PredReg, unsigned MIFlags) const {
369 MachineFunction &MF = *MBB.getParent();
370 MachineConstantPool *ConstantPool = MF.getConstantPool();
372 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
373 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
375 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
376 .addReg(DestReg, getDefRegState(true), SubIdx)
377 .addConstantPoolIndex(Idx)
378 .addImm(0).addImm(Pred).addReg(PredReg)
379 .setMIFlags(MIFlags);
382 bool ARMBaseRegisterInfo::
383 requiresRegisterScavenging(const MachineFunction &MF) const {
387 bool ARMBaseRegisterInfo::
388 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
392 bool ARMBaseRegisterInfo::
393 requiresFrameIndexScavenging(const MachineFunction &MF) const {
397 bool ARMBaseRegisterInfo::
398 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
403 emitSPUpdate(bool isARM,
404 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
405 DebugLoc dl, const ARMBaseInstrInfo &TII,
407 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
409 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
412 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
417 void ARMBaseRegisterInfo::
418 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
419 MachineBasicBlock::iterator I) const {
420 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
421 if (!TFI->hasReservedCallFrame(MF)) {
422 // If we have alloca, convert as follows:
423 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
424 // ADJCALLSTACKUP -> add, sp, sp, amount
425 MachineInstr *Old = I;
426 DebugLoc dl = Old->getDebugLoc();
427 unsigned Amount = Old->getOperand(0).getImm();
429 // We need to keep the stack aligned properly. To do this, we round the
430 // amount of space needed for the outgoing arguments up to the next
431 // alignment boundary.
432 unsigned Align = TFI->getStackAlignment();
433 Amount = (Amount+Align-1)/Align*Align;
435 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
436 assert(!AFI->isThumb1OnlyFunction() &&
437 "This eliminateCallFramePseudoInstr does not support Thumb1!");
438 bool isARM = !AFI->isThumbFunction();
440 // Replace the pseudo instruction with a new instruction...
441 unsigned Opc = Old->getOpcode();
442 int PIdx = Old->findFirstPredOperandIdx();
443 ARMCC::CondCodes Pred = (PIdx == -1)
444 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
445 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
446 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
447 unsigned PredReg = Old->getOperand(2).getReg();
448 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
450 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
451 unsigned PredReg = Old->getOperand(3).getReg();
452 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
453 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
460 int64_t ARMBaseRegisterInfo::
461 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
462 const MCInstrDesc &Desc = MI->getDesc();
463 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
464 int64_t InstrOffs = 0;
468 case ARMII::AddrModeT2_i8:
469 case ARMII::AddrModeT2_i12:
470 case ARMII::AddrMode_i12:
471 InstrOffs = MI->getOperand(Idx+1).getImm();
474 case ARMII::AddrMode5: {
476 const MachineOperand &OffOp = MI->getOperand(Idx+1);
477 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
478 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
479 InstrOffs = -InstrOffs;
483 case ARMII::AddrMode2: {
485 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
486 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
487 InstrOffs = -InstrOffs;
490 case ARMII::AddrMode3: {
492 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
493 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
494 InstrOffs = -InstrOffs;
497 case ARMII::AddrModeT1_s: {
499 InstrOffs = MI->getOperand(ImmIdx).getImm();
504 llvm_unreachable("Unsupported addressing mode!");
507 return InstrOffs * Scale;
510 /// needsFrameBaseReg - Returns true if the instruction's frame index
511 /// reference would be better served by a base register other than FP
512 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
513 /// references it should create new base registers for.
514 bool ARMBaseRegisterInfo::
515 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
516 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
517 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
520 // It's the load/store FI references that cause issues, as it can be difficult
521 // to materialize the offset if it won't fit in the literal field. Estimate
522 // based on the size of the local frame and some conservative assumptions
523 // about the rest of the stack frame (note, this is pre-regalloc, so
524 // we don't know everything for certain yet) whether this offset is likely
525 // to be out of range of the immediate. Return true if so.
527 // We only generate virtual base registers for loads and stores, so
528 // return false for everything else.
529 unsigned Opc = MI->getOpcode();
531 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
532 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
533 case ARM::t2LDRi12: case ARM::t2LDRi8:
534 case ARM::t2STRi12: case ARM::t2STRi8:
535 case ARM::VLDRS: case ARM::VLDRD:
536 case ARM::VSTRS: case ARM::VSTRD:
537 case ARM::tSTRspi: case ARM::tLDRspi:
543 // Without a virtual base register, if the function has variable sized
544 // objects, all fixed-size local references will be via the frame pointer,
545 // Approximate the offset and see if it's legal for the instruction.
546 // Note that the incoming offset is based on the SP value at function entry,
547 // so it'll be negative.
548 MachineFunction &MF = *MI->getParent()->getParent();
549 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
550 MachineFrameInfo *MFI = MF.getFrameInfo();
551 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
553 // Estimate an offset from the frame pointer.
554 // Conservatively assume all callee-saved registers get pushed. R4-R6
555 // will be earlier than the FP, so we ignore those.
557 int64_t FPOffset = Offset - 8;
558 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
559 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
561 // Estimate an offset from the stack pointer.
562 // The incoming offset is relating to the SP at the start of the function,
563 // but when we access the local it'll be relative to the SP after local
564 // allocation, so adjust our SP-relative offset by that allocation size.
566 Offset += MFI->getLocalFrameSize();
567 // Assume that we'll have at least some spill slots allocated.
568 // FIXME: This is a total SWAG number. We should run some statistics
569 // and pick a real one.
570 Offset += 128; // 128 bytes of spill slots
572 // If there is a frame pointer, try using it.
573 // The FP is only available if there is no dynamic realignment. We
574 // don't know for sure yet whether we'll need that, so we guess based
575 // on whether there are any local variables that would trigger it.
576 unsigned StackAlign = TFI->getStackAlignment();
577 if (TFI->hasFP(MF) &&
578 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
579 if (isFrameOffsetLegal(MI, FPOffset))
582 // If we can reference via the stack pointer, try that.
583 // FIXME: This (and the code that resolves the references) can be improved
584 // to only disallow SP relative references in the live range of
585 // the VLA(s). In practice, it's unclear how much difference that
586 // would make, but it may be worth doing.
587 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
590 // The offset likely isn't legal, we want to allocate a virtual base register.
594 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
595 /// be a pointer to FrameIdx at the beginning of the basic block.
596 void ARMBaseRegisterInfo::
597 materializeFrameBaseRegister(MachineBasicBlock *MBB,
598 unsigned BaseReg, int FrameIdx,
599 int64_t Offset) const {
600 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
601 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
602 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
604 MachineBasicBlock::iterator Ins = MBB->begin();
605 DebugLoc DL; // Defaults to "unknown"
606 if (Ins != MBB->end())
607 DL = Ins->getDebugLoc();
609 const MCInstrDesc &MCID = TII.get(ADDriOpc);
610 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
611 const MachineFunction &MF = *MBB->getParent();
612 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
614 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
615 .addFrameIndex(FrameIdx).addImm(Offset));
617 if (!AFI->isThumb1OnlyFunction())
622 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
623 unsigned BaseReg, int64_t Offset) const {
624 MachineInstr &MI = *I;
625 MachineBasicBlock &MBB = *MI.getParent();
626 MachineFunction &MF = *MBB.getParent();
627 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
628 int Off = Offset; // ARM doesn't need the general 64-bit offsets
631 assert(!AFI->isThumb1OnlyFunction() &&
632 "This resolveFrameIndex does not support Thumb1!");
634 while (!MI.getOperand(i).isFI()) {
636 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
639 if (!AFI->isThumbFunction())
640 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
642 assert(AFI->isThumb2Function());
643 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
645 assert (Done && "Unable to resolve frame index!");
649 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
650 int64_t Offset) const {
651 const MCInstrDesc &Desc = MI->getDesc();
652 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
655 while (!MI->getOperand(i).isFI()) {
657 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
660 // AddrMode4 and AddrMode6 cannot handle any offset.
661 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
664 unsigned NumBits = 0;
666 bool isSigned = true;
668 case ARMII::AddrModeT2_i8:
669 case ARMII::AddrModeT2_i12:
670 // i8 supports only negative, and i12 supports only positive, so
671 // based on Offset sign, consider the appropriate instruction
680 case ARMII::AddrMode5:
685 case ARMII::AddrMode_i12:
686 case ARMII::AddrMode2:
689 case ARMII::AddrMode3:
692 case ARMII::AddrModeT1_s:
698 llvm_unreachable("Unsupported addressing mode!");
701 Offset += getFrameIndexInstrOffset(MI, i);
702 // Make sure the offset is encodable for instructions that scale the
704 if ((Offset & (Scale-1)) != 0)
707 if (isSigned && Offset < 0)
710 unsigned Mask = (1 << NumBits) - 1;
711 if ((unsigned)Offset <= Mask * Scale)
718 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
719 int SPAdj, RegScavenger *RS) const {
721 MachineInstr &MI = *II;
722 MachineBasicBlock &MBB = *MI.getParent();
723 MachineFunction &MF = *MBB.getParent();
724 const ARMFrameLowering *TFI =
725 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
726 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
727 assert(!AFI->isThumb1OnlyFunction() &&
728 "This eliminateFrameIndex does not support Thumb1!");
730 while (!MI.getOperand(i).isFI()) {
732 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
735 int FrameIndex = MI.getOperand(i).getIndex();
738 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
740 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
741 // call frame setup/destroy instructions have already been eliminated. That
742 // means the stack pointer cannot be used to access the emergency spill slot
743 // when !hasReservedCallFrame().
745 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
746 assert(TFI->hasReservedCallFrame(MF) &&
747 "Cannot use SP to access the emergency spill slot in "
748 "functions without a reserved call frame");
749 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
750 "Cannot use SP to access the emergency spill slot in "
751 "functions with variable sized frame objects");
755 // Special handling of dbg_value instructions.
756 if (MI.isDebugValue()) {
757 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
758 MI.getOperand(i+1).ChangeToImmediate(Offset);
762 // Modify MI as necessary to handle as much of 'Offset' as possible
764 if (!AFI->isThumbFunction())
765 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
767 assert(AFI->isThumb2Function());
768 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
773 // If we get here, the immediate doesn't fit into the instruction. We folded
774 // as much as possible above, handle the rest, providing a register that is
777 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
778 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
779 "This code isn't needed if offset already handled!");
781 unsigned ScratchReg = 0;
782 int PIdx = MI.findFirstPredOperandIdx();
783 ARMCC::CondCodes Pred = (PIdx == -1)
784 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
785 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
787 // Must be addrmode4/6.
788 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
790 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
791 if (!AFI->isThumbFunction())
792 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
793 Offset, Pred, PredReg, TII);
795 assert(AFI->isThumb2Function());
796 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
797 Offset, Pred, PredReg, TII);
799 // Update the original instruction to use the scratch register.
800 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);