1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
50 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
58 llvm_unreachable("Unknown ARM register!");
59 case R0: case D0: case Q0: return 0;
60 case R1: case D1: case Q1: return 1;
61 case R2: case D2: case Q2: return 2;
62 case R3: case D3: case Q3: return 3;
63 case R4: case D4: case Q4: return 4;
64 case R5: case D5: case Q5: return 5;
65 case R6: case D6: case Q6: return 6;
66 case R7: case D7: case Q7: return 7;
67 case R8: case D8: case Q8: return 8;
68 case R9: case D9: case Q9: return 9;
69 case R10: case D10: case Q10: return 10;
70 case R11: case D11: case Q11: return 11;
71 case R12: case D12: case Q12: return 12;
72 case SP: case D13: case Q13: return 13;
73 case LR: case D14: case Q14: return 14;
74 case PC: case D15: case Q15: return 15;
93 case S0: case S1: case S2: case S3:
94 case S4: case S5: case S6: case S7:
95 case S8: case S9: case S10: case S11:
96 case S12: case S13: case S14: case S15:
97 case S16: case S17: case S18: case S19:
98 case S20: case S21: case S22: case S23:
99 case S24: case S25: case S26: case S27:
100 case S28: case S29: case S30: case S31: {
104 default: return 0; // Avoid compile time warning.
142 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143 const ARMSubtarget &sti)
144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 static const unsigned CalleeSavedRegs[] = {
152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
160 static const unsigned DarwinCalleeSavedRegs[] = {
161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
164 ARM::R11, ARM::R10, ARM::R8,
166 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
173 const TargetRegisterClass* const *
174 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
175 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
176 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
185 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
186 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
188 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
195 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
196 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198 &ARM::GPRRegClass, &ARM::GPRRegClass,
200 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
205 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
206 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
207 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
208 &ARM::GPRRegClass, &ARM::GPRRegClass,
210 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
215 if (STI.isThumb1Only()) {
216 return STI.isTargetDarwin()
217 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219 return STI.isTargetDarwin()
220 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
223 BitVector ARMBaseRegisterInfo::
224 getReservedRegs(const MachineFunction &MF) const {
225 // FIXME: avoid re-calculating this everytime.
226 BitVector Reserved(getNumRegs());
227 Reserved.set(ARM::SP);
228 Reserved.set(ARM::PC);
229 if (STI.isTargetDarwin() || hasFP(MF))
230 Reserved.set(FramePtr);
231 // Some targets reserve R9.
232 if (STI.isR9Reserved())
233 Reserved.set(ARM::R9);
237 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238 unsigned Reg) const {
246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
250 return STI.isR9Reserved();
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258 const TargetRegisterClass *B,
259 unsigned SubIdx) const {
267 if (A->getSize() == 8) {
268 if (B == &ARM::SPR_8RegClass)
269 return &ARM::DPR_8RegClass;
270 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271 if (A == &ARM::DPR_8RegClass)
273 return &ARM::DPR_VFP2RegClass;
276 if (A->getSize() == 16) {
277 if (B == &ARM::SPR_8RegClass)
278 return &ARM::QPR_8RegClass;
279 return &ARM::QPR_VFP2RegClass;
282 if (A->getSize() == 32) {
283 if (B == &ARM::SPR_8RegClass)
284 return 0; // Do not allow coalescing!
285 return &ARM::QQPR_VFP2RegClass;
288 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
289 return 0; // Do not allow coalescing!
296 if (A->getSize() == 16) {
297 if (B == &ARM::DPR_VFP2RegClass)
298 return &ARM::QPR_VFP2RegClass;
299 if (B == &ARM::DPR_8RegClass)
300 return 0; // Do not allow coalescing!
304 if (A->getSize() == 32) {
305 if (B == &ARM::DPR_VFP2RegClass)
306 return &ARM::QQPR_VFP2RegClass;
307 if (B == &ARM::DPR_8RegClass)
308 return 0; // Do not allow coalescing!
312 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
313 if (B != &ARM::DPRRegClass)
314 return 0; // Do not allow coalescing!
321 // D sub-registers of QQQQ registers.
322 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
324 return 0; // Do not allow coalescing!
330 if (A->getSize() == 32) {
331 if (B == &ARM::QPR_VFP2RegClass)
332 return &ARM::QQPR_VFP2RegClass;
333 if (B == &ARM::QPR_8RegClass)
334 return 0; // Do not allow coalescing!
338 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
339 if (B == &ARM::QPRRegClass)
341 return 0; // Do not allow coalescing!
345 // Q sub-registers of QQQQ registers.
346 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
348 return 0; // Do not allow coalescing!
355 ARMBaseRegisterInfo::canCombinedSubRegIndex(const TargetRegisterClass *RC,
356 SmallVectorImpl<unsigned> &SubIndices,
357 unsigned &NewSubIdx) const {
359 unsigned Size = RC->getSize() * 8;
363 NewSubIdx = 0; // Whole register.
364 unsigned NumRegs = SubIndices.size();
366 // 8 D registers -> 1 QQQQ register.
367 return (Size == 512 &&
368 SubIndices[0] == ARM::dsub_0 &&
369 SubIndices[1] == ARM::dsub_1 &&
370 SubIndices[2] == ARM::dsub_2 &&
371 SubIndices[3] == ARM::dsub_3 &&
372 SubIndices[4] == ARM::dsub_4 &&
373 SubIndices[5] == ARM::dsub_5 &&
374 SubIndices[6] == ARM::dsub_6 &&
375 SubIndices[7] == ARM::dsub_7);
376 } else if (NumRegs == 4) {
377 if (SubIndices[0] == ARM::qsub_0) {
378 // 4 Q registers -> 1 QQQQ register.
379 return (Size == 512 &&
380 SubIndices[1] == ARM::qsub_1 &&
381 SubIndices[2] == ARM::qsub_2 &&
382 SubIndices[3] == ARM::qsub_3);
383 } else if (SubIndices[0] == ARM::dsub_0) {
384 // 4 D registers -> 1 QQ register.
386 SubIndices[1] == ARM::dsub_1 &&
387 SubIndices[2] == ARM::dsub_2 &&
388 SubIndices[3] == ARM::dsub_3) {
390 NewSubIdx = ARM::qqsub_0;
393 } else if (SubIndices[0] == ARM::dsub_4) {
394 // 4 D registers -> 1 QQ register (2nd).
396 SubIndices[1] == ARM::dsub_5 &&
397 SubIndices[2] == ARM::dsub_6 &&
398 SubIndices[3] == ARM::dsub_7) {
399 NewSubIdx = ARM::qqsub_1;
402 } else if (SubIndices[0] == ARM::ssub_0) {
403 // 4 S registers -> 1 Q register.
405 SubIndices[1] == ARM::ssub_1 &&
406 SubIndices[2] == ARM::ssub_2 &&
407 SubIndices[3] == ARM::ssub_3) {
409 NewSubIdx = ARM::qsub_0;
413 } else if (NumRegs == 2) {
414 if (SubIndices[0] == ARM::qsub_0) {
415 // 2 Q registers -> 1 QQ register.
416 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
418 NewSubIdx = ARM::qqsub_0;
421 } else if (SubIndices[0] == ARM::qsub_2) {
422 // 2 Q registers -> 1 QQ register (2nd).
423 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
424 NewSubIdx = ARM::qqsub_1;
427 } else if (SubIndices[0] == ARM::dsub_0) {
428 // 2 D registers -> 1 Q register.
429 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
431 NewSubIdx = ARM::qsub_0;
434 } else if (SubIndices[0] == ARM::dsub_2) {
435 // 2 D registers -> 1 Q register (2nd).
436 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
437 NewSubIdx = ARM::qsub_1;
440 } else if (SubIndices[0] == ARM::dsub_4) {
441 // 2 D registers -> 1 Q register (3rd).
442 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
443 NewSubIdx = ARM::qsub_2;
446 } else if (SubIndices[0] == ARM::dsub_6) {
447 // 2 D registers -> 1 Q register (3rd).
448 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
449 NewSubIdx = ARM::qsub_3;
452 } else if (SubIndices[0] == ARM::ssub_0) {
453 // 2 S registers -> 1 D register.
454 if (SubIndices[1] == ARM::ssub_1) {
456 NewSubIdx = ARM::dsub_0;
459 } else if (SubIndices[0] == ARM::ssub_2) {
460 // 2 S registers -> 1 D register (2nd).
461 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
462 NewSubIdx = ARM::dsub_1;
471 const TargetRegisterClass *
472 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
473 return ARM::GPRRegisterClass;
476 /// getAllocationOrder - Returns the register allocation order for a specified
477 /// register class in the form of a pair of TargetRegisterClass iterators.
478 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
479 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
480 unsigned HintType, unsigned HintReg,
481 const MachineFunction &MF) const {
482 // Alternative register allocation orders when favoring even / odd registers
483 // of register pairs.
485 // No FP, R9 is available.
486 static const unsigned GPREven1[] = {
487 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
488 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
491 static const unsigned GPROdd1[] = {
492 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
493 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
497 // FP is R7, R9 is available.
498 static const unsigned GPREven2[] = {
499 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
500 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
503 static const unsigned GPROdd2[] = {
504 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
505 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
509 // FP is R11, R9 is available.
510 static const unsigned GPREven3[] = {
511 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
512 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
515 static const unsigned GPROdd3[] = {
516 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
517 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
521 // No FP, R9 is not available.
522 static const unsigned GPREven4[] = {
523 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
524 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
527 static const unsigned GPROdd4[] = {
528 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
529 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
533 // FP is R7, R9 is not available.
534 static const unsigned GPREven5[] = {
535 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
536 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
539 static const unsigned GPROdd5[] = {
540 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
541 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
545 // FP is R11, R9 is not available.
546 static const unsigned GPREven6[] = {
547 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
548 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
550 static const unsigned GPROdd6[] = {
551 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
552 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
556 if (HintType == ARMRI::RegPairEven) {
557 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
558 // It's no longer possible to fulfill this hint. Return the default
560 return std::make_pair(RC->allocation_order_begin(MF),
561 RC->allocation_order_end(MF));
563 if (!STI.isTargetDarwin() && !hasFP(MF)) {
564 if (!STI.isR9Reserved())
565 return std::make_pair(GPREven1,
566 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
568 return std::make_pair(GPREven4,
569 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
570 } else if (FramePtr == ARM::R7) {
571 if (!STI.isR9Reserved())
572 return std::make_pair(GPREven2,
573 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
575 return std::make_pair(GPREven5,
576 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
577 } else { // FramePtr == ARM::R11
578 if (!STI.isR9Reserved())
579 return std::make_pair(GPREven3,
580 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
582 return std::make_pair(GPREven6,
583 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
585 } else if (HintType == ARMRI::RegPairOdd) {
586 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
587 // It's no longer possible to fulfill this hint. Return the default
589 return std::make_pair(RC->allocation_order_begin(MF),
590 RC->allocation_order_end(MF));
592 if (!STI.isTargetDarwin() && !hasFP(MF)) {
593 if (!STI.isR9Reserved())
594 return std::make_pair(GPROdd1,
595 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
597 return std::make_pair(GPROdd4,
598 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
599 } else if (FramePtr == ARM::R7) {
600 if (!STI.isR9Reserved())
601 return std::make_pair(GPROdd2,
602 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
604 return std::make_pair(GPROdd5,
605 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
606 } else { // FramePtr == ARM::R11
607 if (!STI.isR9Reserved())
608 return std::make_pair(GPROdd3,
609 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
611 return std::make_pair(GPROdd6,
612 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
615 return std::make_pair(RC->allocation_order_begin(MF),
616 RC->allocation_order_end(MF));
619 /// ResolveRegAllocHint - Resolves the specified register allocation hint
620 /// to a physical register. Returns the physical register if it is successful.
622 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
623 const MachineFunction &MF) const {
624 if (Reg == 0 || !isPhysicalRegister(Reg))
628 else if (Type == (unsigned)ARMRI::RegPairOdd)
630 return getRegisterPairOdd(Reg, MF);
631 else if (Type == (unsigned)ARMRI::RegPairEven)
633 return getRegisterPairEven(Reg, MF);
638 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
639 MachineFunction &MF) const {
640 MachineRegisterInfo *MRI = &MF.getRegInfo();
641 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
642 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
643 Hint.first == (unsigned)ARMRI::RegPairEven) &&
644 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
645 // If 'Reg' is one of the even / odd register pair and it's now changed
646 // (e.g. coalesced) into a different register. The other register of the
647 // pair allocation hint must be updated to reflect the relationship
649 unsigned OtherReg = Hint.second;
650 Hint = MRI->getRegAllocationHint(OtherReg);
651 if (Hint.second == Reg)
652 // Make sure the pair has not already divorced.
653 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
657 /// hasFP - Return true if the specified function should have a dedicated frame
658 /// pointer register. This is true if the function has variable sized allocas
659 /// or if frame pointer elimination is disabled.
661 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
662 const MachineFrameInfo *MFI = MF.getFrameInfo();
663 return ((DisableFramePointerElim(MF) && MFI->adjustsStack())||
664 needsStackRealignment(MF) ||
665 MFI->hasVarSizedObjects() ||
666 MFI->isFrameAddressTaken());
669 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
670 const MachineFrameInfo *MFI = MF.getFrameInfo();
671 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
672 return (RealignStack &&
673 !AFI->isThumb1OnlyFunction() &&
674 !MFI->hasVarSizedObjects());
677 bool ARMBaseRegisterInfo::
678 needsStackRealignment(const MachineFunction &MF) const {
679 const MachineFrameInfo *MFI = MF.getFrameInfo();
680 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
681 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
682 return (RealignStack &&
683 !AFI->isThumb1OnlyFunction() &&
684 (MFI->getMaxAlignment() > StackAlign) &&
685 !MFI->hasVarSizedObjects());
688 bool ARMBaseRegisterInfo::
689 cannotEliminateFrame(const MachineFunction &MF) const {
690 const MachineFrameInfo *MFI = MF.getFrameInfo();
691 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
693 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
694 || needsStackRealignment(MF);
697 /// estimateStackSize - Estimate and return the size of the frame.
698 static unsigned estimateStackSize(MachineFunction &MF) {
699 const MachineFrameInfo *FFI = MF.getFrameInfo();
701 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
702 int FixedOff = -FFI->getObjectOffset(i);
703 if (FixedOff > Offset) Offset = FixedOff;
705 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
706 if (FFI->isDeadObjectIndex(i))
708 Offset += FFI->getObjectSize(i);
709 unsigned Align = FFI->getObjectAlignment(i);
710 // Adjust to alignment boundary
711 Offset = (Offset+Align-1)/Align*Align;
713 return (unsigned)Offset;
716 /// estimateRSStackSizeLimit - Look at each instruction that references stack
717 /// frames and return the stack size limit beyond which some of these
718 /// instructions will require a scratch register during their expansion later.
720 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
721 unsigned Limit = (1 << 12) - 1;
722 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
723 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
725 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
726 if (!I->getOperand(i).isFI()) continue;
727 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
728 case ARMII::AddrMode3:
729 case ARMII::AddrModeT2_i8:
730 Limit = std::min(Limit, (1U << 8) - 1);
732 case ARMII::AddrMode5:
733 case ARMII::AddrModeT2_i8s4:
734 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
736 case ARMII::AddrModeT2_i12:
737 if (hasFP(MF)) Limit = std::min(Limit, (1U << 8) - 1);
739 case ARMII::AddrMode6:
740 // Addressing mode 6 (load/store) instructions can't encode an
741 // immediate offset for stack references.
746 break; // At most one FI per instruction
755 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
756 RegScavenger *RS) const {
757 // This tells PEI to spill the FP as if it is any other callee-save register
758 // to take advantage the eliminateFrameIndex machinery. This also ensures it
759 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
760 // to combine multiple loads / stores.
761 bool CanEliminateFrame = true;
762 bool CS1Spilled = false;
763 bool LRSpilled = false;
764 unsigned NumGPRSpills = 0;
765 SmallVector<unsigned, 4> UnspilledCS1GPRs;
766 SmallVector<unsigned, 4> UnspilledCS2GPRs;
767 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
769 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
771 // FIXME: It will be better just to find spare register here.
772 if (needsStackRealignment(MF) &&
773 AFI->isThumb2Function())
774 MF.getRegInfo().setPhysRegUsed(ARM::R4);
776 // Spill LR if Thumb1 function uses variable length argument lists.
777 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
778 MF.getRegInfo().setPhysRegUsed(ARM::LR);
780 // Don't spill FP if the frame can be eliminated. This is determined
781 // by scanning the callee-save registers to see if any is used.
782 const unsigned *CSRegs = getCalleeSavedRegs();
783 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
784 for (unsigned i = 0; CSRegs[i]; ++i) {
785 unsigned Reg = CSRegs[i];
786 bool Spilled = false;
787 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
788 AFI->setCSRegisterIsSpilled(Reg);
790 CanEliminateFrame = false;
792 // Check alias registers too.
793 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
794 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
796 CanEliminateFrame = false;
801 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
802 CSRegClasses[i] == ARM::tGPRRegisterClass) {
806 if (!STI.isTargetDarwin()) {
813 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
828 if (!STI.isTargetDarwin()) {
829 UnspilledCS1GPRs.push_back(Reg);
839 UnspilledCS1GPRs.push_back(Reg);
842 UnspilledCS2GPRs.push_back(Reg);
849 bool ForceLRSpill = false;
850 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
851 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
852 // Force LR to be spilled if the Thumb function size is > 2048. This enables
853 // use of BL to implement far jump. If it turns out that it's not needed
854 // then the branch fix up path will undo it.
855 if (FnSize >= (1 << 11)) {
856 CanEliminateFrame = false;
861 // If any of the stack slot references may be out of range of an immediate
862 // offset, make sure a register (or a spill slot) is available for the
863 // register scavenger. Note that if we're indexing off the frame pointer, the
864 // effective stack size is 4 bytes larger since the FP points to the stack
865 // slot of the previous FP.
866 bool BigStack = RS &&
867 estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
869 bool ExtraCSSpill = false;
870 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
871 AFI->setHasStackFrame(true);
873 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
874 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
875 if (!LRSpilled && CS1Spilled) {
876 MF.getRegInfo().setPhysRegUsed(ARM::LR);
877 AFI->setCSRegisterIsSpilled(ARM::LR);
879 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
880 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
881 ForceLRSpill = false;
885 // Darwin ABI requires FP to point to the stack slot that contains the
887 if (STI.isTargetDarwin() || hasFP(MF)) {
888 MF.getRegInfo().setPhysRegUsed(FramePtr);
892 // If stack and double are 8-byte aligned and we are spilling an odd number
893 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
894 // the integer and double callee save areas.
895 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
896 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
897 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
898 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
899 unsigned Reg = UnspilledCS1GPRs[i];
900 // Don't spill high register if the function is thumb1
901 if (!AFI->isThumb1OnlyFunction() ||
902 isARMLowRegister(Reg) || Reg == ARM::LR) {
903 MF.getRegInfo().setPhysRegUsed(Reg);
904 AFI->setCSRegisterIsSpilled(Reg);
905 if (!isReservedReg(MF, Reg))
910 } else if (!UnspilledCS2GPRs.empty() &&
911 !AFI->isThumb1OnlyFunction()) {
912 unsigned Reg = UnspilledCS2GPRs.front();
913 MF.getRegInfo().setPhysRegUsed(Reg);
914 AFI->setCSRegisterIsSpilled(Reg);
915 if (!isReservedReg(MF, Reg))
920 // Estimate if we might need to scavenge a register at some point in order
921 // to materialize a stack offset. If so, either spill one additional
922 // callee-saved register or reserve a special spill slot to facilitate
923 // register scavenging. Thumb1 needs a spill slot for stack pointer
924 // adjustments also, even when the frame itself is small.
925 if (BigStack && !ExtraCSSpill) {
926 // If any non-reserved CS register isn't spilled, just spill one or two
927 // extra. That should take care of it!
928 unsigned NumExtras = TargetAlign / 4;
929 SmallVector<unsigned, 2> Extras;
930 while (NumExtras && !UnspilledCS1GPRs.empty()) {
931 unsigned Reg = UnspilledCS1GPRs.back();
932 UnspilledCS1GPRs.pop_back();
933 if (!isReservedReg(MF, Reg) &&
934 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
936 Extras.push_back(Reg);
940 // For non-Thumb1 functions, also check for hi-reg CS registers
941 if (!AFI->isThumb1OnlyFunction()) {
942 while (NumExtras && !UnspilledCS2GPRs.empty()) {
943 unsigned Reg = UnspilledCS2GPRs.back();
944 UnspilledCS2GPRs.pop_back();
945 if (!isReservedReg(MF, Reg)) {
946 Extras.push_back(Reg);
951 if (Extras.size() && NumExtras == 0) {
952 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
953 MF.getRegInfo().setPhysRegUsed(Extras[i]);
954 AFI->setCSRegisterIsSpilled(Extras[i]);
956 } else if (!AFI->isThumb1OnlyFunction()) {
957 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
958 // closest to SP or frame pointer.
959 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
960 MachineFrameInfo *MFI = MF.getFrameInfo();
961 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
969 MF.getRegInfo().setPhysRegUsed(ARM::LR);
970 AFI->setCSRegisterIsSpilled(ARM::LR);
971 AFI->setLRIsSpilledForFarJump(true);
975 unsigned ARMBaseRegisterInfo::getRARegister() const {
980 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
981 if (STI.isTargetDarwin() || hasFP(MF))
987 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
988 unsigned &FrameReg) const {
989 const MachineFrameInfo *MFI = MF.getFrameInfo();
990 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
991 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
992 bool isFixed = MFI->isFixedObjectIndex(FI);
995 if (AFI->isGPRCalleeSavedArea1Frame(FI))
996 Offset -= AFI->getGPRCalleeSavedArea1Offset();
997 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
998 Offset -= AFI->getGPRCalleeSavedArea2Offset();
999 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1000 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1001 else if (needsStackRealignment(MF)) {
1002 // When dynamically realigning the stack, use the frame pointer for
1003 // parameters, and the stack pointer for locals.
1004 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1006 FrameReg = getFrameRegister(MF);
1007 Offset -= AFI->getFramePtrSpillOffset();
1009 } else if (hasFP(MF) && AFI->hasStackFrame()) {
1010 if (isFixed || MFI->hasVarSizedObjects()) {
1011 // Use frame pointer to reference fixed objects unless this is a
1012 // frameless function.
1013 FrameReg = getFrameRegister(MF);
1014 Offset -= AFI->getFramePtrSpillOffset();
1015 } else if (AFI->isThumb2Function()) {
1016 // In Thumb2 mode, the negative offset is very limited.
1017 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1018 if (FPOffset >= -255 && FPOffset < 0) {
1019 FrameReg = getFrameRegister(MF);
1029 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1032 return getFrameIndexReference(MF, FI, FrameReg);
1035 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1036 llvm_unreachable("What is the exception register");
1040 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1041 llvm_unreachable("What is the exception handler register");
1045 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1046 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1049 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1050 const MachineFunction &MF) const {
1053 // Return 0 if either register of the pair is a special register.
1062 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
1064 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1066 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1138 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1139 const MachineFunction &MF) const {
1142 // Return 0 if either register of the pair is a special register.
1151 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1153 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1155 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1227 /// emitLoadConstPool - Emits a load from constpool to materialize the
1228 /// specified immediate.
1229 void ARMBaseRegisterInfo::
1230 emitLoadConstPool(MachineBasicBlock &MBB,
1231 MachineBasicBlock::iterator &MBBI,
1233 unsigned DestReg, unsigned SubIdx, int Val,
1234 ARMCC::CondCodes Pred,
1235 unsigned PredReg) const {
1236 MachineFunction &MF = *MBB.getParent();
1237 MachineConstantPool *ConstantPool = MF.getConstantPool();
1239 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1240 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1242 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1243 .addReg(DestReg, getDefRegState(true), SubIdx)
1244 .addConstantPoolIndex(Idx)
1245 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1248 bool ARMBaseRegisterInfo::
1249 requiresRegisterScavenging(const MachineFunction &MF) const {
1253 bool ARMBaseRegisterInfo::
1254 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1258 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1259 // not required, we reserve argument space for call sites in the function
1260 // immediately on entry to the current function. This eliminates the need for
1261 // add/sub sp brackets around call sites. Returns true if the call frame is
1262 // included as part of the stack frame.
1263 bool ARMBaseRegisterInfo::
1264 hasReservedCallFrame(MachineFunction &MF) const {
1265 const MachineFrameInfo *FFI = MF.getFrameInfo();
1266 unsigned CFSize = FFI->getMaxCallFrameSize();
1267 // It's not always a good idea to include the call frame as part of the
1268 // stack frame. ARM (especially Thumb) has small immediate offset to
1269 // address the stack frame. So a large call frame can cause poor codegen
1270 // and may even makes it impossible to scavenge a register.
1271 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1274 return !MF.getFrameInfo()->hasVarSizedObjects();
1277 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1278 // call frame pseudos can be simplified. Unlike most targets, having a FP
1279 // is not sufficient here since we still may reference some objects via SP
1280 // even when FP is available in Thumb2 mode.
1281 bool ARMBaseRegisterInfo::
1282 canSimplifyCallFramePseudos(MachineFunction &MF) const {
1283 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1287 emitSPUpdate(bool isARM,
1288 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1289 DebugLoc dl, const ARMBaseInstrInfo &TII,
1291 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1293 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1294 Pred, PredReg, TII);
1296 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1297 Pred, PredReg, TII);
1301 void ARMBaseRegisterInfo::
1302 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1303 MachineBasicBlock::iterator I) const {
1304 if (!hasReservedCallFrame(MF)) {
1305 // If we have alloca, convert as follows:
1306 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1307 // ADJCALLSTACKUP -> add, sp, sp, amount
1308 MachineInstr *Old = I;
1309 DebugLoc dl = Old->getDebugLoc();
1310 unsigned Amount = Old->getOperand(0).getImm();
1312 // We need to keep the stack aligned properly. To do this, we round the
1313 // amount of space needed for the outgoing arguments up to the next
1314 // alignment boundary.
1315 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1316 Amount = (Amount+Align-1)/Align*Align;
1318 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1319 assert(!AFI->isThumb1OnlyFunction() &&
1320 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1321 bool isARM = !AFI->isThumbFunction();
1323 // Replace the pseudo instruction with a new instruction...
1324 unsigned Opc = Old->getOpcode();
1325 int PIdx = Old->findFirstPredOperandIdx();
1326 ARMCC::CondCodes Pred = (PIdx == -1)
1327 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1328 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1329 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1330 unsigned PredReg = Old->getOperand(2).getReg();
1331 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1333 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1334 unsigned PredReg = Old->getOperand(3).getReg();
1335 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1336 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1344 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1345 int SPAdj, FrameIndexValue *Value,
1346 RegScavenger *RS) const {
1348 MachineInstr &MI = *II;
1349 MachineBasicBlock &MBB = *MI.getParent();
1350 MachineFunction &MF = *MBB.getParent();
1351 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1352 assert(!AFI->isThumb1OnlyFunction() &&
1353 "This eliminateFrameIndex does not support Thumb1!");
1355 while (!MI.getOperand(i).isFI()) {
1357 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1360 int FrameIndex = MI.getOperand(i).getIndex();
1363 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1364 if (FrameReg != ARM::SP)
1368 // Special handling of dbg_value instructions.
1369 if (MI.isDebugValue()) {
1370 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1371 MI.getOperand(i+1).ChangeToImmediate(Offset);
1375 // Modify MI as necessary to handle as much of 'Offset' as possible
1377 if (!AFI->isThumbFunction())
1378 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1380 assert(AFI->isThumb2Function());
1381 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1386 // If we get here, the immediate doesn't fit into the instruction. We folded
1387 // as much as possible above, handle the rest, providing a register that is
1390 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1391 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1392 "This code isn't needed if offset already handled!");
1394 unsigned ScratchReg = 0;
1395 int PIdx = MI.findFirstPredOperandIdx();
1396 ARMCC::CondCodes Pred = (PIdx == -1)
1397 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1398 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1400 // Must be addrmode4/6.
1401 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1403 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1405 Value->first = FrameReg; // use the frame register as a kind indicator
1406 Value->second = Offset;
1408 if (!AFI->isThumbFunction())
1409 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1410 Offset, Pred, PredReg, TII);
1412 assert(AFI->isThumb2Function());
1413 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1414 Offset, Pred, PredReg, TII);
1416 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1417 if (!ReuseFrameIndexVals)
1423 /// Move iterator past the next bunch of callee save load / store ops for
1424 /// the particular spill area (1: integer area 1, 2: integer area 2,
1425 /// 3: fp area, 0: don't care).
1426 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1427 MachineBasicBlock::iterator &MBBI,
1428 int Opc1, int Opc2, unsigned Area,
1429 const ARMSubtarget &STI) {
1430 while (MBBI != MBB.end() &&
1431 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1432 MBBI->getOperand(1).isFI()) {
1435 unsigned Category = 0;
1436 switch (MBBI->getOperand(0).getReg()) {
1437 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1441 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1442 Category = STI.isTargetDarwin() ? 2 : 1;
1444 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1445 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1452 if (Done || Category != Area)
1460 void ARMBaseRegisterInfo::
1461 emitPrologue(MachineFunction &MF) const {
1462 MachineBasicBlock &MBB = MF.front();
1463 MachineBasicBlock::iterator MBBI = MBB.begin();
1464 MachineFrameInfo *MFI = MF.getFrameInfo();
1465 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1466 assert(!AFI->isThumb1OnlyFunction() &&
1467 "This emitPrologue does not support Thumb1!");
1468 bool isARM = !AFI->isThumbFunction();
1469 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1470 unsigned NumBytes = MFI->getStackSize();
1471 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1472 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1474 // Determine the sizes of each callee-save spill areas and record which frame
1475 // belongs to which callee-save spill areas.
1476 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1477 int FramePtrSpillFI = 0;
1479 // Allocate the vararg register save area. This is not counted in NumBytes.
1481 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1483 if (!AFI->hasStackFrame()) {
1485 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1489 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1490 unsigned Reg = CSI[i].getReg();
1491 int FI = CSI[i].getFrameIdx();
1498 if (Reg == FramePtr)
1499 FramePtrSpillFI = FI;
1500 AFI->addGPRCalleeSavedArea1Frame(FI);
1507 if (Reg == FramePtr)
1508 FramePtrSpillFI = FI;
1509 if (STI.isTargetDarwin()) {
1510 AFI->addGPRCalleeSavedArea2Frame(FI);
1513 AFI->addGPRCalleeSavedArea1Frame(FI);
1518 AFI->addDPRCalleeSavedAreaFrame(FI);
1523 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1524 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1525 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1527 // Set FP to point to the stack slot that contains the previous FP.
1528 // For Darwin, FP is R7, which has now been stored in spill area 1.
1529 // Otherwise, if this is not Darwin, all the callee-saved registers go
1530 // into spill area 1, including the FP in R11. In either case, it is
1531 // now safe to emit this assignment.
1532 if (STI.isTargetDarwin() || hasFP(MF)) {
1533 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1534 MachineInstrBuilder MIB =
1535 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1536 .addFrameIndex(FramePtrSpillFI).addImm(0);
1537 AddDefaultCC(AddDefaultPred(MIB));
1540 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1541 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1543 // Build the new SUBri to adjust SP for FP callee-save spill area.
1544 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1545 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1547 // Determine starting offsets of spill areas.
1548 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1549 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1550 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1551 if (STI.isTargetDarwin() || hasFP(MF))
1552 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1554 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1555 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1556 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1558 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1559 NumBytes = DPRCSOffset;
1561 // Adjust SP after all the callee-save spills.
1562 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1565 if (STI.isTargetELF() && hasFP(MF)) {
1566 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1567 AFI->getFramePtrSpillOffset());
1570 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1571 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1572 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1574 // If we need dynamic stack realignment, do it here.
1575 if (needsStackRealignment(MF)) {
1576 unsigned MaxAlign = MFI->getMaxAlignment();
1577 assert (!AFI->isThumb1OnlyFunction());
1578 if (!AFI->isThumbFunction()) {
1579 // Emit bic sp, sp, MaxAlign
1580 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1581 TII.get(ARM::BICri), ARM::SP)
1582 .addReg(ARM::SP, RegState::Kill)
1583 .addImm(MaxAlign-1)));
1585 // We cannot use sp as source/dest register here, thus we're emitting the
1586 // following sequence:
1588 // bic r4, r4, MaxAlign
1590 // FIXME: It will be better just to find spare register here.
1591 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1592 .addReg(ARM::SP, RegState::Kill);
1593 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1594 TII.get(ARM::t2BICri), ARM::R4)
1595 .addReg(ARM::R4, RegState::Kill)
1596 .addImm(MaxAlign-1)));
1597 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1598 .addReg(ARM::R4, RegState::Kill);
1603 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1604 for (unsigned i = 0; CSRegs[i]; ++i)
1605 if (Reg == CSRegs[i])
1610 static bool isCSRestore(MachineInstr *MI,
1611 const ARMBaseInstrInfo &TII,
1612 const unsigned *CSRegs) {
1613 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1614 MI->getOpcode() == (int)ARM::LDR ||
1615 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1616 MI->getOperand(1).isFI() &&
1617 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1620 void ARMBaseRegisterInfo::
1621 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1622 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1623 assert(MBBI->getDesc().isReturn() &&
1624 "Can only insert epilog into returning blocks");
1625 DebugLoc dl = MBBI->getDebugLoc();
1626 MachineFrameInfo *MFI = MF.getFrameInfo();
1627 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1628 assert(!AFI->isThumb1OnlyFunction() &&
1629 "This emitEpilogue does not support Thumb1!");
1630 bool isARM = !AFI->isThumbFunction();
1632 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1633 int NumBytes = (int)MFI->getStackSize();
1635 if (!AFI->hasStackFrame()) {
1637 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1639 // Unwind MBBI to point to first LDR / VLDRD.
1640 const unsigned *CSRegs = getCalleeSavedRegs();
1641 if (MBBI != MBB.begin()) {
1644 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1645 if (!isCSRestore(MBBI, TII, CSRegs))
1649 // Move SP to start of FP callee save spill area.
1650 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1651 AFI->getGPRCalleeSavedArea2Size() +
1652 AFI->getDPRCalleeSavedAreaSize());
1654 // Darwin ABI requires FP to point to the stack slot that contains the
1656 bool HasFP = hasFP(MF);
1657 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1658 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1659 // Reset SP based on frame pointer only if the stack frame extends beyond
1660 // frame pointer stack slot or target is ELF and the function has FP.
1662 AFI->getGPRCalleeSavedArea2Size() ||
1663 AFI->getDPRCalleeSavedAreaSize() ||
1664 AFI->getDPRCalleeSavedAreaOffset()) {
1667 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1670 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1675 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1677 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1679 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1683 } else if (NumBytes)
1684 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1686 // Move SP to start of integer callee save spill area 2.
1687 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1688 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1690 // Move SP to start of integer callee save spill area 1.
1691 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1692 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1694 // Move SP to SP upon entry to the function.
1695 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1696 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1700 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1703 #include "ARMGenRegisterInfo.inc"