1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
47 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
55 llvm_unreachable("Unknown ARM register!");
56 case R0: case D0: case Q0: return 0;
57 case R1: case D1: case Q1: return 1;
58 case R2: case D2: case Q2: return 2;
59 case R3: case D3: case Q3: return 3;
60 case R4: case D4: case Q4: return 4;
61 case R5: case D5: case Q5: return 5;
62 case R6: case D6: case Q6: return 6;
63 case R7: case D7: case Q7: return 7;
64 case R8: case D8: case Q8: return 8;
65 case R9: case D9: case Q9: return 9;
66 case R10: case D10: case Q10: return 10;
67 case R11: case D11: case Q11: return 11;
68 case R12: case D12: case Q12: return 12;
69 case SP: case D13: case Q13: return 13;
70 case LR: case D14: case Q14: return 14;
71 case PC: case D15: case Q15: return 15;
90 case S0: case S1: case S2: case S3:
91 case S4: case S5: case S6: case S7:
92 case S8: case S9: case S10: case S11:
93 case S12: case S13: case S14: case S15:
94 case S16: case S17: case S18: case S19:
95 case S20: case S21: case S22: case S23:
96 case S24: case S25: case S26: case S27:
97 case S28: case S29: case S30: case S31: {
101 default: return 0; // Avoid compile time warning.
139 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140 const ARMSubtarget &sti)
141 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
143 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148 static const unsigned CalleeSavedRegs[] = {
149 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
152 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
157 static const unsigned DarwinCalleeSavedRegs[] = {
158 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
160 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
161 ARM::R11, ARM::R10, ARM::R8,
163 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
167 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
170 const TargetRegisterClass* const *
171 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195 &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205 &ARM::GPRRegClass, &ARM::GPRRegClass,
207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212 if (STI.isThumb1Only()) {
213 return STI.isTargetDarwin()
214 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
216 return STI.isTargetDarwin()
217 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
220 BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
221 // FIXME: avoid re-calculating this everytime.
222 BitVector Reserved(getNumRegs());
223 Reserved.set(ARM::SP);
224 Reserved.set(ARM::PC);
225 if (STI.isTargetDarwin() || hasFP(MF))
226 Reserved.set(FramePtr);
227 // Some targets reserve R9.
228 if (STI.isR9Reserved())
229 Reserved.set(ARM::R9);
233 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
234 unsigned Reg) const {
242 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
246 return STI.isR9Reserved();
252 const TargetRegisterClass *
253 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
254 const TargetRegisterClass *B,
255 unsigned SubIdx) const {
263 if (A->getSize() == 8) {
264 if (B == &ARM::SPR_8RegClass)
265 return &ARM::DPR_8RegClass;
266 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
267 if (A == &ARM::DPR_8RegClass)
269 return &ARM::DPR_VFP2RegClass;
272 assert(A->getSize() == 16 && "Expecting a Q register class!");
273 if (B == &ARM::SPR_8RegClass)
274 return &ARM::QPR_8RegClass;
275 return &ARM::QPR_VFP2RegClass;
279 if (B == &ARM::DPR_VFP2RegClass)
280 return &ARM::QPR_VFP2RegClass;
281 if (B == &ARM::DPR_8RegClass)
282 return &ARM::QPR_8RegClass;
288 const TargetRegisterClass *
289 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
290 return ARM::GPRRegisterClass;
293 /// getAllocationOrder - Returns the register allocation order for a specified
294 /// register class in the form of a pair of TargetRegisterClass iterators.
295 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
296 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
297 unsigned HintType, unsigned HintReg,
298 const MachineFunction &MF) const {
299 // Alternative register allocation orders when favoring even / odd registers
300 // of register pairs.
302 // No FP, R9 is available.
303 static const unsigned GPREven1[] = {
304 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
305 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
308 static const unsigned GPROdd1[] = {
309 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
310 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
314 // FP is R7, R9 is available.
315 static const unsigned GPREven2[] = {
316 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
317 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
320 static const unsigned GPROdd2[] = {
321 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
322 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
326 // FP is R11, R9 is available.
327 static const unsigned GPREven3[] = {
328 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
329 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
332 static const unsigned GPROdd3[] = {
333 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
334 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
338 // No FP, R9 is not available.
339 static const unsigned GPREven4[] = {
340 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
341 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
344 static const unsigned GPROdd4[] = {
345 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
346 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
350 // FP is R7, R9 is not available.
351 static const unsigned GPREven5[] = {
352 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
353 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
356 static const unsigned GPROdd5[] = {
357 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
358 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
362 // FP is R11, R9 is not available.
363 static const unsigned GPREven6[] = {
364 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
365 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
367 static const unsigned GPROdd6[] = {
368 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
369 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
373 if (HintType == ARMRI::RegPairEven) {
374 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
375 // It's no longer possible to fulfill this hint. Return the default
377 return std::make_pair(RC->allocation_order_begin(MF),
378 RC->allocation_order_end(MF));
380 if (!STI.isTargetDarwin() && !hasFP(MF)) {
381 if (!STI.isR9Reserved())
382 return std::make_pair(GPREven1,
383 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
385 return std::make_pair(GPREven4,
386 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
387 } else if (FramePtr == ARM::R7) {
388 if (!STI.isR9Reserved())
389 return std::make_pair(GPREven2,
390 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
392 return std::make_pair(GPREven5,
393 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
394 } else { // FramePtr == ARM::R11
395 if (!STI.isR9Reserved())
396 return std::make_pair(GPREven3,
397 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
399 return std::make_pair(GPREven6,
400 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
402 } else if (HintType == ARMRI::RegPairOdd) {
403 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
404 // It's no longer possible to fulfill this hint. Return the default
406 return std::make_pair(RC->allocation_order_begin(MF),
407 RC->allocation_order_end(MF));
409 if (!STI.isTargetDarwin() && !hasFP(MF)) {
410 if (!STI.isR9Reserved())
411 return std::make_pair(GPROdd1,
412 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
414 return std::make_pair(GPROdd4,
415 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
416 } else if (FramePtr == ARM::R7) {
417 if (!STI.isR9Reserved())
418 return std::make_pair(GPROdd2,
419 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
421 return std::make_pair(GPROdd5,
422 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
423 } else { // FramePtr == ARM::R11
424 if (!STI.isR9Reserved())
425 return std::make_pair(GPROdd3,
426 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
428 return std::make_pair(GPROdd6,
429 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
432 return std::make_pair(RC->allocation_order_begin(MF),
433 RC->allocation_order_end(MF));
436 /// ResolveRegAllocHint - Resolves the specified register allocation hint
437 /// to a physical register. Returns the physical register if it is successful.
439 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
440 const MachineFunction &MF) const {
441 if (Reg == 0 || !isPhysicalRegister(Reg))
445 else if (Type == (unsigned)ARMRI::RegPairOdd)
447 return getRegisterPairOdd(Reg, MF);
448 else if (Type == (unsigned)ARMRI::RegPairEven)
450 return getRegisterPairEven(Reg, MF);
455 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
456 MachineFunction &MF) const {
457 MachineRegisterInfo *MRI = &MF.getRegInfo();
458 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
459 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
460 Hint.first == (unsigned)ARMRI::RegPairEven) &&
461 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
462 // If 'Reg' is one of the even / odd register pair and it's now changed
463 // (e.g. coalesced) into a different register. The other register of the
464 // pair allocation hint must be updated to reflect the relationship
466 unsigned OtherReg = Hint.second;
467 Hint = MRI->getRegAllocationHint(OtherReg);
468 if (Hint.second == Reg)
469 // Make sure the pair has not already divorced.
470 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
474 /// hasFP - Return true if the specified function should have a dedicated frame
475 /// pointer register. This is true if the function has variable sized allocas
476 /// or if frame pointer elimination is disabled.
478 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
479 const MachineFrameInfo *MFI = MF.getFrameInfo();
480 return (NoFramePointerElim ||
481 needsStackRealignment(MF) ||
482 MFI->hasVarSizedObjects() ||
483 MFI->isFrameAddressTaken());
486 bool ARMBaseRegisterInfo::
487 needsStackRealignment(const MachineFunction &MF) const {
488 const MachineFrameInfo *MFI = MF.getFrameInfo();
489 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
491 return (RealignStack &&
492 !AFI->isThumb1OnlyFunction() &&
493 (MFI->getMaxAlignment() > StackAlign) &&
494 !MFI->hasVarSizedObjects());
497 bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
498 const MachineFrameInfo *MFI = MF.getFrameInfo();
499 if (NoFramePointerElim && MFI->hasCalls())
501 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
502 || needsStackRealignment(MF);
505 /// estimateStackSize - Estimate and return the size of the frame.
506 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
507 const MachineFrameInfo *FFI = MF.getFrameInfo();
509 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
510 int FixedOff = -FFI->getObjectOffset(i);
511 if (FixedOff > Offset) Offset = FixedOff;
513 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
514 if (FFI->isDeadObjectIndex(i))
516 Offset += FFI->getObjectSize(i);
517 unsigned Align = FFI->getObjectAlignment(i);
518 // Adjust to alignment boundary
519 Offset = (Offset+Align-1)/Align*Align;
521 return (unsigned)Offset;
524 /// estimateRSStackSizeLimit - Look at each instruction that references stack
525 /// frames and return the stack size limit beyond which some of these
526 /// instructions will require a scratch register during their expansion later.
528 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
529 unsigned Limit = (1 << 12) - 1;
530 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
531 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
533 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
534 if (!I->getOperand(i).isFI()) continue;
536 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
537 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
538 if (AddrMode == ARMII::AddrMode3 ||
539 AddrMode == ARMII::AddrModeT2_i8)
542 if (AddrMode == ARMII::AddrMode5 ||
543 AddrMode == ARMII::AddrModeT2_i8s4)
544 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
546 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
547 // When the stack offset is negative, we will end up using
548 // the i8 instructions instead.
551 if (AddrMode == ARMII::AddrMode6)
553 break; // At most one FI per instruction
562 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
563 RegScavenger *RS) const {
564 // This tells PEI to spill the FP as if it is any other callee-save register
565 // to take advantage the eliminateFrameIndex machinery. This also ensures it
566 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
567 // to combine multiple loads / stores.
568 bool CanEliminateFrame = true;
569 bool CS1Spilled = false;
570 bool LRSpilled = false;
571 unsigned NumGPRSpills = 0;
572 SmallVector<unsigned, 4> UnspilledCS1GPRs;
573 SmallVector<unsigned, 4> UnspilledCS2GPRs;
574 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
577 // Calculate and set max stack object alignment early, so we can decide
578 // whether we will need stack realignment (and thus FP).
580 MachineFrameInfo *MFI = MF.getFrameInfo();
581 MFI->calculateMaxStackAlignment();
584 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
586 // FIXME: It will be better just to find spare register here.
587 if (needsStackRealignment(MF) &&
588 AFI->isThumb2Function())
589 MF.getRegInfo().setPhysRegUsed(ARM::R4);
591 // Don't spill FP if the frame can be eliminated. This is determined
592 // by scanning the callee-save registers to see if any is used.
593 const unsigned *CSRegs = getCalleeSavedRegs();
594 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
595 for (unsigned i = 0; CSRegs[i]; ++i) {
596 unsigned Reg = CSRegs[i];
597 bool Spilled = false;
598 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
599 AFI->setCSRegisterIsSpilled(Reg);
601 CanEliminateFrame = false;
603 // Check alias registers too.
604 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
605 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
607 CanEliminateFrame = false;
612 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
613 CSRegClasses[i] == ARM::tGPRRegisterClass) {
617 if (!STI.isTargetDarwin()) {
624 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
639 if (!STI.isTargetDarwin()) {
640 UnspilledCS1GPRs.push_back(Reg);
650 UnspilledCS1GPRs.push_back(Reg);
653 UnspilledCS2GPRs.push_back(Reg);
660 bool ForceLRSpill = false;
661 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
662 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
663 // Force LR to be spilled if the Thumb function size is > 2048. This enables
664 // use of BL to implement far jump. If it turns out that it's not needed
665 // then the branch fix up path will undo it.
666 if (FnSize >= (1 << 11)) {
667 CanEliminateFrame = false;
672 bool ExtraCSSpill = false;
673 if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
674 AFI->setHasStackFrame(true);
676 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
677 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
678 if (!LRSpilled && CS1Spilled) {
679 MF.getRegInfo().setPhysRegUsed(ARM::LR);
680 AFI->setCSRegisterIsSpilled(ARM::LR);
682 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
683 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
684 ForceLRSpill = false;
688 // Darwin ABI requires FP to point to the stack slot that contains the
690 if (STI.isTargetDarwin() || hasFP(MF)) {
691 MF.getRegInfo().setPhysRegUsed(FramePtr);
695 // If stack and double are 8-byte aligned and we are spilling an odd number
696 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
697 // the integer and double callee save areas.
698 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
699 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
700 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
701 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
702 unsigned Reg = UnspilledCS1GPRs[i];
703 // Don't spill high register if the function is thumb1
704 if (!AFI->isThumb1OnlyFunction() ||
705 isARMLowRegister(Reg) || Reg == ARM::LR) {
706 MF.getRegInfo().setPhysRegUsed(Reg);
707 AFI->setCSRegisterIsSpilled(Reg);
708 if (!isReservedReg(MF, Reg))
713 } else if (!UnspilledCS2GPRs.empty() &&
714 !AFI->isThumb1OnlyFunction()) {
715 unsigned Reg = UnspilledCS2GPRs.front();
716 MF.getRegInfo().setPhysRegUsed(Reg);
717 AFI->setCSRegisterIsSpilled(Reg);
718 if (!isReservedReg(MF, Reg))
723 // Estimate if we might need to scavenge a register at some point in order
724 // to materialize a stack offset. If so, either spill one additional
725 // callee-saved register or reserve a special spill slot to facilitate
726 // register scavenging. Thumb1 needs a spill slot for stack pointer
727 // adjustments also, even when the frame itself is small.
728 if (RS && !ExtraCSSpill) {
729 MachineFrameInfo *MFI = MF.getFrameInfo();
730 // If any of the stack slot references may be out of range of an
731 // immediate offset, make sure a register (or a spill slot) is
732 // available for the register scavenger. Note that if we're indexing
733 // off the frame pointer, the effective stack size is 4 bytes larger
734 // since the FP points to the stack slot of the previous FP.
735 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
736 >= estimateRSStackSizeLimit(MF)) {
737 // If any non-reserved CS register isn't spilled, just spill one or two
738 // extra. That should take care of it!
739 unsigned NumExtras = TargetAlign / 4;
740 SmallVector<unsigned, 2> Extras;
741 while (NumExtras && !UnspilledCS1GPRs.empty()) {
742 unsigned Reg = UnspilledCS1GPRs.back();
743 UnspilledCS1GPRs.pop_back();
744 if (!isReservedReg(MF, Reg)) {
745 Extras.push_back(Reg);
749 // For non-Thumb1 functions, also check for hi-reg CS registers
750 if (!AFI->isThumb1OnlyFunction()) {
751 while (NumExtras && !UnspilledCS2GPRs.empty()) {
752 unsigned Reg = UnspilledCS2GPRs.back();
753 UnspilledCS2GPRs.pop_back();
754 if (!isReservedReg(MF, Reg)) {
755 Extras.push_back(Reg);
760 if (Extras.size() && NumExtras == 0) {
761 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
762 MF.getRegInfo().setPhysRegUsed(Extras[i]);
763 AFI->setCSRegisterIsSpilled(Extras[i]);
765 } else if (!AFI->isThumb1OnlyFunction()) {
766 // note: Thumb1 functions spill to R12, not the stack.
767 // Reserve a slot closest to SP or frame pointer.
768 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
769 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
778 MF.getRegInfo().setPhysRegUsed(ARM::LR);
779 AFI->setCSRegisterIsSpilled(ARM::LR);
780 AFI->setLRIsSpilledForFarJump(true);
784 unsigned ARMBaseRegisterInfo::getRARegister() const {
789 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
790 if (STI.isTargetDarwin() || hasFP(MF))
796 ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI,
797 unsigned &FrameReg) const {
798 const MachineFrameInfo *MFI = MF.getFrameInfo();
799 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
800 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
801 bool isFixed = MFI->isFixedObjectIndex(FI);
804 if (AFI->isGPRCalleeSavedArea1Frame(FI))
805 Offset -= AFI->getGPRCalleeSavedArea1Offset();
806 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
807 Offset -= AFI->getGPRCalleeSavedArea2Offset();
808 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
809 Offset -= AFI->getDPRCalleeSavedAreaOffset();
810 else if (needsStackRealignment(MF)) {
811 // When dynamically realigning the stack, use the frame pointer for
812 // parameters, and the stack pointer for locals.
813 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
815 FrameReg = getFrameRegister(MF);
816 Offset -= AFI->getFramePtrSpillOffset();
818 } else if (hasFP(MF) && AFI->hasStackFrame()) {
819 if (isFixed || MFI->hasVarSizedObjects()) {
820 // Use frame pointer to reference fixed objects unless this is a
821 // frameless function.
822 FrameReg = getFrameRegister(MF);
823 Offset -= AFI->getFramePtrSpillOffset();
824 } else if (AFI->isThumb2Function()) {
825 // In Thumb2 mode, the negative offset is very limited.
826 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
827 if (FPOffset >= -255 && FPOffset < 0) {
828 FrameReg = getFrameRegister(MF);
838 ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
840 return getFrameIndexReference(MF, FI, FrameReg);
843 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
844 llvm_unreachable("What is the exception register");
848 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
849 llvm_unreachable("What is the exception handler register");
853 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
854 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
857 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
858 const MachineFunction &MF) const {
861 // Return 0 if either register of the pair is a special register.
870 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
872 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
874 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
946 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
947 const MachineFunction &MF) const {
950 // Return 0 if either register of the pair is a special register.
959 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
961 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
963 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1035 /// emitLoadConstPool - Emits a load from constpool to materialize the
1036 /// specified immediate.
1037 void ARMBaseRegisterInfo::
1038 emitLoadConstPool(MachineBasicBlock &MBB,
1039 MachineBasicBlock::iterator &MBBI,
1041 unsigned DestReg, unsigned SubIdx, int Val,
1042 ARMCC::CondCodes Pred,
1043 unsigned PredReg) const {
1044 MachineFunction &MF = *MBB.getParent();
1045 MachineConstantPool *ConstantPool = MF.getConstantPool();
1047 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1048 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1050 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1051 .addReg(DestReg, getDefRegState(true), SubIdx)
1052 .addConstantPoolIndex(Idx)
1053 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1056 bool ARMBaseRegisterInfo::
1057 requiresRegisterScavenging(const MachineFunction &MF) const {
1061 bool ARMBaseRegisterInfo::
1062 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1066 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1067 // not required, we reserve argument space for call sites in the function
1068 // immediately on entry to the current function. This eliminates the need for
1069 // add/sub sp brackets around call sites. Returns true if the call frame is
1070 // included as part of the stack frame.
1071 bool ARMBaseRegisterInfo::
1072 hasReservedCallFrame(MachineFunction &MF) const {
1073 const MachineFrameInfo *FFI = MF.getFrameInfo();
1074 unsigned CFSize = FFI->getMaxCallFrameSize();
1075 // It's not always a good idea to include the call frame as part of the
1076 // stack frame. ARM (especially Thumb) has small immediate offset to
1077 // address the stack frame. So a large call frame can cause poor codegen
1078 // and may even makes it impossible to scavenge a register.
1079 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1082 return !MF.getFrameInfo()->hasVarSizedObjects();
1086 emitSPUpdate(bool isARM,
1087 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1088 DebugLoc dl, const ARMBaseInstrInfo &TII,
1090 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1092 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1093 Pred, PredReg, TII);
1095 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1096 Pred, PredReg, TII);
1100 void ARMBaseRegisterInfo::
1101 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1102 MachineBasicBlock::iterator I) const {
1103 if (!hasReservedCallFrame(MF)) {
1104 // If we have alloca, convert as follows:
1105 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1106 // ADJCALLSTACKUP -> add, sp, sp, amount
1107 MachineInstr *Old = I;
1108 DebugLoc dl = Old->getDebugLoc();
1109 unsigned Amount = Old->getOperand(0).getImm();
1111 // We need to keep the stack aligned properly. To do this, we round the
1112 // amount of space needed for the outgoing arguments up to the next
1113 // alignment boundary.
1114 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1115 Amount = (Amount+Align-1)/Align*Align;
1117 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1118 assert(!AFI->isThumb1OnlyFunction() &&
1119 "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1120 bool isARM = !AFI->isThumbFunction();
1122 // Replace the pseudo instruction with a new instruction...
1123 unsigned Opc = Old->getOpcode();
1124 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1125 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1126 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1127 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1128 unsigned PredReg = Old->getOperand(2).getReg();
1129 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1131 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1132 unsigned PredReg = Old->getOperand(3).getReg();
1133 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1134 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1142 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1143 int SPAdj, int *Value,
1144 RegScavenger *RS) const {
1146 MachineInstr &MI = *II;
1147 MachineBasicBlock &MBB = *MI.getParent();
1148 MachineFunction &MF = *MBB.getParent();
1149 const MachineFrameInfo *MFI = MF.getFrameInfo();
1150 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1151 assert(!AFI->isThumb1OnlyFunction() &&
1152 "This eliminateFrameIndex does not support Thumb1!");
1154 while (!MI.getOperand(i).isFI()) {
1156 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1159 int FrameIndex = MI.getOperand(i).getIndex();
1160 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1163 Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1164 if (FrameReg != ARM::SP)
1167 // Modify MI as necessary to handle as much of 'Offset' as possible
1169 if (!AFI->isThumbFunction())
1170 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1172 assert(AFI->isThumb2Function());
1173 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1178 // If we get here, the immediate doesn't fit into the instruction. We folded
1179 // as much as possible above, handle the rest, providing a register that is
1182 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1183 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1184 "This code isn't needed if offset already handled!");
1186 unsigned ScratchReg = 0;
1187 int PIdx = MI.findFirstPredOperandIdx();
1188 ARMCC::CondCodes Pred = (PIdx == -1)
1189 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1190 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1192 // Must be addrmode4/6.
1193 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1195 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1196 if (Value) *Value = Offset;
1197 if (!AFI->isThumbFunction())
1198 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1199 Offset, Pred, PredReg, TII);
1201 assert(AFI->isThumb2Function());
1202 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1203 Offset, Pred, PredReg, TII);
1205 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1206 if (!ReuseFrameIndexVals)
1212 /// Move iterator past the next bunch of callee save load / store ops for
1213 /// the particular spill area (1: integer area 1, 2: integer area 2,
1214 /// 3: fp area, 0: don't care).
1215 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1216 MachineBasicBlock::iterator &MBBI,
1217 int Opc1, int Opc2, unsigned Area,
1218 const ARMSubtarget &STI) {
1219 while (MBBI != MBB.end() &&
1220 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1221 MBBI->getOperand(1).isFI()) {
1224 unsigned Category = 0;
1225 switch (MBBI->getOperand(0).getReg()) {
1226 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1230 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1231 Category = STI.isTargetDarwin() ? 2 : 1;
1233 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1234 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1241 if (Done || Category != Area)
1249 void ARMBaseRegisterInfo::
1250 emitPrologue(MachineFunction &MF) const {
1251 MachineBasicBlock &MBB = MF.front();
1252 MachineBasicBlock::iterator MBBI = MBB.begin();
1253 MachineFrameInfo *MFI = MF.getFrameInfo();
1254 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1255 assert(!AFI->isThumb1OnlyFunction() &&
1256 "This emitPrologue does not suppor Thumb1!");
1257 bool isARM = !AFI->isThumbFunction();
1258 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1259 unsigned NumBytes = MFI->getStackSize();
1260 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1261 DebugLoc dl = (MBBI != MBB.end() ?
1262 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1264 // Determine the sizes of each callee-save spill areas and record which frame
1265 // belongs to which callee-save spill areas.
1266 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1267 int FramePtrSpillFI = 0;
1269 // Allocate the vararg register save area. This is not counted in NumBytes.
1271 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1273 if (!AFI->hasStackFrame()) {
1275 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1279 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1280 unsigned Reg = CSI[i].getReg();
1281 int FI = CSI[i].getFrameIdx();
1288 if (Reg == FramePtr)
1289 FramePtrSpillFI = FI;
1290 AFI->addGPRCalleeSavedArea1Frame(FI);
1297 if (Reg == FramePtr)
1298 FramePtrSpillFI = FI;
1299 if (STI.isTargetDarwin()) {
1300 AFI->addGPRCalleeSavedArea2Frame(FI);
1303 AFI->addGPRCalleeSavedArea1Frame(FI);
1308 AFI->addDPRCalleeSavedAreaFrame(FI);
1313 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1314 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1315 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1317 // Set FP to point to the stack slot that contains the previous FP.
1318 // For Darwin, FP is R7, which has now been stored in spill area 1.
1319 // Otherwise, if this is not Darwin, all the callee-saved registers go
1320 // into spill area 1, including the FP in R11. In either case, it is
1321 // now safe to emit this assignment.
1322 if (STI.isTargetDarwin() || hasFP(MF)) {
1323 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1324 MachineInstrBuilder MIB =
1325 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1326 .addFrameIndex(FramePtrSpillFI).addImm(0);
1327 AddDefaultCC(AddDefaultPred(MIB));
1330 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1331 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1333 // Build the new SUBri to adjust SP for FP callee-save spill area.
1334 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1335 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1337 // Determine starting offsets of spill areas.
1338 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1339 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1340 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1341 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1342 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1343 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1344 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1346 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1347 NumBytes = DPRCSOffset;
1349 // Adjust SP after all the callee-save spills.
1350 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1353 if (STI.isTargetELF() && hasFP(MF)) {
1354 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1355 AFI->getFramePtrSpillOffset());
1358 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1359 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1360 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1362 // If we need dynamic stack realignment, do it here.
1363 if (needsStackRealignment(MF)) {
1364 unsigned MaxAlign = MFI->getMaxAlignment();
1365 assert (!AFI->isThumb1OnlyFunction());
1366 if (!AFI->isThumbFunction()) {
1367 // Emit bic sp, sp, MaxAlign
1368 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1369 TII.get(ARM::BICri), ARM::SP)
1370 .addReg(ARM::SP, RegState::Kill)
1371 .addImm(MaxAlign-1)));
1373 // We cannot use sp as source/dest register here, thus we're emitting the
1374 // following sequence:
1376 // bic r4, r4, MaxAlign
1378 // FIXME: It will be better just to find spare register here.
1379 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1380 .addReg(ARM::SP, RegState::Kill);
1381 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1382 TII.get(ARM::t2BICri), ARM::R4)
1383 .addReg(ARM::R4, RegState::Kill)
1384 .addImm(MaxAlign-1)));
1385 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1386 .addReg(ARM::R4, RegState::Kill);
1391 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1392 for (unsigned i = 0; CSRegs[i]; ++i)
1393 if (Reg == CSRegs[i])
1398 static bool isCSRestore(MachineInstr *MI,
1399 const ARMBaseInstrInfo &TII,
1400 const unsigned *CSRegs) {
1401 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1402 MI->getOpcode() == (int)ARM::LDR ||
1403 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1404 MI->getOperand(1).isFI() &&
1405 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1408 void ARMBaseRegisterInfo::
1409 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1410 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1411 assert(MBBI->getDesc().isReturn() &&
1412 "Can only insert epilog into returning blocks");
1413 DebugLoc dl = MBBI->getDebugLoc();
1414 MachineFrameInfo *MFI = MF.getFrameInfo();
1415 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1416 assert(!AFI->isThumb1OnlyFunction() &&
1417 "This emitEpilogue does not suppor Thumb1!");
1418 bool isARM = !AFI->isThumbFunction();
1420 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1421 int NumBytes = (int)MFI->getStackSize();
1423 if (!AFI->hasStackFrame()) {
1425 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1427 // Unwind MBBI to point to first LDR / VLDRD.
1428 const unsigned *CSRegs = getCalleeSavedRegs();
1429 if (MBBI != MBB.begin()) {
1432 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1433 if (!isCSRestore(MBBI, TII, CSRegs))
1437 // Move SP to start of FP callee save spill area.
1438 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1439 AFI->getGPRCalleeSavedArea2Size() +
1440 AFI->getDPRCalleeSavedAreaSize());
1442 // Darwin ABI requires FP to point to the stack slot that contains the
1444 bool HasFP = hasFP(MF);
1445 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1446 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1447 // Reset SP based on frame pointer only if the stack frame extends beyond
1448 // frame pointer stack slot or target is ELF and the function has FP.
1450 AFI->getGPRCalleeSavedArea2Size() ||
1451 AFI->getDPRCalleeSavedAreaSize() ||
1452 AFI->getDPRCalleeSavedAreaOffset()) {
1455 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1458 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1463 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1465 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1467 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1471 } else if (NumBytes)
1472 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1474 // Move SP to start of integer callee save spill area 2.
1475 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1476 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1478 // Move SP to start of integer callee save spill area 1.
1479 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1480 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1482 // Move SP to SP upon entry to the function.
1483 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1484 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1488 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1491 #include "ARMGenRegisterInfo.inc"