1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
46 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti),
48 FramePtr((STI.isTargetMachO() || STI.isThumb()) ? ARM::R7 : ARM::R11),
53 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
54 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI())
58 if (!MF) return RegList;
60 const Function *F = MF->getFunction();
61 if (F->getCallingConv() == CallingConv::GHC) {
62 // GHC set of callee saved regs is empty as all those regs are
63 // used for passing STG regs around
64 return CSR_NoRegs_SaveList;
65 } else if (F->hasFnAttribute("interrupt")) {
67 // M-class CPUs have hardware which saves the registers needed to allow a
68 // function conforming to the AAPCS to function as a handler.
69 return CSR_AAPCS_SaveList;
70 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
71 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
72 // need to be saved to restore user-mode state.
73 return CSR_FIQ_SaveList;
75 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
76 // exception handling.
77 return CSR_GenericInt_SaveList;
85 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
86 if (CC == CallingConv::GHC)
87 // This is academic becase all GHC calls are (supposed to be) tail calls
88 return CSR_NoRegs_RegMask;
89 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
90 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
94 ARMBaseRegisterInfo::getNoPreservedMask() const {
95 return CSR_NoRegs_RegMask;
99 ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const {
100 // This should return a register mask that is the same as that returned by
101 // getCallPreservedMask but that additionally preserves the register used for
102 // the first i32 argument (which must also be the register used to return a
103 // single i32 return value)
105 // In case that the calling convention does not use the same register for
106 // both or otherwise does not want to enable this optimization, the function
107 // should return NULL
108 if (CC == CallingConv::GHC)
109 // This is academic becase all GHC calls are (supposed to be) tail calls
111 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
112 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask;
115 BitVector ARMBaseRegisterInfo::
116 getReservedRegs(const MachineFunction &MF) const {
117 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
119 // FIXME: avoid re-calculating this every time.
120 BitVector Reserved(getNumRegs());
121 Reserved.set(ARM::SP);
122 Reserved.set(ARM::PC);
123 Reserved.set(ARM::FPSCR);
124 Reserved.set(ARM::APSR_NZCV);
126 Reserved.set(FramePtr);
127 if (hasBasePointer(MF))
128 Reserved.set(BasePtr);
129 // Some targets reserve R9.
130 if (STI.isR9Reserved())
131 Reserved.set(ARM::R9);
132 // Reserve D16-D31 if the subtarget doesn't support them.
133 if (!STI.hasVFP3() || STI.hasD16()) {
134 assert(ARM::D31 == ARM::D16 + 15);
135 for (unsigned i = 0; i != 16; ++i)
136 Reserved.set(ARM::D16 + i);
138 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
139 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
140 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
141 if (Reserved.test(*SI)) Reserved.set(*I);
146 const TargetRegisterClass*
147 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
149 const TargetRegisterClass *Super = RC;
150 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
152 switch (Super->getID()) {
153 case ARM::GPRRegClassID:
154 case ARM::SPRRegClassID:
155 case ARM::DPRRegClassID:
156 case ARM::QPRRegClassID:
157 case ARM::QQPRRegClassID:
158 case ARM::QQQQPRRegClassID:
159 case ARM::GPRPairRegClassID:
167 const TargetRegisterClass *
168 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
170 return &ARM::GPRRegClass;
173 const TargetRegisterClass *
174 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
175 if (RC == &ARM::CCRRegClass)
176 return 0; // Can't copy CCR registers.
181 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
182 MachineFunction &MF) const {
183 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
185 switch (RC->getID()) {
188 case ARM::tGPRRegClassID:
189 return TFI->hasFP(MF) ? 4 : 5;
190 case ARM::GPRRegClassID: {
191 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
192 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
194 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
195 case ARM::DPRRegClassID:
200 // Get the other register in a GPRPair.
201 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
202 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
203 if (ARM::GPRPairRegClass.contains(*Supers))
204 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
208 // Resolve the RegPairEven / RegPairOdd register allocator hints.
210 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
211 ArrayRef<MCPhysReg> Order,
212 SmallVectorImpl<MCPhysReg> &Hints,
213 const MachineFunction &MF,
214 const VirtRegMap *VRM) const {
215 const MachineRegisterInfo &MRI = MF.getRegInfo();
216 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
219 switch (Hint.first) {
220 case ARMRI::RegPairEven:
223 case ARMRI::RegPairOdd:
227 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
231 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
232 // Check if the other part of the pair has already been assigned, and provide
233 // the paired register as the first hint.
234 unsigned PairedPhys = 0;
235 if (VRM && VRM->hasPhys(Hint.second)) {
236 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
237 if (PairedPhys && MRI.isReserved(PairedPhys))
241 // First prefer the paired physreg.
243 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
244 Hints.push_back(PairedPhys);
246 // Then prefer even or odd registers.
247 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
248 unsigned Reg = Order[I];
249 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
251 // Don't provide hints that are paired to a reserved register.
252 unsigned Paired = getPairedGPR(Reg, !Odd, this);
253 if (!Paired || MRI.isReserved(Paired))
255 Hints.push_back(Reg);
260 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
261 MachineFunction &MF) const {
262 MachineRegisterInfo *MRI = &MF.getRegInfo();
263 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
264 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
265 Hint.first == (unsigned)ARMRI::RegPairEven) &&
266 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
267 // If 'Reg' is one of the even / odd register pair and it's now changed
268 // (e.g. coalesced) into a different register. The other register of the
269 // pair allocation hint must be updated to reflect the relationship
271 unsigned OtherReg = Hint.second;
272 Hint = MRI->getRegAllocationHint(OtherReg);
273 if (Hint.second == Reg)
274 // Make sure the pair has not already divorced.
275 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
280 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
281 // CortexA9 has a Write-after-write hazard for NEON registers.
285 switch (RC->getID()) {
286 case ARM::DPRRegClassID:
287 case ARM::DPR_8RegClassID:
288 case ARM::DPR_VFP2RegClassID:
289 case ARM::QPRRegClassID:
290 case ARM::QPR_8RegClassID:
291 case ARM::QPR_VFP2RegClassID:
292 case ARM::SPRRegClassID:
293 case ARM::SPR_8RegClassID:
294 // Avoid reusing S, D, and Q registers.
295 // Don't increase register pressure for QQ and QQQQ.
302 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
303 const MachineFrameInfo *MFI = MF.getFrameInfo();
304 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
305 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
307 // When outgoing call frames are so large that we adjust the stack pointer
308 // around the call, we can no longer use the stack pointer to reach the
309 // emergency spill slot.
310 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
313 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
314 // negative range for ldr/str (255), and thumb1 is positive offsets only.
315 // It's going to be better to use the SP or Base Pointer instead. When there
316 // are variable sized objects, we can't reference off of the SP, so we
317 // reserve a Base Pointer.
318 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
319 // Conservatively estimate whether the negative offset from the frame
320 // pointer will be sufficient to reach. If a function has a smallish
321 // frame, it's less likely to have lots of spills and callee saved
322 // space, so it's all more likely to be within range of the frame pointer.
323 // If it's wrong, the scavenger will still enable access to work, it just
325 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
333 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
334 const MachineRegisterInfo *MRI = &MF.getRegInfo();
335 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
336 // We can't realign the stack if:
337 // 1. Dynamic stack realignment is explicitly disabled,
338 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
339 // 3. There are VLAs in the function and the base pointer is disabled.
340 if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
342 if (AFI->isThumb1OnlyFunction())
344 // Stack realignment requires a frame pointer. If we already started
345 // register allocation with frame pointer elimination, it is too late now.
346 if (!MRI->canReserveReg(FramePtr))
348 // We may also need a base pointer if there are dynamic allocas or stack
349 // pointer adjustments around calls.
350 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
352 // A base pointer is required and allowed. Check that it isn't too late to
354 return MRI->canReserveReg(BasePtr);
357 bool ARMBaseRegisterInfo::
358 needsStackRealignment(const MachineFunction &MF) const {
359 const MachineFrameInfo *MFI = MF.getFrameInfo();
360 const Function *F = MF.getFunction();
361 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
362 bool requiresRealignment =
363 ((MFI->getMaxAlignment() > StackAlign) ||
364 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
365 Attribute::StackAlignment));
367 return requiresRealignment && canRealignStack(MF);
370 bool ARMBaseRegisterInfo::
371 cannotEliminateFrame(const MachineFunction &MF) const {
372 const MachineFrameInfo *MFI = MF.getFrameInfo();
373 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
375 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
376 || needsStackRealignment(MF);
380 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
381 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
388 /// emitLoadConstPool - Emits a load from constpool to materialize the
389 /// specified immediate.
390 void ARMBaseRegisterInfo::
391 emitLoadConstPool(MachineBasicBlock &MBB,
392 MachineBasicBlock::iterator &MBBI,
394 unsigned DestReg, unsigned SubIdx, int Val,
395 ARMCC::CondCodes Pred,
396 unsigned PredReg, unsigned MIFlags) const {
397 MachineFunction &MF = *MBB.getParent();
398 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
399 MachineConstantPool *ConstantPool = MF.getConstantPool();
401 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
402 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
404 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
405 .addReg(DestReg, getDefRegState(true), SubIdx)
406 .addConstantPoolIndex(Idx)
407 .addImm(0).addImm(Pred).addReg(PredReg)
408 .setMIFlags(MIFlags);
411 bool ARMBaseRegisterInfo::mayOverrideLocalAssignment() const {
412 // The native linux build hits a downstream codegen bug when this is enabled.
413 return STI.isTargetDarwin();
416 bool ARMBaseRegisterInfo::
417 requiresRegisterScavenging(const MachineFunction &MF) const {
421 bool ARMBaseRegisterInfo::
422 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
426 bool ARMBaseRegisterInfo::
427 requiresFrameIndexScavenging(const MachineFunction &MF) const {
431 bool ARMBaseRegisterInfo::
432 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
436 int64_t ARMBaseRegisterInfo::
437 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
438 const MCInstrDesc &Desc = MI->getDesc();
439 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
440 int64_t InstrOffs = 0;
444 case ARMII::AddrModeT2_i8:
445 case ARMII::AddrModeT2_i12:
446 case ARMII::AddrMode_i12:
447 InstrOffs = MI->getOperand(Idx+1).getImm();
450 case ARMII::AddrMode5: {
452 const MachineOperand &OffOp = MI->getOperand(Idx+1);
453 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
454 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
455 InstrOffs = -InstrOffs;
459 case ARMII::AddrMode2: {
461 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
462 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
463 InstrOffs = -InstrOffs;
466 case ARMII::AddrMode3: {
468 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
469 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
470 InstrOffs = -InstrOffs;
473 case ARMII::AddrModeT1_s: {
475 InstrOffs = MI->getOperand(ImmIdx).getImm();
480 llvm_unreachable("Unsupported addressing mode!");
483 return InstrOffs * Scale;
486 /// needsFrameBaseReg - Returns true if the instruction's frame index
487 /// reference would be better served by a base register other than FP
488 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
489 /// references it should create new base registers for.
490 bool ARMBaseRegisterInfo::
491 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
492 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
493 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
496 // It's the load/store FI references that cause issues, as it can be difficult
497 // to materialize the offset if it won't fit in the literal field. Estimate
498 // based on the size of the local frame and some conservative assumptions
499 // about the rest of the stack frame (note, this is pre-regalloc, so
500 // we don't know everything for certain yet) whether this offset is likely
501 // to be out of range of the immediate. Return true if so.
503 // We only generate virtual base registers for loads and stores, so
504 // return false for everything else.
505 unsigned Opc = MI->getOpcode();
507 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
508 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
509 case ARM::t2LDRi12: case ARM::t2LDRi8:
510 case ARM::t2STRi12: case ARM::t2STRi8:
511 case ARM::VLDRS: case ARM::VLDRD:
512 case ARM::VSTRS: case ARM::VSTRD:
513 case ARM::tSTRspi: case ARM::tLDRspi:
519 // Without a virtual base register, if the function has variable sized
520 // objects, all fixed-size local references will be via the frame pointer,
521 // Approximate the offset and see if it's legal for the instruction.
522 // Note that the incoming offset is based on the SP value at function entry,
523 // so it'll be negative.
524 MachineFunction &MF = *MI->getParent()->getParent();
525 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
526 MachineFrameInfo *MFI = MF.getFrameInfo();
527 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
529 // Estimate an offset from the frame pointer.
530 // Conservatively assume all callee-saved registers get pushed. R4-R6
531 // will be earlier than the FP, so we ignore those.
533 int64_t FPOffset = Offset - 8;
534 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
535 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
537 // Estimate an offset from the stack pointer.
538 // The incoming offset is relating to the SP at the start of the function,
539 // but when we access the local it'll be relative to the SP after local
540 // allocation, so adjust our SP-relative offset by that allocation size.
542 Offset += MFI->getLocalFrameSize();
543 // Assume that we'll have at least some spill slots allocated.
544 // FIXME: This is a total SWAG number. We should run some statistics
545 // and pick a real one.
546 Offset += 128; // 128 bytes of spill slots
548 // If there is a frame pointer, try using it.
549 // The FP is only available if there is no dynamic realignment. We
550 // don't know for sure yet whether we'll need that, so we guess based
551 // on whether there are any local variables that would trigger it.
552 unsigned StackAlign = TFI->getStackAlignment();
553 if (TFI->hasFP(MF) &&
554 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
555 if (isFrameOffsetLegal(MI, FPOffset))
558 // If we can reference via the stack pointer, try that.
559 // FIXME: This (and the code that resolves the references) can be improved
560 // to only disallow SP relative references in the live range of
561 // the VLA(s). In practice, it's unclear how much difference that
562 // would make, but it may be worth doing.
563 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
566 // The offset likely isn't legal, we want to allocate a virtual base register.
570 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
571 /// be a pointer to FrameIdx at the beginning of the basic block.
572 void ARMBaseRegisterInfo::
573 materializeFrameBaseRegister(MachineBasicBlock *MBB,
574 unsigned BaseReg, int FrameIdx,
575 int64_t Offset) const {
576 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
577 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
578 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
580 MachineBasicBlock::iterator Ins = MBB->begin();
581 DebugLoc DL; // Defaults to "unknown"
582 if (Ins != MBB->end())
583 DL = Ins->getDebugLoc();
585 const MachineFunction &MF = *MBB->getParent();
586 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
587 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
588 const MCInstrDesc &MCID = TII.get(ADDriOpc);
589 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
591 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
592 .addFrameIndex(FrameIdx).addImm(Offset));
594 if (!AFI->isThumb1OnlyFunction())
599 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
600 unsigned BaseReg, int64_t Offset) const {
601 MachineInstr &MI = *I;
602 MachineBasicBlock &MBB = *MI.getParent();
603 MachineFunction &MF = *MBB.getParent();
604 const ARMBaseInstrInfo &TII =
605 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
606 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
607 int Off = Offset; // ARM doesn't need the general 64-bit offsets
610 assert(!AFI->isThumb1OnlyFunction() &&
611 "This resolveFrameIndex does not support Thumb1!");
613 while (!MI.getOperand(i).isFI()) {
615 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
618 if (!AFI->isThumbFunction())
619 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
621 assert(AFI->isThumb2Function());
622 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
624 assert (Done && "Unable to resolve frame index!");
628 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
629 int64_t Offset) const {
630 const MCInstrDesc &Desc = MI->getDesc();
631 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
634 while (!MI->getOperand(i).isFI()) {
636 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
639 // AddrMode4 and AddrMode6 cannot handle any offset.
640 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
643 unsigned NumBits = 0;
645 bool isSigned = true;
647 case ARMII::AddrModeT2_i8:
648 case ARMII::AddrModeT2_i12:
649 // i8 supports only negative, and i12 supports only positive, so
650 // based on Offset sign, consider the appropriate instruction
659 case ARMII::AddrMode5:
664 case ARMII::AddrMode_i12:
665 case ARMII::AddrMode2:
668 case ARMII::AddrMode3:
671 case ARMII::AddrModeT1_s:
677 llvm_unreachable("Unsupported addressing mode!");
680 Offset += getFrameIndexInstrOffset(MI, i);
681 // Make sure the offset is encodable for instructions that scale the
683 if ((Offset & (Scale-1)) != 0)
686 if (isSigned && Offset < 0)
689 unsigned Mask = (1 << NumBits) - 1;
690 if ((unsigned)Offset <= Mask * Scale)
697 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
698 int SPAdj, unsigned FIOperandNum,
699 RegScavenger *RS) const {
700 MachineInstr &MI = *II;
701 MachineBasicBlock &MBB = *MI.getParent();
702 MachineFunction &MF = *MBB.getParent();
703 const ARMBaseInstrInfo &TII =
704 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo());
705 const ARMFrameLowering *TFI =
706 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
707 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
708 assert(!AFI->isThumb1OnlyFunction() &&
709 "This eliminateFrameIndex does not support Thumb1!");
710 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
713 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
715 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
716 // call frame setup/destroy instructions have already been eliminated. That
717 // means the stack pointer cannot be used to access the emergency spill slot
718 // when !hasReservedCallFrame().
720 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
721 assert(TFI->hasReservedCallFrame(MF) &&
722 "Cannot use SP to access the emergency spill slot in "
723 "functions without a reserved call frame");
724 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
725 "Cannot use SP to access the emergency spill slot in "
726 "functions with variable sized frame objects");
730 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
732 // Modify MI as necessary to handle as much of 'Offset' as possible
734 if (!AFI->isThumbFunction())
735 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
737 assert(AFI->isThumb2Function());
738 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
743 // If we get here, the immediate doesn't fit into the instruction. We folded
744 // as much as possible above, handle the rest, providing a register that is
747 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
748 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
749 "This code isn't needed if offset already handled!");
751 unsigned ScratchReg = 0;
752 int PIdx = MI.findFirstPredOperandIdx();
753 ARMCC::CondCodes Pred = (PIdx == -1)
754 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
755 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
757 // Must be addrmode4/6.
758 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
760 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
761 if (!AFI->isThumbFunction())
762 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
763 Offset, Pred, PredReg, TII);
765 assert(AFI->isThumb2Function());
766 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
767 Offset, Pred, PredReg, TII);
769 // Update the original instruction to use the scratch register.
770 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);