1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMFrameLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMSubtarget.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/LLVMContext.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/SmallVector.h"
41 #include "llvm/Support/CommandLine.h"
46 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
47 cl::desc("Force use of virtual base registers for stack load/store"));
49 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
50 cl::desc("Enable pre-regalloc stack frame index allocation"));
52 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
53 cl::desc("Enable use of a base pointer for complex stack frames"));
55 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
56 const ARMSubtarget &sti)
57 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 static const unsigned CalleeSavedRegs[] = {
66 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
67 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
69 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
70 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
74 static const unsigned DarwinCalleeSavedRegs[] = {
75 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
78 ARM::R11, ARM::R10, ARM::R8,
80 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
81 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
84 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
87 BitVector ARMBaseRegisterInfo::
88 getReservedRegs(const MachineFunction &MF) const {
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 // FIXME: avoid re-calculating this everytime.
92 BitVector Reserved(getNumRegs());
93 Reserved.set(ARM::SP);
94 Reserved.set(ARM::PC);
95 Reserved.set(ARM::FPSCR);
97 Reserved.set(FramePtr);
98 if (hasBasePointer(MF))
99 Reserved.set(BasePtr);
100 // Some targets reserve R9.
101 if (STI.isR9Reserved())
102 Reserved.set(ARM::R9);
106 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
107 unsigned Reg) const {
108 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
116 if (hasBasePointer(MF))
121 if (FramePtr == Reg && TFI->hasFP(MF))
125 return STI.isR9Reserved();
131 const TargetRegisterClass *
132 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
133 const TargetRegisterClass *B,
134 unsigned SubIdx) const {
142 if (A->getSize() == 8) {
143 if (B == &ARM::SPR_8RegClass)
144 return &ARM::DPR_8RegClass;
145 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
146 if (A == &ARM::DPR_8RegClass)
148 return &ARM::DPR_VFP2RegClass;
151 if (A->getSize() == 16) {
152 if (B == &ARM::SPR_8RegClass)
153 return &ARM::QPR_8RegClass;
154 return &ARM::QPR_VFP2RegClass;
157 if (A->getSize() == 32) {
158 if (B == &ARM::SPR_8RegClass)
159 return 0; // Do not allow coalescing!
160 return &ARM::QQPR_VFP2RegClass;
163 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
164 return 0; // Do not allow coalescing!
171 if (A->getSize() == 16) {
172 if (B == &ARM::DPR_VFP2RegClass)
173 return &ARM::QPR_VFP2RegClass;
174 if (B == &ARM::DPR_8RegClass)
175 return 0; // Do not allow coalescing!
179 if (A->getSize() == 32) {
180 if (B == &ARM::DPR_VFP2RegClass)
181 return &ARM::QQPR_VFP2RegClass;
182 if (B == &ARM::DPR_8RegClass)
183 return 0; // Do not allow coalescing!
187 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
188 if (B != &ARM::DPRRegClass)
189 return 0; // Do not allow coalescing!
196 // D sub-registers of QQQQ registers.
197 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
199 return 0; // Do not allow coalescing!
205 if (A->getSize() == 32) {
206 if (B == &ARM::QPR_VFP2RegClass)
207 return &ARM::QQPR_VFP2RegClass;
208 if (B == &ARM::QPR_8RegClass)
209 return 0; // Do not allow coalescing!
213 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
214 if (B == &ARM::QPRRegClass)
216 return 0; // Do not allow coalescing!
220 // Q sub-registers of QQQQ registers.
221 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
223 return 0; // Do not allow coalescing!
230 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
231 SmallVectorImpl<unsigned> &SubIndices,
232 unsigned &NewSubIdx) const {
234 unsigned Size = RC->getSize() * 8;
238 NewSubIdx = 0; // Whole register.
239 unsigned NumRegs = SubIndices.size();
241 // 8 D registers -> 1 QQQQ register.
242 return (Size == 512 &&
243 SubIndices[0] == ARM::dsub_0 &&
244 SubIndices[1] == ARM::dsub_1 &&
245 SubIndices[2] == ARM::dsub_2 &&
246 SubIndices[3] == ARM::dsub_3 &&
247 SubIndices[4] == ARM::dsub_4 &&
248 SubIndices[5] == ARM::dsub_5 &&
249 SubIndices[6] == ARM::dsub_6 &&
250 SubIndices[7] == ARM::dsub_7);
251 } else if (NumRegs == 4) {
252 if (SubIndices[0] == ARM::qsub_0) {
253 // 4 Q registers -> 1 QQQQ register.
254 return (Size == 512 &&
255 SubIndices[1] == ARM::qsub_1 &&
256 SubIndices[2] == ARM::qsub_2 &&
257 SubIndices[3] == ARM::qsub_3);
258 } else if (SubIndices[0] == ARM::dsub_0) {
259 // 4 D registers -> 1 QQ register.
261 SubIndices[1] == ARM::dsub_1 &&
262 SubIndices[2] == ARM::dsub_2 &&
263 SubIndices[3] == ARM::dsub_3) {
265 NewSubIdx = ARM::qqsub_0;
268 } else if (SubIndices[0] == ARM::dsub_4) {
269 // 4 D registers -> 1 QQ register (2nd).
271 SubIndices[1] == ARM::dsub_5 &&
272 SubIndices[2] == ARM::dsub_6 &&
273 SubIndices[3] == ARM::dsub_7) {
274 NewSubIdx = ARM::qqsub_1;
277 } else if (SubIndices[0] == ARM::ssub_0) {
278 // 4 S registers -> 1 Q register.
280 SubIndices[1] == ARM::ssub_1 &&
281 SubIndices[2] == ARM::ssub_2 &&
282 SubIndices[3] == ARM::ssub_3) {
284 NewSubIdx = ARM::qsub_0;
288 } else if (NumRegs == 2) {
289 if (SubIndices[0] == ARM::qsub_0) {
290 // 2 Q registers -> 1 QQ register.
291 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
293 NewSubIdx = ARM::qqsub_0;
296 } else if (SubIndices[0] == ARM::qsub_2) {
297 // 2 Q registers -> 1 QQ register (2nd).
298 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
299 NewSubIdx = ARM::qqsub_1;
302 } else if (SubIndices[0] == ARM::dsub_0) {
303 // 2 D registers -> 1 Q register.
304 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
306 NewSubIdx = ARM::qsub_0;
309 } else if (SubIndices[0] == ARM::dsub_2) {
310 // 2 D registers -> 1 Q register (2nd).
311 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
312 NewSubIdx = ARM::qsub_1;
315 } else if (SubIndices[0] == ARM::dsub_4) {
316 // 2 D registers -> 1 Q register (3rd).
317 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
318 NewSubIdx = ARM::qsub_2;
321 } else if (SubIndices[0] == ARM::dsub_6) {
322 // 2 D registers -> 1 Q register (3rd).
323 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
324 NewSubIdx = ARM::qsub_3;
327 } else if (SubIndices[0] == ARM::ssub_0) {
328 // 2 S registers -> 1 D register.
329 if (SubIndices[1] == ARM::ssub_1) {
331 NewSubIdx = ARM::dsub_0;
334 } else if (SubIndices[0] == ARM::ssub_2) {
335 // 2 S registers -> 1 D register (2nd).
336 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
337 NewSubIdx = ARM::dsub_1;
346 const TargetRegisterClass *
347 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
348 return ARM::GPRRegisterClass;
352 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
353 MachineFunction &MF) const {
354 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
356 switch (RC->getID()) {
359 case ARM::tGPRRegClassID:
360 return TFI->hasFP(MF) ? 4 : 5;
361 case ARM::GPRRegClassID: {
362 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
363 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
365 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
366 case ARM::DPRRegClassID:
371 /// getAllocationOrder - Returns the register allocation order for a specified
372 /// register class in the form of a pair of TargetRegisterClass iterators.
373 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
374 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
375 unsigned HintType, unsigned HintReg,
376 const MachineFunction &MF) const {
377 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
378 // Alternative register allocation orders when favoring even / odd registers
379 // of register pairs.
381 // No FP, R9 is available.
382 static const unsigned GPREven1[] = {
383 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
384 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
387 static const unsigned GPROdd1[] = {
388 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
389 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
393 // FP is R7, R9 is available.
394 static const unsigned GPREven2[] = {
395 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
396 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
399 static const unsigned GPROdd2[] = {
400 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
401 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
405 // FP is R11, R9 is available.
406 static const unsigned GPREven3[] = {
407 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
408 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
411 static const unsigned GPROdd3[] = {
412 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
413 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
417 // No FP, R9 is not available.
418 static const unsigned GPREven4[] = {
419 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
420 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
423 static const unsigned GPROdd4[] = {
424 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
425 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
429 // FP is R7, R9 is not available.
430 static const unsigned GPREven5[] = {
431 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
432 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
435 static const unsigned GPROdd5[] = {
436 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
437 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
441 // FP is R11, R9 is not available.
442 static const unsigned GPREven6[] = {
443 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
444 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
446 static const unsigned GPROdd6[] = {
447 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
448 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
452 if (HintType == ARMRI::RegPairEven) {
453 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
454 // It's no longer possible to fulfill this hint. Return the default
456 return std::make_pair(RC->allocation_order_begin(MF),
457 RC->allocation_order_end(MF));
459 if (!TFI->hasFP(MF)) {
460 if (!STI.isR9Reserved())
461 return std::make_pair(GPREven1,
462 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
464 return std::make_pair(GPREven4,
465 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
466 } else if (FramePtr == ARM::R7) {
467 if (!STI.isR9Reserved())
468 return std::make_pair(GPREven2,
469 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
471 return std::make_pair(GPREven5,
472 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
473 } else { // FramePtr == ARM::R11
474 if (!STI.isR9Reserved())
475 return std::make_pair(GPREven3,
476 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
478 return std::make_pair(GPREven6,
479 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
481 } else if (HintType == ARMRI::RegPairOdd) {
482 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
483 // It's no longer possible to fulfill this hint. Return the default
485 return std::make_pair(RC->allocation_order_begin(MF),
486 RC->allocation_order_end(MF));
488 if (!TFI->hasFP(MF)) {
489 if (!STI.isR9Reserved())
490 return std::make_pair(GPROdd1,
491 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
493 return std::make_pair(GPROdd4,
494 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
495 } else if (FramePtr == ARM::R7) {
496 if (!STI.isR9Reserved())
497 return std::make_pair(GPROdd2,
498 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
500 return std::make_pair(GPROdd5,
501 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
502 } else { // FramePtr == ARM::R11
503 if (!STI.isR9Reserved())
504 return std::make_pair(GPROdd3,
505 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
507 return std::make_pair(GPROdd6,
508 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
511 return std::make_pair(RC->allocation_order_begin(MF),
512 RC->allocation_order_end(MF));
515 /// ResolveRegAllocHint - Resolves the specified register allocation hint
516 /// to a physical register. Returns the physical register if it is successful.
518 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
519 const MachineFunction &MF) const {
520 if (Reg == 0 || !isPhysicalRegister(Reg))
524 else if (Type == (unsigned)ARMRI::RegPairOdd)
526 return getRegisterPairOdd(Reg, MF);
527 else if (Type == (unsigned)ARMRI::RegPairEven)
529 return getRegisterPairEven(Reg, MF);
534 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
535 MachineFunction &MF) const {
536 MachineRegisterInfo *MRI = &MF.getRegInfo();
537 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
538 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
539 Hint.first == (unsigned)ARMRI::RegPairEven) &&
540 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
541 // If 'Reg' is one of the even / odd register pair and it's now changed
542 // (e.g. coalesced) into a different register. The other register of the
543 // pair allocation hint must be updated to reflect the relationship
545 unsigned OtherReg = Hint.second;
546 Hint = MRI->getRegAllocationHint(OtherReg);
547 if (Hint.second == Reg)
548 // Make sure the pair has not already divorced.
549 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
553 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
554 const MachineFrameInfo *MFI = MF.getFrameInfo();
555 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
557 if (!EnableBasePointer)
560 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
563 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
564 // negative range for ldr/str (255), and thumb1 is positive offsets only.
565 // It's going to be better to use the SP or Base Pointer instead. When there
566 // are variable sized objects, we can't reference off of the SP, so we
567 // reserve a Base Pointer.
568 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
569 // Conservatively estimate whether the negative offset from the frame
570 // pointer will be sufficient to reach. If a function has a smallish
571 // frame, it's less likely to have lots of spills and callee saved
572 // space, so it's all more likely to be within range of the frame pointer.
573 // If it's wrong, the scavenger will still enable access to work, it just
575 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
583 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
584 const MachineFrameInfo *MFI = MF.getFrameInfo();
585 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
586 // We can't realign the stack if:
587 // 1. Dynamic stack realignment is explicitly disabled,
588 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
589 // 3. There are VLAs in the function and the base pointer is disabled.
590 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
591 (!MFI->hasVarSizedObjects() || EnableBasePointer));
594 bool ARMBaseRegisterInfo::
595 needsStackRealignment(const MachineFunction &MF) const {
596 const MachineFrameInfo *MFI = MF.getFrameInfo();
597 const Function *F = MF.getFunction();
598 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
599 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
600 F->hasFnAttr(Attribute::StackAlignment));
602 return requiresRealignment && canRealignStack(MF);
605 bool ARMBaseRegisterInfo::
606 cannotEliminateFrame(const MachineFunction &MF) const {
607 const MachineFrameInfo *MFI = MF.getFrameInfo();
608 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
610 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
611 || needsStackRealignment(MF);
614 unsigned ARMBaseRegisterInfo::getRARegister() const {
619 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
620 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
627 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
628 llvm_unreachable("What is the exception register");
632 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
633 llvm_unreachable("What is the exception handler register");
637 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
638 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
641 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
642 const MachineFunction &MF) const {
645 // Return 0 if either register of the pair is a special register.
654 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
657 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
659 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
731 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
732 const MachineFunction &MF) const {
735 // Return 0 if either register of the pair is a special register.
744 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
747 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
749 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
821 /// emitLoadConstPool - Emits a load from constpool to materialize the
822 /// specified immediate.
823 void ARMBaseRegisterInfo::
824 emitLoadConstPool(MachineBasicBlock &MBB,
825 MachineBasicBlock::iterator &MBBI,
827 unsigned DestReg, unsigned SubIdx, int Val,
828 ARMCC::CondCodes Pred,
829 unsigned PredReg, unsigned MIFlags) const {
830 MachineFunction &MF = *MBB.getParent();
831 MachineConstantPool *ConstantPool = MF.getConstantPool();
833 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
834 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
836 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
837 .addReg(DestReg, getDefRegState(true), SubIdx)
838 .addConstantPoolIndex(Idx)
839 .addImm(0).addImm(Pred).addReg(PredReg)
840 .setMIFlags(MIFlags);
843 bool ARMBaseRegisterInfo::
844 requiresRegisterScavenging(const MachineFunction &MF) const {
848 bool ARMBaseRegisterInfo::
849 requiresFrameIndexScavenging(const MachineFunction &MF) const {
853 bool ARMBaseRegisterInfo::
854 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
855 return EnableLocalStackAlloc;
859 emitSPUpdate(bool isARM,
860 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
861 DebugLoc dl, const ARMBaseInstrInfo &TII,
863 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
865 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
868 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
873 void ARMBaseRegisterInfo::
874 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
875 MachineBasicBlock::iterator I) const {
876 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
877 if (!TFI->hasReservedCallFrame(MF)) {
878 // If we have alloca, convert as follows:
879 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
880 // ADJCALLSTACKUP -> add, sp, sp, amount
881 MachineInstr *Old = I;
882 DebugLoc dl = Old->getDebugLoc();
883 unsigned Amount = Old->getOperand(0).getImm();
885 // We need to keep the stack aligned properly. To do this, we round the
886 // amount of space needed for the outgoing arguments up to the next
887 // alignment boundary.
888 unsigned Align = TFI->getStackAlignment();
889 Amount = (Amount+Align-1)/Align*Align;
891 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
892 assert(!AFI->isThumb1OnlyFunction() &&
893 "This eliminateCallFramePseudoInstr does not support Thumb1!");
894 bool isARM = !AFI->isThumbFunction();
896 // Replace the pseudo instruction with a new instruction...
897 unsigned Opc = Old->getOpcode();
898 int PIdx = Old->findFirstPredOperandIdx();
899 ARMCC::CondCodes Pred = (PIdx == -1)
900 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
901 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
902 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
903 unsigned PredReg = Old->getOperand(2).getReg();
904 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
906 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
907 unsigned PredReg = Old->getOperand(3).getReg();
908 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
909 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
916 int64_t ARMBaseRegisterInfo::
917 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
918 const TargetInstrDesc &Desc = MI->getDesc();
919 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
920 int64_t InstrOffs = 0;;
924 case ARMII::AddrModeT2_i8:
925 case ARMII::AddrModeT2_i12:
926 case ARMII::AddrMode_i12:
927 InstrOffs = MI->getOperand(Idx+1).getImm();
930 case ARMII::AddrMode5: {
932 const MachineOperand &OffOp = MI->getOperand(Idx+1);
933 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
934 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
935 InstrOffs = -InstrOffs;
939 case ARMII::AddrMode2: {
941 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
942 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
943 InstrOffs = -InstrOffs;
946 case ARMII::AddrMode3: {
948 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
949 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
950 InstrOffs = -InstrOffs;
953 case ARMII::AddrModeT1_s: {
955 InstrOffs = MI->getOperand(ImmIdx).getImm();
960 llvm_unreachable("Unsupported addressing mode!");
964 return InstrOffs * Scale;
967 /// needsFrameBaseReg - Returns true if the instruction's frame index
968 /// reference would be better served by a base register other than FP
969 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
970 /// references it should create new base registers for.
971 bool ARMBaseRegisterInfo::
972 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
973 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
974 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
977 // It's the load/store FI references that cause issues, as it can be difficult
978 // to materialize the offset if it won't fit in the literal field. Estimate
979 // based on the size of the local frame and some conservative assumptions
980 // about the rest of the stack frame (note, this is pre-regalloc, so
981 // we don't know everything for certain yet) whether this offset is likely
982 // to be out of range of the immediate. Return true if so.
984 // We only generate virtual base registers for loads and stores, so
985 // return false for everything else.
986 unsigned Opc = MI->getOpcode();
988 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
989 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
990 case ARM::t2LDRi12: case ARM::t2LDRi8:
991 case ARM::t2STRi12: case ARM::t2STRi8:
992 case ARM::VLDRS: case ARM::VLDRD:
993 case ARM::VSTRS: case ARM::VSTRD:
994 case ARM::tSTRspi: case ARM::tLDRspi:
995 if (ForceAllBaseRegAlloc)
1002 // Without a virtual base register, if the function has variable sized
1003 // objects, all fixed-size local references will be via the frame pointer,
1004 // Approximate the offset and see if it's legal for the instruction.
1005 // Note that the incoming offset is based on the SP value at function entry,
1006 // so it'll be negative.
1007 MachineFunction &MF = *MI->getParent()->getParent();
1008 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
1009 MachineFrameInfo *MFI = MF.getFrameInfo();
1010 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1012 // Estimate an offset from the frame pointer.
1013 // Conservatively assume all callee-saved registers get pushed. R4-R6
1014 // will be earlier than the FP, so we ignore those.
1016 int64_t FPOffset = Offset - 8;
1017 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1018 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1020 // Estimate an offset from the stack pointer.
1021 // The incoming offset is relating to the SP at the start of the function,
1022 // but when we access the local it'll be relative to the SP after local
1023 // allocation, so adjust our SP-relative offset by that allocation size.
1025 Offset += MFI->getLocalFrameSize();
1026 // Assume that we'll have at least some spill slots allocated.
1027 // FIXME: This is a total SWAG number. We should run some statistics
1028 // and pick a real one.
1029 Offset += 128; // 128 bytes of spill slots
1031 // If there is a frame pointer, try using it.
1032 // The FP is only available if there is no dynamic realignment. We
1033 // don't know for sure yet whether we'll need that, so we guess based
1034 // on whether there are any local variables that would trigger it.
1035 unsigned StackAlign = TFI->getStackAlignment();
1036 if (TFI->hasFP(MF) &&
1037 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1038 if (isFrameOffsetLegal(MI, FPOffset))
1041 // If we can reference via the stack pointer, try that.
1042 // FIXME: This (and the code that resolves the references) can be improved
1043 // to only disallow SP relative references in the live range of
1044 // the VLA(s). In practice, it's unclear how much difference that
1045 // would make, but it may be worth doing.
1046 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1049 // The offset likely isn't legal, we want to allocate a virtual base register.
1053 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1054 /// be a pointer to FrameIdx at the beginning of the basic block.
1055 void ARMBaseRegisterInfo::
1056 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1057 unsigned BaseReg, int FrameIdx,
1058 int64_t Offset) const {
1059 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1060 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1061 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1063 MachineBasicBlock::iterator Ins = MBB->begin();
1064 DebugLoc DL; // Defaults to "unknown"
1065 if (Ins != MBB->end())
1066 DL = Ins->getDebugLoc();
1068 MachineInstrBuilder MIB =
1069 BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)
1070 .addFrameIndex(FrameIdx).addImm(Offset);
1072 if (!AFI->isThumb1OnlyFunction())
1073 AddDefaultCC(AddDefaultPred(MIB));
1077 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1078 unsigned BaseReg, int64_t Offset) const {
1079 MachineInstr &MI = *I;
1080 MachineBasicBlock &MBB = *MI.getParent();
1081 MachineFunction &MF = *MBB.getParent();
1082 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1083 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1086 assert(!AFI->isThumb1OnlyFunction() &&
1087 "This resolveFrameIndex does not support Thumb1!");
1089 while (!MI.getOperand(i).isFI()) {
1091 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1094 if (!AFI->isThumbFunction())
1095 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1097 assert(AFI->isThumb2Function());
1098 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1100 assert (Done && "Unable to resolve frame index!");
1103 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1104 int64_t Offset) const {
1105 const TargetInstrDesc &Desc = MI->getDesc();
1106 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1109 while (!MI->getOperand(i).isFI()) {
1111 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1114 // AddrMode4 and AddrMode6 cannot handle any offset.
1115 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1118 unsigned NumBits = 0;
1120 bool isSigned = true;
1122 case ARMII::AddrModeT2_i8:
1123 case ARMII::AddrModeT2_i12:
1124 // i8 supports only negative, and i12 supports only positive, so
1125 // based on Offset sign, consider the appropriate instruction
1134 case ARMII::AddrMode5:
1135 // VFP address mode.
1139 case ARMII::AddrMode_i12:
1140 case ARMII::AddrMode2:
1143 case ARMII::AddrMode3:
1146 case ARMII::AddrModeT1_s:
1152 llvm_unreachable("Unsupported addressing mode!");
1156 Offset += getFrameIndexInstrOffset(MI, i);
1157 // Make sure the offset is encodable for instructions that scale the
1159 if ((Offset & (Scale-1)) != 0)
1162 if (isSigned && Offset < 0)
1165 unsigned Mask = (1 << NumBits) - 1;
1166 if ((unsigned)Offset <= Mask * Scale)
1173 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1174 int SPAdj, RegScavenger *RS) const {
1176 MachineInstr &MI = *II;
1177 MachineBasicBlock &MBB = *MI.getParent();
1178 MachineFunction &MF = *MBB.getParent();
1179 const ARMFrameLowering *TFI =
1180 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1181 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1182 assert(!AFI->isThumb1OnlyFunction() &&
1183 "This eliminateFrameIndex does not support Thumb1!");
1185 while (!MI.getOperand(i).isFI()) {
1187 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1190 int FrameIndex = MI.getOperand(i).getIndex();
1193 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1195 // Special handling of dbg_value instructions.
1196 if (MI.isDebugValue()) {
1197 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1198 MI.getOperand(i+1).ChangeToImmediate(Offset);
1202 // Modify MI as necessary to handle as much of 'Offset' as possible
1204 if (!AFI->isThumbFunction())
1205 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1207 assert(AFI->isThumb2Function());
1208 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1213 // If we get here, the immediate doesn't fit into the instruction. We folded
1214 // as much as possible above, handle the rest, providing a register that is
1217 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1218 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1219 "This code isn't needed if offset already handled!");
1221 unsigned ScratchReg = 0;
1222 int PIdx = MI.findFirstPredOperandIdx();
1223 ARMCC::CondCodes Pred = (PIdx == -1)
1224 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1225 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1227 // Must be addrmode4/6.
1228 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1230 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1231 if (!AFI->isThumbFunction())
1232 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1233 Offset, Pred, PredReg, TII);
1235 assert(AFI->isThumb2Function());
1236 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1237 Offset, Pred, PredReg, TII);
1239 // Update the original instruction to use the scratch register.
1240 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1241 if (MI.getOpcode() == ARM::t2ADDrSPi)
1242 MI.setDesc(TII.get(ARM::t2ADDri));
1243 else if (MI.getOpcode() == ARM::t2SUBrSPi)
1244 MI.setDesc(TII.get(ARM::t2SUBri));
1248 #include "ARMGenRegisterInfo.inc"