1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/RegisterScavenging.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/Support/CommandLine.h"
41 #define GET_REGINFO_TARGET_DESC
42 #include "ARMGenRegisterInfo.inc"
47 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
48 cl::desc("Force use of virtual base registers for stack load/store"));
50 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
51 cl::desc("Enable pre-regalloc stack frame index allocation"));
53 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
56 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57 const ARMSubtarget &sti)
58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
64 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
66 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
70 ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71 return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
72 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
75 BitVector ARMBaseRegisterInfo::
76 getReservedRegs(const MachineFunction &MF) const {
77 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79 // FIXME: avoid re-calculating this every time.
80 BitVector Reserved(getNumRegs());
81 Reserved.set(ARM::SP);
82 Reserved.set(ARM::PC);
83 Reserved.set(ARM::FPSCR);
85 Reserved.set(FramePtr);
86 if (hasBasePointer(MF))
87 Reserved.set(BasePtr);
88 // Some targets reserve R9.
89 if (STI.isR9Reserved())
90 Reserved.set(ARM::R9);
91 // Reserve D16-D31 if the subtarget doesn't support them.
92 if (!STI.hasVFP3() || STI.hasD16()) {
93 assert(ARM::D31 == ARM::D16 + 15);
94 for (unsigned i = 0; i != 16; ++i)
95 Reserved.set(ARM::D16 + i);
100 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
101 unsigned Reg) const {
102 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
110 if (hasBasePointer(MF))
115 if (FramePtr == Reg && TFI->hasFP(MF))
119 return STI.isR9Reserved();
126 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
127 SmallVectorImpl<unsigned> &SubIndices,
128 unsigned &NewSubIdx) const {
130 unsigned Size = RC->getSize() * 8;
134 NewSubIdx = 0; // Whole register.
135 unsigned NumRegs = SubIndices.size();
137 // 8 D registers -> 1 QQQQ register.
138 return (Size == 512 &&
139 SubIndices[0] == ARM::dsub_0 &&
140 SubIndices[1] == ARM::dsub_1 &&
141 SubIndices[2] == ARM::dsub_2 &&
142 SubIndices[3] == ARM::dsub_3 &&
143 SubIndices[4] == ARM::dsub_4 &&
144 SubIndices[5] == ARM::dsub_5 &&
145 SubIndices[6] == ARM::dsub_6 &&
146 SubIndices[7] == ARM::dsub_7);
147 } else if (NumRegs == 4) {
148 if (SubIndices[0] == ARM::qsub_0) {
149 // 4 Q registers -> 1 QQQQ register.
150 return (Size == 512 &&
151 SubIndices[1] == ARM::qsub_1 &&
152 SubIndices[2] == ARM::qsub_2 &&
153 SubIndices[3] == ARM::qsub_3);
154 } else if (SubIndices[0] == ARM::dsub_0) {
155 // 4 D registers -> 1 QQ register.
157 SubIndices[1] == ARM::dsub_1 &&
158 SubIndices[2] == ARM::dsub_2 &&
159 SubIndices[3] == ARM::dsub_3) {
161 NewSubIdx = ARM::qqsub_0;
164 } else if (SubIndices[0] == ARM::dsub_4) {
165 // 4 D registers -> 1 QQ register (2nd).
167 SubIndices[1] == ARM::dsub_5 &&
168 SubIndices[2] == ARM::dsub_6 &&
169 SubIndices[3] == ARM::dsub_7) {
170 NewSubIdx = ARM::qqsub_1;
173 } else if (SubIndices[0] == ARM::ssub_0) {
174 // 4 S registers -> 1 Q register.
176 SubIndices[1] == ARM::ssub_1 &&
177 SubIndices[2] == ARM::ssub_2 &&
178 SubIndices[3] == ARM::ssub_3) {
180 NewSubIdx = ARM::qsub_0;
184 } else if (NumRegs == 2) {
185 if (SubIndices[0] == ARM::qsub_0) {
186 // 2 Q registers -> 1 QQ register.
187 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
189 NewSubIdx = ARM::qqsub_0;
192 } else if (SubIndices[0] == ARM::qsub_2) {
193 // 2 Q registers -> 1 QQ register (2nd).
194 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
195 NewSubIdx = ARM::qqsub_1;
198 } else if (SubIndices[0] == ARM::dsub_0) {
199 // 2 D registers -> 1 Q register.
200 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
202 NewSubIdx = ARM::qsub_0;
205 } else if (SubIndices[0] == ARM::dsub_2) {
206 // 2 D registers -> 1 Q register (2nd).
207 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
208 NewSubIdx = ARM::qsub_1;
211 } else if (SubIndices[0] == ARM::dsub_4) {
212 // 2 D registers -> 1 Q register (3rd).
213 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
214 NewSubIdx = ARM::qsub_2;
217 } else if (SubIndices[0] == ARM::dsub_6) {
218 // 2 D registers -> 1 Q register (3rd).
219 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
220 NewSubIdx = ARM::qsub_3;
223 } else if (SubIndices[0] == ARM::ssub_0) {
224 // 2 S registers -> 1 D register.
225 if (SubIndices[1] == ARM::ssub_1) {
227 NewSubIdx = ARM::dsub_0;
230 } else if (SubIndices[0] == ARM::ssub_2) {
231 // 2 S registers -> 1 D register (2nd).
232 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
233 NewSubIdx = ARM::dsub_1;
241 const TargetRegisterClass*
242 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
244 const TargetRegisterClass *Super = RC;
245 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
247 switch (Super->getID()) {
248 case ARM::GPRRegClassID:
249 case ARM::SPRRegClassID:
250 case ARM::DPRRegClassID:
251 case ARM::QPRRegClassID:
252 case ARM::QQPRRegClassID:
253 case ARM::QQQQPRRegClassID:
261 const TargetRegisterClass *
262 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
263 return &ARM::GPRRegClass;
266 const TargetRegisterClass *
267 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
268 if (RC == &ARM::CCRRegClass)
269 return 0; // Can't copy CCR registers.
274 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
275 MachineFunction &MF) const {
276 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
278 switch (RC->getID()) {
281 case ARM::tGPRRegClassID:
282 return TFI->hasFP(MF) ? 4 : 5;
283 case ARM::GPRRegClassID: {
284 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
285 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
287 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
288 case ARM::DPRRegClassID:
293 /// getRawAllocationOrder - Returns the register allocation order for a
294 /// specified register class with a target-dependent hint.
296 ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
297 unsigned HintType, unsigned HintReg,
298 const MachineFunction &MF) const {
299 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
300 // Alternative register allocation orders when favoring even / odd registers
301 // of register pairs.
303 // No FP, R9 is available.
304 static const uint16_t GPREven1[] = {
305 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
306 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
309 static const uint16_t GPROdd1[] = {
310 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
311 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
315 // FP is R7, R9 is available.
316 static const uint16_t GPREven2[] = {
317 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
318 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
321 static const uint16_t GPROdd2[] = {
322 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
323 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
327 // FP is R11, R9 is available.
328 static const uint16_t GPREven3[] = {
329 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
330 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
333 static const uint16_t GPROdd3[] = {
334 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
335 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
339 // No FP, R9 is not available.
340 static const uint16_t GPREven4[] = {
341 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
342 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
345 static const uint16_t GPROdd4[] = {
346 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
347 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
351 // FP is R7, R9 is not available.
352 static const uint16_t GPREven5[] = {
353 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
354 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
357 static const uint16_t GPROdd5[] = {
358 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
359 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
363 // FP is R11, R9 is not available.
364 static const uint16_t GPREven6[] = {
365 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
366 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
368 static const uint16_t GPROdd6[] = {
369 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
370 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
373 // We only support even/odd hints for GPR and rGPR.
374 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
375 return RC->getRawAllocationOrder(MF);
377 if (HintType == ARMRI::RegPairEven) {
378 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
379 // It's no longer possible to fulfill this hint. Return the default
381 return RC->getRawAllocationOrder(MF);
383 if (!TFI->hasFP(MF)) {
384 if (!STI.isR9Reserved())
385 return makeArrayRef(GPREven1);
387 return makeArrayRef(GPREven4);
388 } else if (FramePtr == ARM::R7) {
389 if (!STI.isR9Reserved())
390 return makeArrayRef(GPREven2);
392 return makeArrayRef(GPREven5);
393 } else { // FramePtr == ARM::R11
394 if (!STI.isR9Reserved())
395 return makeArrayRef(GPREven3);
397 return makeArrayRef(GPREven6);
399 } else if (HintType == ARMRI::RegPairOdd) {
400 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
401 // It's no longer possible to fulfill this hint. Return the default
403 return RC->getRawAllocationOrder(MF);
405 if (!TFI->hasFP(MF)) {
406 if (!STI.isR9Reserved())
407 return makeArrayRef(GPROdd1);
409 return makeArrayRef(GPROdd4);
410 } else if (FramePtr == ARM::R7) {
411 if (!STI.isR9Reserved())
412 return makeArrayRef(GPROdd2);
414 return makeArrayRef(GPROdd5);
415 } else { // FramePtr == ARM::R11
416 if (!STI.isR9Reserved())
417 return makeArrayRef(GPROdd3);
419 return makeArrayRef(GPROdd6);
422 return RC->getRawAllocationOrder(MF);
425 /// ResolveRegAllocHint - Resolves the specified register allocation hint
426 /// to a physical register. Returns the physical register if it is successful.
428 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
429 const MachineFunction &MF) const {
430 if (Reg == 0 || !isPhysicalRegister(Reg))
434 else if (Type == (unsigned)ARMRI::RegPairOdd)
436 return getRegisterPairOdd(Reg, MF);
437 else if (Type == (unsigned)ARMRI::RegPairEven)
439 return getRegisterPairEven(Reg, MF);
444 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
445 MachineFunction &MF) const {
446 MachineRegisterInfo *MRI = &MF.getRegInfo();
447 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
448 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
449 Hint.first == (unsigned)ARMRI::RegPairEven) &&
450 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
451 // If 'Reg' is one of the even / odd register pair and it's now changed
452 // (e.g. coalesced) into a different register. The other register of the
453 // pair allocation hint must be updated to reflect the relationship
455 unsigned OtherReg = Hint.second;
456 Hint = MRI->getRegAllocationHint(OtherReg);
457 if (Hint.second == Reg)
458 // Make sure the pair has not already divorced.
459 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
464 ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
465 // CortexA9 has a Write-after-write hazard for NEON registers.
466 if (!STI.isCortexA9())
469 switch (RC->getID()) {
470 case ARM::DPRRegClassID:
471 case ARM::DPR_8RegClassID:
472 case ARM::DPR_VFP2RegClassID:
473 case ARM::QPRRegClassID:
474 case ARM::QPR_8RegClassID:
475 case ARM::QPR_VFP2RegClassID:
476 case ARM::SPRRegClassID:
477 case ARM::SPR_8RegClassID:
478 // Avoid reusing S, D, and Q registers.
479 // Don't increase register pressure for QQ and QQQQ.
486 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
487 const MachineFrameInfo *MFI = MF.getFrameInfo();
488 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
489 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
491 if (!EnableBasePointer)
494 // When outgoing call frames are so large that we adjust the stack pointer
495 // around the call, we can no longer use the stack pointer to reach the
496 // emergency spill slot.
497 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
500 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
501 // negative range for ldr/str (255), and thumb1 is positive offsets only.
502 // It's going to be better to use the SP or Base Pointer instead. When there
503 // are variable sized objects, we can't reference off of the SP, so we
504 // reserve a Base Pointer.
505 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
506 // Conservatively estimate whether the negative offset from the frame
507 // pointer will be sufficient to reach. If a function has a smallish
508 // frame, it's less likely to have lots of spills and callee saved
509 // space, so it's all more likely to be within range of the frame pointer.
510 // If it's wrong, the scavenger will still enable access to work, it just
512 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
520 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
521 const MachineRegisterInfo *MRI = &MF.getRegInfo();
522 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
523 // We can't realign the stack if:
524 // 1. Dynamic stack realignment is explicitly disabled,
525 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
526 // 3. There are VLAs in the function and the base pointer is disabled.
527 if (!MF.getTarget().Options.RealignStack)
529 if (AFI->isThumb1OnlyFunction())
531 // Stack realignment requires a frame pointer. If we already started
532 // register allocation with frame pointer elimination, it is too late now.
533 if (!MRI->canReserveReg(FramePtr))
535 // We may also need a base pointer if there are dynamic allocas or stack
536 // pointer adjustments around calls.
537 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
539 if (!EnableBasePointer)
541 // A base pointer is required and allowed. Check that it isn't too late to
543 return MRI->canReserveReg(BasePtr);
546 bool ARMBaseRegisterInfo::
547 needsStackRealignment(const MachineFunction &MF) const {
548 const MachineFrameInfo *MFI = MF.getFrameInfo();
549 const Function *F = MF.getFunction();
550 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
551 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
552 F->hasFnAttr(Attribute::StackAlignment));
554 return requiresRealignment && canRealignStack(MF);
557 bool ARMBaseRegisterInfo::
558 cannotEliminateFrame(const MachineFunction &MF) const {
559 const MachineFrameInfo *MFI = MF.getFrameInfo();
560 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
562 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
563 || needsStackRealignment(MF);
567 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
568 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
575 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
576 llvm_unreachable("What is the exception register");
579 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
580 llvm_unreachable("What is the exception handler register");
583 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
584 const MachineFunction &MF) const {
587 // Return 0 if either register of the pair is a special register.
589 case ARM::R1: return ARM::R0;
590 case ARM::R3: return ARM::R2;
591 case ARM::R5: return ARM::R4;
593 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
595 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
596 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
598 case ARM::S1: return ARM::S0;
599 case ARM::S3: return ARM::S2;
600 case ARM::S5: return ARM::S4;
601 case ARM::S7: return ARM::S6;
602 case ARM::S9: return ARM::S8;
603 case ARM::S11: return ARM::S10;
604 case ARM::S13: return ARM::S12;
605 case ARM::S15: return ARM::S14;
606 case ARM::S17: return ARM::S16;
607 case ARM::S19: return ARM::S18;
608 case ARM::S21: return ARM::S20;
609 case ARM::S23: return ARM::S22;
610 case ARM::S25: return ARM::S24;
611 case ARM::S27: return ARM::S26;
612 case ARM::S29: return ARM::S28;
613 case ARM::S31: return ARM::S30;
615 case ARM::D1: return ARM::D0;
616 case ARM::D3: return ARM::D2;
617 case ARM::D5: return ARM::D4;
618 case ARM::D7: return ARM::D6;
619 case ARM::D9: return ARM::D8;
620 case ARM::D11: return ARM::D10;
621 case ARM::D13: return ARM::D12;
622 case ARM::D15: return ARM::D14;
623 case ARM::D17: return ARM::D16;
624 case ARM::D19: return ARM::D18;
625 case ARM::D21: return ARM::D20;
626 case ARM::D23: return ARM::D22;
627 case ARM::D25: return ARM::D24;
628 case ARM::D27: return ARM::D26;
629 case ARM::D29: return ARM::D28;
630 case ARM::D31: return ARM::D30;
636 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
637 const MachineFunction &MF) const {
640 // Return 0 if either register of the pair is a special register.
642 case ARM::R0: return ARM::R1;
643 case ARM::R2: return ARM::R3;
644 case ARM::R4: return ARM::R5;
646 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
648 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
649 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
651 case ARM::S0: return ARM::S1;
652 case ARM::S2: return ARM::S3;
653 case ARM::S4: return ARM::S5;
654 case ARM::S6: return ARM::S7;
655 case ARM::S8: return ARM::S9;
656 case ARM::S10: return ARM::S11;
657 case ARM::S12: return ARM::S13;
658 case ARM::S14: return ARM::S15;
659 case ARM::S16: return ARM::S17;
660 case ARM::S18: return ARM::S19;
661 case ARM::S20: return ARM::S21;
662 case ARM::S22: return ARM::S23;
663 case ARM::S24: return ARM::S25;
664 case ARM::S26: return ARM::S27;
665 case ARM::S28: return ARM::S29;
666 case ARM::S30: return ARM::S31;
668 case ARM::D0: return ARM::D1;
669 case ARM::D2: return ARM::D3;
670 case ARM::D4: return ARM::D5;
671 case ARM::D6: return ARM::D7;
672 case ARM::D8: return ARM::D9;
673 case ARM::D10: return ARM::D11;
674 case ARM::D12: return ARM::D13;
675 case ARM::D14: return ARM::D15;
676 case ARM::D16: return ARM::D17;
677 case ARM::D18: return ARM::D19;
678 case ARM::D20: return ARM::D21;
679 case ARM::D22: return ARM::D23;
680 case ARM::D24: return ARM::D25;
681 case ARM::D26: return ARM::D27;
682 case ARM::D28: return ARM::D29;
683 case ARM::D30: return ARM::D31;
689 /// emitLoadConstPool - Emits a load from constpool to materialize the
690 /// specified immediate.
691 void ARMBaseRegisterInfo::
692 emitLoadConstPool(MachineBasicBlock &MBB,
693 MachineBasicBlock::iterator &MBBI,
695 unsigned DestReg, unsigned SubIdx, int Val,
696 ARMCC::CondCodes Pred,
697 unsigned PredReg, unsigned MIFlags) const {
698 MachineFunction &MF = *MBB.getParent();
699 MachineConstantPool *ConstantPool = MF.getConstantPool();
701 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
702 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
704 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
705 .addReg(DestReg, getDefRegState(true), SubIdx)
706 .addConstantPoolIndex(Idx)
707 .addImm(0).addImm(Pred).addReg(PredReg)
708 .setMIFlags(MIFlags);
711 bool ARMBaseRegisterInfo::
712 requiresRegisterScavenging(const MachineFunction &MF) const {
716 bool ARMBaseRegisterInfo::
717 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
721 bool ARMBaseRegisterInfo::
722 requiresFrameIndexScavenging(const MachineFunction &MF) const {
726 bool ARMBaseRegisterInfo::
727 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
728 return EnableLocalStackAlloc;
732 emitSPUpdate(bool isARM,
733 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
734 DebugLoc dl, const ARMBaseInstrInfo &TII,
736 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
738 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
741 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
746 void ARMBaseRegisterInfo::
747 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
748 MachineBasicBlock::iterator I) const {
749 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
750 if (!TFI->hasReservedCallFrame(MF)) {
751 // If we have alloca, convert as follows:
752 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
753 // ADJCALLSTACKUP -> add, sp, sp, amount
754 MachineInstr *Old = I;
755 DebugLoc dl = Old->getDebugLoc();
756 unsigned Amount = Old->getOperand(0).getImm();
758 // We need to keep the stack aligned properly. To do this, we round the
759 // amount of space needed for the outgoing arguments up to the next
760 // alignment boundary.
761 unsigned Align = TFI->getStackAlignment();
762 Amount = (Amount+Align-1)/Align*Align;
764 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
765 assert(!AFI->isThumb1OnlyFunction() &&
766 "This eliminateCallFramePseudoInstr does not support Thumb1!");
767 bool isARM = !AFI->isThumbFunction();
769 // Replace the pseudo instruction with a new instruction...
770 unsigned Opc = Old->getOpcode();
771 int PIdx = Old->findFirstPredOperandIdx();
772 ARMCC::CondCodes Pred = (PIdx == -1)
773 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
774 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
775 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
776 unsigned PredReg = Old->getOperand(2).getReg();
777 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
779 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
780 unsigned PredReg = Old->getOperand(3).getReg();
781 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
782 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
789 int64_t ARMBaseRegisterInfo::
790 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
791 const MCInstrDesc &Desc = MI->getDesc();
792 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
793 int64_t InstrOffs = 0;
797 case ARMII::AddrModeT2_i8:
798 case ARMII::AddrModeT2_i12:
799 case ARMII::AddrMode_i12:
800 InstrOffs = MI->getOperand(Idx+1).getImm();
803 case ARMII::AddrMode5: {
805 const MachineOperand &OffOp = MI->getOperand(Idx+1);
806 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
807 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
808 InstrOffs = -InstrOffs;
812 case ARMII::AddrMode2: {
814 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
815 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
816 InstrOffs = -InstrOffs;
819 case ARMII::AddrMode3: {
821 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
822 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
823 InstrOffs = -InstrOffs;
826 case ARMII::AddrModeT1_s: {
828 InstrOffs = MI->getOperand(ImmIdx).getImm();
833 llvm_unreachable("Unsupported addressing mode!");
836 return InstrOffs * Scale;
839 /// needsFrameBaseReg - Returns true if the instruction's frame index
840 /// reference would be better served by a base register other than FP
841 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
842 /// references it should create new base registers for.
843 bool ARMBaseRegisterInfo::
844 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
845 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
846 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
849 // It's the load/store FI references that cause issues, as it can be difficult
850 // to materialize the offset if it won't fit in the literal field. Estimate
851 // based on the size of the local frame and some conservative assumptions
852 // about the rest of the stack frame (note, this is pre-regalloc, so
853 // we don't know everything for certain yet) whether this offset is likely
854 // to be out of range of the immediate. Return true if so.
856 // We only generate virtual base registers for loads and stores, so
857 // return false for everything else.
858 unsigned Opc = MI->getOpcode();
860 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
861 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
862 case ARM::t2LDRi12: case ARM::t2LDRi8:
863 case ARM::t2STRi12: case ARM::t2STRi8:
864 case ARM::VLDRS: case ARM::VLDRD:
865 case ARM::VSTRS: case ARM::VSTRD:
866 case ARM::tSTRspi: case ARM::tLDRspi:
867 if (ForceAllBaseRegAlloc)
874 // Without a virtual base register, if the function has variable sized
875 // objects, all fixed-size local references will be via the frame pointer,
876 // Approximate the offset and see if it's legal for the instruction.
877 // Note that the incoming offset is based on the SP value at function entry,
878 // so it'll be negative.
879 MachineFunction &MF = *MI->getParent()->getParent();
880 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
881 MachineFrameInfo *MFI = MF.getFrameInfo();
882 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
884 // Estimate an offset from the frame pointer.
885 // Conservatively assume all callee-saved registers get pushed. R4-R6
886 // will be earlier than the FP, so we ignore those.
888 int64_t FPOffset = Offset - 8;
889 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
890 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
892 // Estimate an offset from the stack pointer.
893 // The incoming offset is relating to the SP at the start of the function,
894 // but when we access the local it'll be relative to the SP after local
895 // allocation, so adjust our SP-relative offset by that allocation size.
897 Offset += MFI->getLocalFrameSize();
898 // Assume that we'll have at least some spill slots allocated.
899 // FIXME: This is a total SWAG number. We should run some statistics
900 // and pick a real one.
901 Offset += 128; // 128 bytes of spill slots
903 // If there is a frame pointer, try using it.
904 // The FP is only available if there is no dynamic realignment. We
905 // don't know for sure yet whether we'll need that, so we guess based
906 // on whether there are any local variables that would trigger it.
907 unsigned StackAlign = TFI->getStackAlignment();
908 if (TFI->hasFP(MF) &&
909 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
910 if (isFrameOffsetLegal(MI, FPOffset))
913 // If we can reference via the stack pointer, try that.
914 // FIXME: This (and the code that resolves the references) can be improved
915 // to only disallow SP relative references in the live range of
916 // the VLA(s). In practice, it's unclear how much difference that
917 // would make, but it may be worth doing.
918 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
921 // The offset likely isn't legal, we want to allocate a virtual base register.
925 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
926 /// be a pointer to FrameIdx at the beginning of the basic block.
927 void ARMBaseRegisterInfo::
928 materializeFrameBaseRegister(MachineBasicBlock *MBB,
929 unsigned BaseReg, int FrameIdx,
930 int64_t Offset) const {
931 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
932 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
933 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
935 MachineBasicBlock::iterator Ins = MBB->begin();
936 DebugLoc DL; // Defaults to "unknown"
937 if (Ins != MBB->end())
938 DL = Ins->getDebugLoc();
940 const MCInstrDesc &MCID = TII.get(ADDriOpc);
941 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
942 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
944 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
945 .addFrameIndex(FrameIdx).addImm(Offset));
947 if (!AFI->isThumb1OnlyFunction())
952 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
953 unsigned BaseReg, int64_t Offset) const {
954 MachineInstr &MI = *I;
955 MachineBasicBlock &MBB = *MI.getParent();
956 MachineFunction &MF = *MBB.getParent();
957 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
958 int Off = Offset; // ARM doesn't need the general 64-bit offsets
961 assert(!AFI->isThumb1OnlyFunction() &&
962 "This resolveFrameIndex does not support Thumb1!");
964 while (!MI.getOperand(i).isFI()) {
966 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
969 if (!AFI->isThumbFunction())
970 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
972 assert(AFI->isThumb2Function());
973 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
975 assert (Done && "Unable to resolve frame index!");
979 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
980 int64_t Offset) const {
981 const MCInstrDesc &Desc = MI->getDesc();
982 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
985 while (!MI->getOperand(i).isFI()) {
987 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
990 // AddrMode4 and AddrMode6 cannot handle any offset.
991 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
994 unsigned NumBits = 0;
996 bool isSigned = true;
998 case ARMII::AddrModeT2_i8:
999 case ARMII::AddrModeT2_i12:
1000 // i8 supports only negative, and i12 supports only positive, so
1001 // based on Offset sign, consider the appropriate instruction
1010 case ARMII::AddrMode5:
1011 // VFP address mode.
1015 case ARMII::AddrMode_i12:
1016 case ARMII::AddrMode2:
1019 case ARMII::AddrMode3:
1022 case ARMII::AddrModeT1_s:
1028 llvm_unreachable("Unsupported addressing mode!");
1031 Offset += getFrameIndexInstrOffset(MI, i);
1032 // Make sure the offset is encodable for instructions that scale the
1034 if ((Offset & (Scale-1)) != 0)
1037 if (isSigned && Offset < 0)
1040 unsigned Mask = (1 << NumBits) - 1;
1041 if ((unsigned)Offset <= Mask * Scale)
1048 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1049 int SPAdj, RegScavenger *RS) const {
1051 MachineInstr &MI = *II;
1052 MachineBasicBlock &MBB = *MI.getParent();
1053 MachineFunction &MF = *MBB.getParent();
1054 const ARMFrameLowering *TFI =
1055 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1056 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1057 assert(!AFI->isThumb1OnlyFunction() &&
1058 "This eliminateFrameIndex does not support Thumb1!");
1060 while (!MI.getOperand(i).isFI()) {
1062 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1065 int FrameIndex = MI.getOperand(i).getIndex();
1068 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1070 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
1071 // call frame setup/destroy instructions have already been eliminated. That
1072 // means the stack pointer cannot be used to access the emergency spill slot
1073 // when !hasReservedCallFrame().
1075 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1076 assert(TFI->hasReservedCallFrame(MF) &&
1077 "Cannot use SP to access the emergency spill slot in "
1078 "functions without a reserved call frame");
1079 assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
1080 "Cannot use SP to access the emergency spill slot in "
1081 "functions with variable sized frame objects");
1085 // Special handling of dbg_value instructions.
1086 if (MI.isDebugValue()) {
1087 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1088 MI.getOperand(i+1).ChangeToImmediate(Offset);
1092 // Modify MI as necessary to handle as much of 'Offset' as possible
1094 if (!AFI->isThumbFunction())
1095 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1097 assert(AFI->isThumb2Function());
1098 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1103 // If we get here, the immediate doesn't fit into the instruction. We folded
1104 // as much as possible above, handle the rest, providing a register that is
1107 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1108 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1109 "This code isn't needed if offset already handled!");
1111 unsigned ScratchReg = 0;
1112 int PIdx = MI.findFirstPredOperandIdx();
1113 ARMCC::CondCodes Pred = (PIdx == -1)
1114 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1115 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1117 // Must be addrmode4/6.
1118 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1120 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
1121 if (!AFI->isThumbFunction())
1122 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1123 Offset, Pred, PredReg, TII);
1125 assert(AFI->isThumb2Function());
1126 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1127 Offset, Pred, PredReg, TII);
1129 // Update the original instruction to use the scratch register.
1130 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);