1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45 cl::desc("Reuse repeated frame index values"));
50 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
58 llvm_unreachable("Unknown ARM register!");
59 case R0: case D0: case Q0: return 0;
60 case R1: case D1: case Q1: return 1;
61 case R2: case D2: case Q2: return 2;
62 case R3: case D3: case Q3: return 3;
63 case R4: case D4: case Q4: return 4;
64 case R5: case D5: case Q5: return 5;
65 case R6: case D6: case Q6: return 6;
66 case R7: case D7: case Q7: return 7;
67 case R8: case D8: case Q8: return 8;
68 case R9: case D9: case Q9: return 9;
69 case R10: case D10: case Q10: return 10;
70 case R11: case D11: case Q11: return 11;
71 case R12: case D12: case Q12: return 12;
72 case SP: case D13: case Q13: return 13;
73 case LR: case D14: case Q14: return 14;
74 case PC: case D15: case Q15: return 15;
93 case S0: case S1: case S2: case S3:
94 case S4: case S5: case S6: case S7:
95 case S8: case S9: case S10: case S11:
96 case S12: case S13: case S14: case S15:
97 case S16: case S17: case S18: case S19:
98 case S20: case S21: case S22: case S23:
99 case S24: case S25: case S26: case S27:
100 case S28: case S29: case S30: case S31: {
104 default: return 0; // Avoid compile time warning.
142 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143 const ARMSubtarget &sti)
144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 static const unsigned CalleeSavedRegs[] = {
152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
155 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
160 static const unsigned DarwinCalleeSavedRegs[] = {
161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
164 ARM::R11, ARM::R10, ARM::R8,
166 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
173 const TargetRegisterClass* const *
174 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
175 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
176 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
181 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
185 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
186 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
188 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
195 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
196 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198 &ARM::GPRRegClass, &ARM::GPRRegClass,
200 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
205 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
206 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass,
207 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
208 &ARM::GPRRegClass, &ARM::GPRRegClass,
210 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
215 if (STI.isThumb1Only()) {
216 return STI.isTargetDarwin()
217 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219 return STI.isTargetDarwin()
220 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
223 BitVector ARMBaseRegisterInfo::
224 getReservedRegs(const MachineFunction &MF) const {
225 // FIXME: avoid re-calculating this everytime.
226 BitVector Reserved(getNumRegs());
227 Reserved.set(ARM::SP);
228 Reserved.set(ARM::PC);
229 if (STI.isTargetDarwin() || hasFP(MF))
230 Reserved.set(FramePtr);
231 // Some targets reserve R9.
232 if (STI.isR9Reserved())
233 Reserved.set(ARM::R9);
237 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238 unsigned Reg) const {
246 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
250 return STI.isR9Reserved();
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258 const TargetRegisterClass *B,
259 unsigned SubIdx) const {
267 if (A->getSize() == 8) {
268 if (B == &ARM::SPR_8RegClass)
269 return &ARM::DPR_8RegClass;
270 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271 if (A == &ARM::DPR_8RegClass)
273 return &ARM::DPR_VFP2RegClass;
276 if (A->getSize() == 16) {
277 if (B == &ARM::SPR_8RegClass)
278 return &ARM::QPR_8RegClass;
279 return &ARM::QPR_VFP2RegClass;
282 assert(A->getSize() == 32 && "Expecting a QQ register class!");
283 if (B == &ARM::SPR_8RegClass)
284 return &ARM::QQPR_8RegClass;
285 return &ARM::QQPR_VFP2RegClass;
292 if (A->getSize() == 16) {
293 if (B == &ARM::DPR_VFP2RegClass)
294 return &ARM::QPR_VFP2RegClass;
295 if (B == &ARM::DPR_8RegClass)
296 return &ARM::QPR_8RegClass;
300 assert(A->getSize() == 32 && "Expecting a QQ register class!");
301 if (B == &ARM::DPR_VFP2RegClass)
302 return &ARM::QQPR_VFP2RegClass;
303 if (B == &ARM::DPR_8RegClass)
304 return &ARM::QQPR_8RegClass;
310 assert(A->getSize() == 32 && "Expecting a QQ register class!");
311 if (B == &ARM::QPR_VFP2RegClass)
312 return &ARM::QQPR_VFP2RegClass;
313 if (B == &ARM::QPR_8RegClass)
314 return &ARM::QQPR_8RegClass;
321 const TargetRegisterClass *
322 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
323 return ARM::GPRRegisterClass;
326 /// getAllocationOrder - Returns the register allocation order for a specified
327 /// register class in the form of a pair of TargetRegisterClass iterators.
328 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
329 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
330 unsigned HintType, unsigned HintReg,
331 const MachineFunction &MF) const {
332 // Alternative register allocation orders when favoring even / odd registers
333 // of register pairs.
335 // No FP, R9 is available.
336 static const unsigned GPREven1[] = {
337 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
338 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
341 static const unsigned GPROdd1[] = {
342 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
343 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
347 // FP is R7, R9 is available.
348 static const unsigned GPREven2[] = {
349 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
350 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
353 static const unsigned GPROdd2[] = {
354 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
355 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
359 // FP is R11, R9 is available.
360 static const unsigned GPREven3[] = {
361 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
362 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
365 static const unsigned GPROdd3[] = {
366 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
367 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
371 // No FP, R9 is not available.
372 static const unsigned GPREven4[] = {
373 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
374 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
377 static const unsigned GPROdd4[] = {
378 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
379 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
383 // FP is R7, R9 is not available.
384 static const unsigned GPREven5[] = {
385 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
386 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
389 static const unsigned GPROdd5[] = {
390 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
391 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
395 // FP is R11, R9 is not available.
396 static const unsigned GPREven6[] = {
397 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
398 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
400 static const unsigned GPROdd6[] = {
401 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
402 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
406 if (HintType == ARMRI::RegPairEven) {
407 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
408 // It's no longer possible to fulfill this hint. Return the default
410 return std::make_pair(RC->allocation_order_begin(MF),
411 RC->allocation_order_end(MF));
413 if (!STI.isTargetDarwin() && !hasFP(MF)) {
414 if (!STI.isR9Reserved())
415 return std::make_pair(GPREven1,
416 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
418 return std::make_pair(GPREven4,
419 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
420 } else if (FramePtr == ARM::R7) {
421 if (!STI.isR9Reserved())
422 return std::make_pair(GPREven2,
423 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
425 return std::make_pair(GPREven5,
426 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
427 } else { // FramePtr == ARM::R11
428 if (!STI.isR9Reserved())
429 return std::make_pair(GPREven3,
430 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
432 return std::make_pair(GPREven6,
433 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
435 } else if (HintType == ARMRI::RegPairOdd) {
436 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
437 // It's no longer possible to fulfill this hint. Return the default
439 return std::make_pair(RC->allocation_order_begin(MF),
440 RC->allocation_order_end(MF));
442 if (!STI.isTargetDarwin() && !hasFP(MF)) {
443 if (!STI.isR9Reserved())
444 return std::make_pair(GPROdd1,
445 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
447 return std::make_pair(GPROdd4,
448 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
449 } else if (FramePtr == ARM::R7) {
450 if (!STI.isR9Reserved())
451 return std::make_pair(GPROdd2,
452 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
454 return std::make_pair(GPROdd5,
455 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
456 } else { // FramePtr == ARM::R11
457 if (!STI.isR9Reserved())
458 return std::make_pair(GPROdd3,
459 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
461 return std::make_pair(GPROdd6,
462 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
465 return std::make_pair(RC->allocation_order_begin(MF),
466 RC->allocation_order_end(MF));
469 /// ResolveRegAllocHint - Resolves the specified register allocation hint
470 /// to a physical register. Returns the physical register if it is successful.
472 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
473 const MachineFunction &MF) const {
474 if (Reg == 0 || !isPhysicalRegister(Reg))
478 else if (Type == (unsigned)ARMRI::RegPairOdd)
480 return getRegisterPairOdd(Reg, MF);
481 else if (Type == (unsigned)ARMRI::RegPairEven)
483 return getRegisterPairEven(Reg, MF);
488 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
489 MachineFunction &MF) const {
490 MachineRegisterInfo *MRI = &MF.getRegInfo();
491 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
492 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
493 Hint.first == (unsigned)ARMRI::RegPairEven) &&
494 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
495 // If 'Reg' is one of the even / odd register pair and it's now changed
496 // (e.g. coalesced) into a different register. The other register of the
497 // pair allocation hint must be updated to reflect the relationship
499 unsigned OtherReg = Hint.second;
500 Hint = MRI->getRegAllocationHint(OtherReg);
501 if (Hint.second == Reg)
502 // Make sure the pair has not already divorced.
503 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
507 /// hasFP - Return true if the specified function should have a dedicated frame
508 /// pointer register. This is true if the function has variable sized allocas
509 /// or if frame pointer elimination is disabled.
511 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
512 const MachineFrameInfo *MFI = MF.getFrameInfo();
513 return ((DisableFramePointerElim(MF) && MFI->hasCalls())||
514 needsStackRealignment(MF) ||
515 MFI->hasVarSizedObjects() ||
516 MFI->isFrameAddressTaken());
519 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
520 const MachineFrameInfo *MFI = MF.getFrameInfo();
521 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
522 return (RealignStack &&
523 !AFI->isThumb1OnlyFunction() &&
524 !MFI->hasVarSizedObjects());
527 bool ARMBaseRegisterInfo::
528 needsStackRealignment(const MachineFunction &MF) const {
529 const MachineFrameInfo *MFI = MF.getFrameInfo();
530 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
531 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
532 return (RealignStack &&
533 !AFI->isThumb1OnlyFunction() &&
534 (MFI->getMaxAlignment() > StackAlign) &&
535 !MFI->hasVarSizedObjects());
538 bool ARMBaseRegisterInfo::
539 cannotEliminateFrame(const MachineFunction &MF) const {
540 const MachineFrameInfo *MFI = MF.getFrameInfo();
541 if (DisableFramePointerElim(MF) && MFI->hasCalls())
543 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
544 || needsStackRealignment(MF);
547 /// estimateStackSize - Estimate and return the size of the frame.
548 static unsigned estimateStackSize(MachineFunction &MF) {
549 const MachineFrameInfo *FFI = MF.getFrameInfo();
551 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
552 int FixedOff = -FFI->getObjectOffset(i);
553 if (FixedOff > Offset) Offset = FixedOff;
555 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
556 if (FFI->isDeadObjectIndex(i))
558 Offset += FFI->getObjectSize(i);
559 unsigned Align = FFI->getObjectAlignment(i);
560 // Adjust to alignment boundary
561 Offset = (Offset+Align-1)/Align*Align;
563 return (unsigned)Offset;
566 /// estimateRSStackSizeLimit - Look at each instruction that references stack
567 /// frames and return the stack size limit beyond which some of these
568 /// instructions will require a scratch register during their expansion later.
570 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
571 unsigned Limit = (1 << 12) - 1;
572 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
573 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
575 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
576 if (!I->getOperand(i).isFI()) continue;
578 const TargetInstrDesc &Desc = TII.get(I->getOpcode());
579 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
580 if (AddrMode == ARMII::AddrMode3 ||
581 AddrMode == ARMII::AddrModeT2_i8)
584 if (AddrMode == ARMII::AddrMode5 ||
585 AddrMode == ARMII::AddrModeT2_i8s4)
586 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
588 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
589 // When the stack offset is negative, we will end up using
590 // the i8 instructions instead.
593 if (AddrMode == ARMII::AddrMode6)
595 break; // At most one FI per instruction
604 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
605 RegScavenger *RS) const {
606 // This tells PEI to spill the FP as if it is any other callee-save register
607 // to take advantage the eliminateFrameIndex machinery. This also ensures it
608 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
609 // to combine multiple loads / stores.
610 bool CanEliminateFrame = true;
611 bool CS1Spilled = false;
612 bool LRSpilled = false;
613 unsigned NumGPRSpills = 0;
614 SmallVector<unsigned, 4> UnspilledCS1GPRs;
615 SmallVector<unsigned, 4> UnspilledCS2GPRs;
616 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
618 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
620 // FIXME: It will be better just to find spare register here.
621 if (needsStackRealignment(MF) &&
622 AFI->isThumb2Function())
623 MF.getRegInfo().setPhysRegUsed(ARM::R4);
625 // Spill LR if Thumb1 function uses variable length argument lists.
626 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
627 MF.getRegInfo().setPhysRegUsed(ARM::LR);
629 // Don't spill FP if the frame can be eliminated. This is determined
630 // by scanning the callee-save registers to see if any is used.
631 const unsigned *CSRegs = getCalleeSavedRegs();
632 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
633 for (unsigned i = 0; CSRegs[i]; ++i) {
634 unsigned Reg = CSRegs[i];
635 bool Spilled = false;
636 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
637 AFI->setCSRegisterIsSpilled(Reg);
639 CanEliminateFrame = false;
641 // Check alias registers too.
642 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
643 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
645 CanEliminateFrame = false;
650 if (CSRegClasses[i] == ARM::GPRRegisterClass ||
651 CSRegClasses[i] == ARM::tGPRRegisterClass) {
655 if (!STI.isTargetDarwin()) {
662 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
677 if (!STI.isTargetDarwin()) {
678 UnspilledCS1GPRs.push_back(Reg);
688 UnspilledCS1GPRs.push_back(Reg);
691 UnspilledCS2GPRs.push_back(Reg);
698 bool ForceLRSpill = false;
699 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
700 unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
701 // Force LR to be spilled if the Thumb function size is > 2048. This enables
702 // use of BL to implement far jump. If it turns out that it's not needed
703 // then the branch fix up path will undo it.
704 if (FnSize >= (1 << 11)) {
705 CanEliminateFrame = false;
710 // If any of the stack slot references may be out of range of an immediate
711 // offset, make sure a register (or a spill slot) is available for the
712 // register scavenger. Note that if we're indexing off the frame pointer, the
713 // effective stack size is 4 bytes larger since the FP points to the stack
714 // slot of the previous FP.
715 bool BigStack = RS &&
716 estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
718 bool ExtraCSSpill = false;
719 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
720 AFI->setHasStackFrame(true);
722 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
723 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
724 if (!LRSpilled && CS1Spilled) {
725 MF.getRegInfo().setPhysRegUsed(ARM::LR);
726 AFI->setCSRegisterIsSpilled(ARM::LR);
728 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
729 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
730 ForceLRSpill = false;
734 // Darwin ABI requires FP to point to the stack slot that contains the
736 if (STI.isTargetDarwin() || hasFP(MF)) {
737 MF.getRegInfo().setPhysRegUsed(FramePtr);
741 // If stack and double are 8-byte aligned and we are spilling an odd number
742 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
743 // the integer and double callee save areas.
744 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
745 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
746 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
747 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
748 unsigned Reg = UnspilledCS1GPRs[i];
749 // Don't spill high register if the function is thumb1
750 if (!AFI->isThumb1OnlyFunction() ||
751 isARMLowRegister(Reg) || Reg == ARM::LR) {
752 MF.getRegInfo().setPhysRegUsed(Reg);
753 AFI->setCSRegisterIsSpilled(Reg);
754 if (!isReservedReg(MF, Reg))
759 } else if (!UnspilledCS2GPRs.empty() &&
760 !AFI->isThumb1OnlyFunction()) {
761 unsigned Reg = UnspilledCS2GPRs.front();
762 MF.getRegInfo().setPhysRegUsed(Reg);
763 AFI->setCSRegisterIsSpilled(Reg);
764 if (!isReservedReg(MF, Reg))
769 // Estimate if we might need to scavenge a register at some point in order
770 // to materialize a stack offset. If so, either spill one additional
771 // callee-saved register or reserve a special spill slot to facilitate
772 // register scavenging. Thumb1 needs a spill slot for stack pointer
773 // adjustments also, even when the frame itself is small.
774 if (BigStack && !ExtraCSSpill) {
775 // If any non-reserved CS register isn't spilled, just spill one or two
776 // extra. That should take care of it!
777 unsigned NumExtras = TargetAlign / 4;
778 SmallVector<unsigned, 2> Extras;
779 while (NumExtras && !UnspilledCS1GPRs.empty()) {
780 unsigned Reg = UnspilledCS1GPRs.back();
781 UnspilledCS1GPRs.pop_back();
782 if (!isReservedReg(MF, Reg) &&
783 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
785 Extras.push_back(Reg);
789 // For non-Thumb1 functions, also check for hi-reg CS registers
790 if (!AFI->isThumb1OnlyFunction()) {
791 while (NumExtras && !UnspilledCS2GPRs.empty()) {
792 unsigned Reg = UnspilledCS2GPRs.back();
793 UnspilledCS2GPRs.pop_back();
794 if (!isReservedReg(MF, Reg)) {
795 Extras.push_back(Reg);
800 if (Extras.size() && NumExtras == 0) {
801 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
802 MF.getRegInfo().setPhysRegUsed(Extras[i]);
803 AFI->setCSRegisterIsSpilled(Extras[i]);
805 } else if (!AFI->isThumb1OnlyFunction()) {
806 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
807 // closest to SP or frame pointer.
808 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
809 MachineFrameInfo *MFI = MF.getFrameInfo();
810 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
818 MF.getRegInfo().setPhysRegUsed(ARM::LR);
819 AFI->setCSRegisterIsSpilled(ARM::LR);
820 AFI->setLRIsSpilledForFarJump(true);
824 unsigned ARMBaseRegisterInfo::getRARegister() const {
829 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
830 if (STI.isTargetDarwin() || hasFP(MF))
836 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
837 unsigned &FrameReg) const {
838 const MachineFrameInfo *MFI = MF.getFrameInfo();
839 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
840 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
841 bool isFixed = MFI->isFixedObjectIndex(FI);
844 if (AFI->isGPRCalleeSavedArea1Frame(FI))
845 Offset -= AFI->getGPRCalleeSavedArea1Offset();
846 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
847 Offset -= AFI->getGPRCalleeSavedArea2Offset();
848 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
849 Offset -= AFI->getDPRCalleeSavedAreaOffset();
850 else if (needsStackRealignment(MF)) {
851 // When dynamically realigning the stack, use the frame pointer for
852 // parameters, and the stack pointer for locals.
853 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
855 FrameReg = getFrameRegister(MF);
856 Offset -= AFI->getFramePtrSpillOffset();
858 } else if (hasFP(MF) && AFI->hasStackFrame()) {
859 if (isFixed || MFI->hasVarSizedObjects()) {
860 // Use frame pointer to reference fixed objects unless this is a
861 // frameless function.
862 FrameReg = getFrameRegister(MF);
863 Offset -= AFI->getFramePtrSpillOffset();
864 } else if (AFI->isThumb2Function()) {
865 // In Thumb2 mode, the negative offset is very limited.
866 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
867 if (FPOffset >= -255 && FPOffset < 0) {
868 FrameReg = getFrameRegister(MF);
878 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
881 return getFrameIndexReference(MF, FI, FrameReg);
884 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
885 llvm_unreachable("What is the exception register");
889 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
890 llvm_unreachable("What is the exception handler register");
894 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
895 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
898 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
899 const MachineFunction &MF) const {
902 // Return 0 if either register of the pair is a special register.
911 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6;
913 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
915 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
987 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
988 const MachineFunction &MF) const {
991 // Return 0 if either register of the pair is a special register.
1000 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7;
1002 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1004 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1076 /// emitLoadConstPool - Emits a load from constpool to materialize the
1077 /// specified immediate.
1078 void ARMBaseRegisterInfo::
1079 emitLoadConstPool(MachineBasicBlock &MBB,
1080 MachineBasicBlock::iterator &MBBI,
1082 unsigned DestReg, unsigned SubIdx, int Val,
1083 ARMCC::CondCodes Pred,
1084 unsigned PredReg) const {
1085 MachineFunction &MF = *MBB.getParent();
1086 MachineConstantPool *ConstantPool = MF.getConstantPool();
1088 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1089 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1091 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1092 .addReg(DestReg, getDefRegState(true), SubIdx)
1093 .addConstantPoolIndex(Idx)
1094 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1097 bool ARMBaseRegisterInfo::
1098 requiresRegisterScavenging(const MachineFunction &MF) const {
1102 bool ARMBaseRegisterInfo::
1103 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1107 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1108 // not required, we reserve argument space for call sites in the function
1109 // immediately on entry to the current function. This eliminates the need for
1110 // add/sub sp brackets around call sites. Returns true if the call frame is
1111 // included as part of the stack frame.
1112 bool ARMBaseRegisterInfo::
1113 hasReservedCallFrame(MachineFunction &MF) const {
1114 const MachineFrameInfo *FFI = MF.getFrameInfo();
1115 unsigned CFSize = FFI->getMaxCallFrameSize();
1116 // It's not always a good idea to include the call frame as part of the
1117 // stack frame. ARM (especially Thumb) has small immediate offset to
1118 // address the stack frame. So a large call frame can cause poor codegen
1119 // and may even makes it impossible to scavenge a register.
1120 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1123 return !MF.getFrameInfo()->hasVarSizedObjects();
1126 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1127 // call frame pseudos can be simplified. Unlike most targets, having a FP
1128 // is not sufficient here since we still may reference some objects via SP
1129 // even when FP is available in Thumb2 mode.
1130 bool ARMBaseRegisterInfo::
1131 canSimplifyCallFramePseudos(MachineFunction &MF) const {
1132 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1136 emitSPUpdate(bool isARM,
1137 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1138 DebugLoc dl, const ARMBaseInstrInfo &TII,
1140 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1142 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1143 Pred, PredReg, TII);
1145 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1146 Pred, PredReg, TII);
1150 void ARMBaseRegisterInfo::
1151 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1152 MachineBasicBlock::iterator I) const {
1153 if (!hasReservedCallFrame(MF)) {
1154 // If we have alloca, convert as follows:
1155 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1156 // ADJCALLSTACKUP -> add, sp, sp, amount
1157 MachineInstr *Old = I;
1158 DebugLoc dl = Old->getDebugLoc();
1159 unsigned Amount = Old->getOperand(0).getImm();
1161 // We need to keep the stack aligned properly. To do this, we round the
1162 // amount of space needed for the outgoing arguments up to the next
1163 // alignment boundary.
1164 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1165 Amount = (Amount+Align-1)/Align*Align;
1167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1168 assert(!AFI->isThumb1OnlyFunction() &&
1169 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1170 bool isARM = !AFI->isThumbFunction();
1172 // Replace the pseudo instruction with a new instruction...
1173 unsigned Opc = Old->getOpcode();
1174 int PIdx = Old->findFirstPredOperandIdx();
1175 ARMCC::CondCodes Pred = (PIdx == -1)
1176 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1177 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1178 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1179 unsigned PredReg = Old->getOperand(2).getReg();
1180 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1182 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1183 unsigned PredReg = Old->getOperand(3).getReg();
1184 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1185 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1193 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1194 int SPAdj, FrameIndexValue *Value,
1195 RegScavenger *RS) const {
1197 MachineInstr &MI = *II;
1198 MachineBasicBlock &MBB = *MI.getParent();
1199 MachineFunction &MF = *MBB.getParent();
1200 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1201 assert(!AFI->isThumb1OnlyFunction() &&
1202 "This eliminateFrameIndex does not support Thumb1!");
1204 while (!MI.getOperand(i).isFI()) {
1206 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1209 int FrameIndex = MI.getOperand(i).getIndex();
1212 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1213 if (FrameReg != ARM::SP)
1217 // Special handling of dbg_value instructions.
1218 if (MI.isDebugValue()) {
1219 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1220 MI.getOperand(i+1).ChangeToImmediate(Offset);
1224 // Modify MI as necessary to handle as much of 'Offset' as possible
1226 if (!AFI->isThumbFunction())
1227 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1229 assert(AFI->isThumb2Function());
1230 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1235 // If we get here, the immediate doesn't fit into the instruction. We folded
1236 // as much as possible above, handle the rest, providing a register that is
1239 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1240 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1241 "This code isn't needed if offset already handled!");
1243 unsigned ScratchReg = 0;
1244 int PIdx = MI.findFirstPredOperandIdx();
1245 ARMCC::CondCodes Pred = (PIdx == -1)
1246 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1247 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1249 // Must be addrmode4/6.
1250 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1252 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1254 Value->first = FrameReg; // use the frame register as a kind indicator
1255 Value->second = Offset;
1257 if (!AFI->isThumbFunction())
1258 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1259 Offset, Pred, PredReg, TII);
1261 assert(AFI->isThumb2Function());
1262 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1263 Offset, Pred, PredReg, TII);
1265 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1266 if (!ReuseFrameIndexVals)
1272 /// Move iterator past the next bunch of callee save load / store ops for
1273 /// the particular spill area (1: integer area 1, 2: integer area 2,
1274 /// 3: fp area, 0: don't care).
1275 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1276 MachineBasicBlock::iterator &MBBI,
1277 int Opc1, int Opc2, unsigned Area,
1278 const ARMSubtarget &STI) {
1279 while (MBBI != MBB.end() &&
1280 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1281 MBBI->getOperand(1).isFI()) {
1284 unsigned Category = 0;
1285 switch (MBBI->getOperand(0).getReg()) {
1286 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1290 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1291 Category = STI.isTargetDarwin() ? 2 : 1;
1293 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1294 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1301 if (Done || Category != Area)
1309 void ARMBaseRegisterInfo::
1310 emitPrologue(MachineFunction &MF) const {
1311 MachineBasicBlock &MBB = MF.front();
1312 MachineBasicBlock::iterator MBBI = MBB.begin();
1313 MachineFrameInfo *MFI = MF.getFrameInfo();
1314 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1315 assert(!AFI->isThumb1OnlyFunction() &&
1316 "This emitPrologue does not support Thumb1!");
1317 bool isARM = !AFI->isThumbFunction();
1318 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1319 unsigned NumBytes = MFI->getStackSize();
1320 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1321 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1323 // Determine the sizes of each callee-save spill areas and record which frame
1324 // belongs to which callee-save spill areas.
1325 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1326 int FramePtrSpillFI = 0;
1328 // Allocate the vararg register save area. This is not counted in NumBytes.
1330 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1332 if (!AFI->hasStackFrame()) {
1334 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1338 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1339 unsigned Reg = CSI[i].getReg();
1340 int FI = CSI[i].getFrameIdx();
1347 if (Reg == FramePtr)
1348 FramePtrSpillFI = FI;
1349 AFI->addGPRCalleeSavedArea1Frame(FI);
1356 if (Reg == FramePtr)
1357 FramePtrSpillFI = FI;
1358 if (STI.isTargetDarwin()) {
1359 AFI->addGPRCalleeSavedArea2Frame(FI);
1362 AFI->addGPRCalleeSavedArea1Frame(FI);
1367 AFI->addDPRCalleeSavedAreaFrame(FI);
1372 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1373 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1374 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1376 // Set FP to point to the stack slot that contains the previous FP.
1377 // For Darwin, FP is R7, which has now been stored in spill area 1.
1378 // Otherwise, if this is not Darwin, all the callee-saved registers go
1379 // into spill area 1, including the FP in R11. In either case, it is
1380 // now safe to emit this assignment.
1381 if (STI.isTargetDarwin() || hasFP(MF)) {
1382 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1383 MachineInstrBuilder MIB =
1384 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1385 .addFrameIndex(FramePtrSpillFI).addImm(0);
1386 AddDefaultCC(AddDefaultPred(MIB));
1389 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1390 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1392 // Build the new SUBri to adjust SP for FP callee-save spill area.
1393 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1394 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1396 // Determine starting offsets of spill areas.
1397 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1398 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1399 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1400 if (STI.isTargetDarwin() || hasFP(MF))
1401 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1403 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1404 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1405 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1407 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1408 NumBytes = DPRCSOffset;
1410 // Adjust SP after all the callee-save spills.
1411 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1414 if (STI.isTargetELF() && hasFP(MF)) {
1415 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1416 AFI->getFramePtrSpillOffset());
1419 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1420 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1421 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1423 // If we need dynamic stack realignment, do it here.
1424 if (needsStackRealignment(MF)) {
1425 unsigned MaxAlign = MFI->getMaxAlignment();
1426 assert (!AFI->isThumb1OnlyFunction());
1427 if (!AFI->isThumbFunction()) {
1428 // Emit bic sp, sp, MaxAlign
1429 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1430 TII.get(ARM::BICri), ARM::SP)
1431 .addReg(ARM::SP, RegState::Kill)
1432 .addImm(MaxAlign-1)));
1434 // We cannot use sp as source/dest register here, thus we're emitting the
1435 // following sequence:
1437 // bic r4, r4, MaxAlign
1439 // FIXME: It will be better just to find spare register here.
1440 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1441 .addReg(ARM::SP, RegState::Kill);
1442 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1443 TII.get(ARM::t2BICri), ARM::R4)
1444 .addReg(ARM::R4, RegState::Kill)
1445 .addImm(MaxAlign-1)));
1446 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1447 .addReg(ARM::R4, RegState::Kill);
1452 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1453 for (unsigned i = 0; CSRegs[i]; ++i)
1454 if (Reg == CSRegs[i])
1459 static bool isCSRestore(MachineInstr *MI,
1460 const ARMBaseInstrInfo &TII,
1461 const unsigned *CSRegs) {
1462 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1463 MI->getOpcode() == (int)ARM::LDR ||
1464 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1465 MI->getOperand(1).isFI() &&
1466 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1469 void ARMBaseRegisterInfo::
1470 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1471 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1472 assert(MBBI->getDesc().isReturn() &&
1473 "Can only insert epilog into returning blocks");
1474 DebugLoc dl = MBBI->getDebugLoc();
1475 MachineFrameInfo *MFI = MF.getFrameInfo();
1476 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1477 assert(!AFI->isThumb1OnlyFunction() &&
1478 "This emitEpilogue does not support Thumb1!");
1479 bool isARM = !AFI->isThumbFunction();
1481 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1482 int NumBytes = (int)MFI->getStackSize();
1484 if (!AFI->hasStackFrame()) {
1486 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1488 // Unwind MBBI to point to first LDR / VLDRD.
1489 const unsigned *CSRegs = getCalleeSavedRegs();
1490 if (MBBI != MBB.begin()) {
1493 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1494 if (!isCSRestore(MBBI, TII, CSRegs))
1498 // Move SP to start of FP callee save spill area.
1499 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1500 AFI->getGPRCalleeSavedArea2Size() +
1501 AFI->getDPRCalleeSavedAreaSize());
1503 // Darwin ABI requires FP to point to the stack slot that contains the
1505 bool HasFP = hasFP(MF);
1506 if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1507 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1508 // Reset SP based on frame pointer only if the stack frame extends beyond
1509 // frame pointer stack slot or target is ELF and the function has FP.
1511 AFI->getGPRCalleeSavedArea2Size() ||
1512 AFI->getDPRCalleeSavedAreaSize() ||
1513 AFI->getDPRCalleeSavedAreaOffset()) {
1516 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1519 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1524 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1526 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1528 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1532 } else if (NumBytes)
1533 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1535 // Move SP to start of integer callee save spill area 2.
1536 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1537 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1539 // Move SP to start of integer callee save spill area 1.
1540 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1541 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1543 // Move SP to SP upon entry to the function.
1544 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1545 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1549 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1552 #include "ARMGenRegisterInfo.inc"