1 //===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/Support/CommandLine.h"
44 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45 cl::desc("Force use of virtual base registers for stack load/store"));
47 EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48 cl::desc("Enable pre-regalloc stack frame index allocation"));
54 EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
65 llvm_unreachable("Unknown ARM register!");
66 case R0: case D0: case Q0: return 0;
67 case R1: case D1: case Q1: return 1;
68 case R2: case D2: case Q2: return 2;
69 case R3: case D3: case Q3: return 3;
70 case R4: case D4: case Q4: return 4;
71 case R5: case D5: case Q5: return 5;
72 case R6: case D6: case Q6: return 6;
73 case R7: case D7: case Q7: return 7;
74 case R8: case D8: case Q8: return 8;
75 case R9: case D9: case Q9: return 9;
76 case R10: case D10: case Q10: return 10;
77 case R11: case D11: case Q11: return 11;
78 case R12: case D12: case Q12: return 12;
79 case SP: case D13: case Q13: return 13;
80 case LR: case D14: case Q14: return 14;
81 case PC: case D15: case Q15: return 15;
100 case S0: case S1: case S2: case S3:
101 case S4: case S5: case S6: case S7:
102 case S8: case S9: case S10: case S11:
103 case S12: case S13: case S14: case S15:
104 case S16: case S17: case S18: case S19:
105 case S20: case S21: case S22: case S23:
106 case S24: case S25: case S26: case S27:
107 case S28: case S29: case S30: case S31: {
111 default: return 0; // Avoid compile time warning.
149 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
150 const ARMSubtarget &sti)
151 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
153 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
158 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
159 static const unsigned CalleeSavedRegs[] = {
160 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
161 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
163 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
168 static const unsigned DarwinCalleeSavedRegs[] = {
169 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
171 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
172 ARM::R11, ARM::R10, ARM::R8,
174 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
175 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
178 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
181 BitVector ARMBaseRegisterInfo::
182 getReservedRegs(const MachineFunction &MF) const {
183 // FIXME: avoid re-calculating this everytime.
184 BitVector Reserved(getNumRegs());
185 Reserved.set(ARM::SP);
186 Reserved.set(ARM::PC);
187 Reserved.set(ARM::FPSCR);
189 Reserved.set(FramePtr);
190 if (hasBasePointer(MF))
191 Reserved.set(BasePtr);
192 // Some targets reserve R9.
193 if (STI.isR9Reserved())
194 Reserved.set(ARM::R9);
198 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
199 unsigned Reg) const {
206 if (hasBasePointer(MF))
211 if (FramePtr == Reg && hasFP(MF))
215 return STI.isR9Reserved();
221 const TargetRegisterClass *
222 ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
223 const TargetRegisterClass *B,
224 unsigned SubIdx) const {
232 if (A->getSize() == 8) {
233 if (B == &ARM::SPR_8RegClass)
234 return &ARM::DPR_8RegClass;
235 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
236 if (A == &ARM::DPR_8RegClass)
238 return &ARM::DPR_VFP2RegClass;
241 if (A->getSize() == 16) {
242 if (B == &ARM::SPR_8RegClass)
243 return &ARM::QPR_8RegClass;
244 return &ARM::QPR_VFP2RegClass;
247 if (A->getSize() == 32) {
248 if (B == &ARM::SPR_8RegClass)
249 return 0; // Do not allow coalescing!
250 return &ARM::QQPR_VFP2RegClass;
253 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
254 return 0; // Do not allow coalescing!
261 if (A->getSize() == 16) {
262 if (B == &ARM::DPR_VFP2RegClass)
263 return &ARM::QPR_VFP2RegClass;
264 if (B == &ARM::DPR_8RegClass)
265 return 0; // Do not allow coalescing!
269 if (A->getSize() == 32) {
270 if (B == &ARM::DPR_VFP2RegClass)
271 return &ARM::QQPR_VFP2RegClass;
272 if (B == &ARM::DPR_8RegClass)
273 return 0; // Do not allow coalescing!
277 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
278 if (B != &ARM::DPRRegClass)
279 return 0; // Do not allow coalescing!
286 // D sub-registers of QQQQ registers.
287 if (A->getSize() == 64 && B == &ARM::DPRRegClass)
289 return 0; // Do not allow coalescing!
295 if (A->getSize() == 32) {
296 if (B == &ARM::QPR_VFP2RegClass)
297 return &ARM::QQPR_VFP2RegClass;
298 if (B == &ARM::QPR_8RegClass)
299 return 0; // Do not allow coalescing!
303 assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
304 if (B == &ARM::QPRRegClass)
306 return 0; // Do not allow coalescing!
310 // Q sub-registers of QQQQ registers.
311 if (A->getSize() == 64 && B == &ARM::QPRRegClass)
313 return 0; // Do not allow coalescing!
320 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
321 SmallVectorImpl<unsigned> &SubIndices,
322 unsigned &NewSubIdx) const {
324 unsigned Size = RC->getSize() * 8;
328 NewSubIdx = 0; // Whole register.
329 unsigned NumRegs = SubIndices.size();
331 // 8 D registers -> 1 QQQQ register.
332 return (Size == 512 &&
333 SubIndices[0] == ARM::dsub_0 &&
334 SubIndices[1] == ARM::dsub_1 &&
335 SubIndices[2] == ARM::dsub_2 &&
336 SubIndices[3] == ARM::dsub_3 &&
337 SubIndices[4] == ARM::dsub_4 &&
338 SubIndices[5] == ARM::dsub_5 &&
339 SubIndices[6] == ARM::dsub_6 &&
340 SubIndices[7] == ARM::dsub_7);
341 } else if (NumRegs == 4) {
342 if (SubIndices[0] == ARM::qsub_0) {
343 // 4 Q registers -> 1 QQQQ register.
344 return (Size == 512 &&
345 SubIndices[1] == ARM::qsub_1 &&
346 SubIndices[2] == ARM::qsub_2 &&
347 SubIndices[3] == ARM::qsub_3);
348 } else if (SubIndices[0] == ARM::dsub_0) {
349 // 4 D registers -> 1 QQ register.
351 SubIndices[1] == ARM::dsub_1 &&
352 SubIndices[2] == ARM::dsub_2 &&
353 SubIndices[3] == ARM::dsub_3) {
355 NewSubIdx = ARM::qqsub_0;
358 } else if (SubIndices[0] == ARM::dsub_4) {
359 // 4 D registers -> 1 QQ register (2nd).
361 SubIndices[1] == ARM::dsub_5 &&
362 SubIndices[2] == ARM::dsub_6 &&
363 SubIndices[3] == ARM::dsub_7) {
364 NewSubIdx = ARM::qqsub_1;
367 } else if (SubIndices[0] == ARM::ssub_0) {
368 // 4 S registers -> 1 Q register.
370 SubIndices[1] == ARM::ssub_1 &&
371 SubIndices[2] == ARM::ssub_2 &&
372 SubIndices[3] == ARM::ssub_3) {
374 NewSubIdx = ARM::qsub_0;
378 } else if (NumRegs == 2) {
379 if (SubIndices[0] == ARM::qsub_0) {
380 // 2 Q registers -> 1 QQ register.
381 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
383 NewSubIdx = ARM::qqsub_0;
386 } else if (SubIndices[0] == ARM::qsub_2) {
387 // 2 Q registers -> 1 QQ register (2nd).
388 if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
389 NewSubIdx = ARM::qqsub_1;
392 } else if (SubIndices[0] == ARM::dsub_0) {
393 // 2 D registers -> 1 Q register.
394 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
396 NewSubIdx = ARM::qsub_0;
399 } else if (SubIndices[0] == ARM::dsub_2) {
400 // 2 D registers -> 1 Q register (2nd).
401 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
402 NewSubIdx = ARM::qsub_1;
405 } else if (SubIndices[0] == ARM::dsub_4) {
406 // 2 D registers -> 1 Q register (3rd).
407 if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
408 NewSubIdx = ARM::qsub_2;
411 } else if (SubIndices[0] == ARM::dsub_6) {
412 // 2 D registers -> 1 Q register (3rd).
413 if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
414 NewSubIdx = ARM::qsub_3;
417 } else if (SubIndices[0] == ARM::ssub_0) {
418 // 2 S registers -> 1 D register.
419 if (SubIndices[1] == ARM::ssub_1) {
421 NewSubIdx = ARM::dsub_0;
424 } else if (SubIndices[0] == ARM::ssub_2) {
425 // 2 S registers -> 1 D register (2nd).
426 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
427 NewSubIdx = ARM::dsub_1;
436 const TargetRegisterClass *
437 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
438 return ARM::GPRRegisterClass;
441 /// getAllocationOrder - Returns the register allocation order for a specified
442 /// register class in the form of a pair of TargetRegisterClass iterators.
443 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
444 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
445 unsigned HintType, unsigned HintReg,
446 const MachineFunction &MF) const {
447 // Alternative register allocation orders when favoring even / odd registers
448 // of register pairs.
450 // No FP, R9 is available.
451 static const unsigned GPREven1[] = {
452 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
453 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
456 static const unsigned GPROdd1[] = {
457 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
458 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
462 // FP is R7, R9 is available.
463 static const unsigned GPREven2[] = {
464 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
465 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
468 static const unsigned GPROdd2[] = {
469 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
470 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
474 // FP is R11, R9 is available.
475 static const unsigned GPREven3[] = {
476 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
477 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
480 static const unsigned GPROdd3[] = {
481 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
482 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
486 // No FP, R9 is not available.
487 static const unsigned GPREven4[] = {
488 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
489 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
492 static const unsigned GPROdd4[] = {
493 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
494 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
498 // FP is R7, R9 is not available.
499 static const unsigned GPREven5[] = {
500 ARM::R0, ARM::R2, ARM::R4, ARM::R10,
501 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
504 static const unsigned GPROdd5[] = {
505 ARM::R1, ARM::R3, ARM::R5, ARM::R11,
506 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
510 // FP is R11, R9 is not available.
511 static const unsigned GPREven6[] = {
512 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
513 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
515 static const unsigned GPROdd6[] = {
516 ARM::R1, ARM::R3, ARM::R5, ARM::R7,
517 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
521 if (HintType == ARMRI::RegPairEven) {
522 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
523 // It's no longer possible to fulfill this hint. Return the default
525 return std::make_pair(RC->allocation_order_begin(MF),
526 RC->allocation_order_end(MF));
529 if (!STI.isR9Reserved())
530 return std::make_pair(GPREven1,
531 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
533 return std::make_pair(GPREven4,
534 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
535 } else if (FramePtr == ARM::R7) {
536 if (!STI.isR9Reserved())
537 return std::make_pair(GPREven2,
538 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
540 return std::make_pair(GPREven5,
541 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
542 } else { // FramePtr == ARM::R11
543 if (!STI.isR9Reserved())
544 return std::make_pair(GPREven3,
545 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
547 return std::make_pair(GPREven6,
548 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
550 } else if (HintType == ARMRI::RegPairOdd) {
551 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
552 // It's no longer possible to fulfill this hint. Return the default
554 return std::make_pair(RC->allocation_order_begin(MF),
555 RC->allocation_order_end(MF));
558 if (!STI.isR9Reserved())
559 return std::make_pair(GPROdd1,
560 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
562 return std::make_pair(GPROdd4,
563 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
564 } else if (FramePtr == ARM::R7) {
565 if (!STI.isR9Reserved())
566 return std::make_pair(GPROdd2,
567 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
569 return std::make_pair(GPROdd5,
570 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
571 } else { // FramePtr == ARM::R11
572 if (!STI.isR9Reserved())
573 return std::make_pair(GPROdd3,
574 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
576 return std::make_pair(GPROdd6,
577 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
580 return std::make_pair(RC->allocation_order_begin(MF),
581 RC->allocation_order_end(MF));
584 /// ResolveRegAllocHint - Resolves the specified register allocation hint
585 /// to a physical register. Returns the physical register if it is successful.
587 ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
588 const MachineFunction &MF) const {
589 if (Reg == 0 || !isPhysicalRegister(Reg))
593 else if (Type == (unsigned)ARMRI::RegPairOdd)
595 return getRegisterPairOdd(Reg, MF);
596 else if (Type == (unsigned)ARMRI::RegPairEven)
598 return getRegisterPairEven(Reg, MF);
603 ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
604 MachineFunction &MF) const {
605 MachineRegisterInfo *MRI = &MF.getRegInfo();
606 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
607 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
608 Hint.first == (unsigned)ARMRI::RegPairEven) &&
609 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
610 // If 'Reg' is one of the even / odd register pair and it's now changed
611 // (e.g. coalesced) into a different register. The other register of the
612 // pair allocation hint must be updated to reflect the relationship
614 unsigned OtherReg = Hint.second;
615 Hint = MRI->getRegAllocationHint(OtherReg);
616 if (Hint.second == Reg)
617 // Make sure the pair has not already divorced.
618 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
622 /// hasFP - Return true if the specified function should have a dedicated frame
623 /// pointer register. This is true if the function has variable sized allocas
624 /// or if frame pointer elimination is disabled.
626 bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
627 // Mac OS X requires FP not to be clobbered for backtracing purpose.
628 if (STI.isTargetDarwin())
631 const MachineFrameInfo *MFI = MF.getFrameInfo();
632 // Always eliminate non-leaf frame pointers.
633 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
634 needsStackRealignment(MF) ||
635 MFI->hasVarSizedObjects() ||
636 MFI->isFrameAddressTaken());
639 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
640 const MachineFrameInfo *MFI = MF.getFrameInfo();
641 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
643 if (!EnableBasePointer)
646 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
649 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
650 // negative range for ldr/str (255), and thumb1 is positive offsets only.
651 // It's going to be better to use the SP or Base Pointer instead. When there
652 // are variable sized objects, we can't reference off of the SP, so we
653 // reserve a Base Pointer.
654 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
655 // Conservatively estimate whether the negative offset from the frame
656 // pointer will be sufficient to reach. If a function has a smallish
657 // frame, it's less likely to have lots of spills and callee saved
658 // space, so it's all more likely to be within range of the frame pointer.
659 // If it's wrong, the scavenger will still enable access to work, it just
661 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
669 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
670 const MachineFrameInfo *MFI = MF.getFrameInfo();
671 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
672 // We can't realign the stack if:
673 // 1. Dynamic stack realignment is explicitly disabled,
674 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
675 // 3. There are VLAs in the function and the base pointer is disabled.
676 return (RealignStack && !AFI->isThumb1OnlyFunction() &&
677 (!MFI->hasVarSizedObjects() || EnableBasePointer));
680 bool ARMBaseRegisterInfo::
681 needsStackRealignment(const MachineFunction &MF) const {
682 const MachineFrameInfo *MFI = MF.getFrameInfo();
683 const Function *F = MF.getFunction();
684 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
685 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
686 F->hasFnAttr(Attribute::StackAlignment));
688 return requiresRealignment && canRealignStack(MF);
691 bool ARMBaseRegisterInfo::
692 cannotEliminateFrame(const MachineFunction &MF) const {
693 const MachineFrameInfo *MFI = MF.getFrameInfo();
694 if (DisableFramePointerElim(MF) && MFI->adjustsStack())
696 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
697 || needsStackRealignment(MF);
700 /// estimateStackSize - Estimate and return the size of the frame.
701 static unsigned estimateStackSize(MachineFunction &MF) {
702 const MachineFrameInfo *FFI = MF.getFrameInfo();
704 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
705 int FixedOff = -FFI->getObjectOffset(i);
706 if (FixedOff > Offset) Offset = FixedOff;
708 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
709 if (FFI->isDeadObjectIndex(i))
711 Offset += FFI->getObjectSize(i);
712 unsigned Align = FFI->getObjectAlignment(i);
713 // Adjust to alignment boundary
714 Offset = (Offset+Align-1)/Align*Align;
716 return (unsigned)Offset;
719 /// estimateRSStackSizeLimit - Look at each instruction that references stack
720 /// frames and return the stack size limit beyond which some of these
721 /// instructions will require a scratch register during their expansion later.
723 ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
724 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
725 unsigned Limit = (1 << 12) - 1;
726 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
727 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
729 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
730 if (!I->getOperand(i).isFI()) continue;
732 // When using ADDri to get the address of a stack object, 255 is the
733 // largest offset guaranteed to fit in the immediate offset.
734 if (I->getOpcode() == ARM::ADDri) {
735 Limit = std::min(Limit, (1U << 8) - 1);
739 // Otherwise check the addressing mode.
740 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
741 case ARMII::AddrMode3:
742 case ARMII::AddrModeT2_i8:
743 Limit = std::min(Limit, (1U << 8) - 1);
745 case ARMII::AddrMode5:
746 case ARMII::AddrModeT2_i8s4:
747 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
749 case ARMII::AddrModeT2_i12:
750 // i12 supports only positive offset so these will be converted to
751 // i8 opcodes. See llvm::rewriteT2FrameIndex.
752 if (hasFP(MF) && AFI->hasStackFrame())
753 Limit = std::min(Limit, (1U << 8) - 1);
755 case ARMII::AddrMode6:
756 // Addressing mode 6 (load/store) instructions can't encode an
757 // immediate offset for stack references.
762 break; // At most one FI per instruction
770 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
771 const ARMBaseInstrInfo &TII) {
773 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
775 const MachineBasicBlock &MBB = *MBBI;
776 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
778 FnSize += TII.GetInstSizeInBytes(I);
784 ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
785 RegScavenger *RS) const {
786 // This tells PEI to spill the FP as if it is any other callee-save register
787 // to take advantage the eliminateFrameIndex machinery. This also ensures it
788 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
789 // to combine multiple loads / stores.
790 bool CanEliminateFrame = true;
791 bool CS1Spilled = false;
792 bool LRSpilled = false;
793 unsigned NumGPRSpills = 0;
794 SmallVector<unsigned, 4> UnspilledCS1GPRs;
795 SmallVector<unsigned, 4> UnspilledCS2GPRs;
796 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
797 MachineFrameInfo *MFI = MF.getFrameInfo();
799 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
801 // FIXME: It will be better just to find spare register here.
802 if (needsStackRealignment(MF) &&
803 AFI->isThumb2Function())
804 MF.getRegInfo().setPhysRegUsed(ARM::R4);
806 // Spill LR if Thumb1 function uses variable length argument lists.
807 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
808 MF.getRegInfo().setPhysRegUsed(ARM::LR);
810 // Spill the BasePtr if it's used.
811 if (hasBasePointer(MF))
812 MF.getRegInfo().setPhysRegUsed(BasePtr);
814 // Don't spill FP if the frame can be eliminated. This is determined
815 // by scanning the callee-save registers to see if any is used.
816 const unsigned *CSRegs = getCalleeSavedRegs();
817 for (unsigned i = 0; CSRegs[i]; ++i) {
818 unsigned Reg = CSRegs[i];
819 bool Spilled = false;
820 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
821 AFI->setCSRegisterIsSpilled(Reg);
823 CanEliminateFrame = false;
825 // Check alias registers too.
826 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
827 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
829 CanEliminateFrame = false;
834 if (!ARM::GPRRegisterClass->contains(Reg))
840 if (!STI.isTargetDarwin()) {
847 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
862 if (!STI.isTargetDarwin()) {
863 UnspilledCS1GPRs.push_back(Reg);
873 UnspilledCS1GPRs.push_back(Reg);
876 UnspilledCS2GPRs.push_back(Reg);
882 bool ForceLRSpill = false;
883 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
884 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
885 // Force LR to be spilled if the Thumb function size is > 2048. This enables
886 // use of BL to implement far jump. If it turns out that it's not needed
887 // then the branch fix up path will undo it.
888 if (FnSize >= (1 << 11)) {
889 CanEliminateFrame = false;
894 // If any of the stack slot references may be out of range of an immediate
895 // offset, make sure a register (or a spill slot) is available for the
896 // register scavenger. Note that if we're indexing off the frame pointer, the
897 // effective stack size is 4 bytes larger since the FP points to the stack
898 // slot of the previous FP. Also, if we have variable sized objects in the
899 // function, stack slot references will often be negative, and some of
900 // our instructions are positive-offset only, so conservatively consider
901 // that case to want a spill slot (or register) as well. Similarly, if
902 // the function adjusts the stack pointer during execution and the
903 // adjustments aren't already part of our stack size estimate, our offset
904 // calculations may be off, so be conservative.
905 // FIXME: We could add logic to be more precise about negative offsets
906 // and which instructions will need a scratch register for them. Is it
907 // worth the effort and added fragility?
910 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
911 estimateRSStackSizeLimit(MF)))
912 || MFI->hasVarSizedObjects()
913 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
915 bool ExtraCSSpill = false;
916 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
917 AFI->setHasStackFrame(true);
919 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
920 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
921 if (!LRSpilled && CS1Spilled) {
922 MF.getRegInfo().setPhysRegUsed(ARM::LR);
923 AFI->setCSRegisterIsSpilled(ARM::LR);
925 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
926 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
927 ForceLRSpill = false;
932 MF.getRegInfo().setPhysRegUsed(FramePtr);
936 // If stack and double are 8-byte aligned and we are spilling an odd number
937 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
938 // the integer and double callee save areas.
939 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
940 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
941 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
942 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
943 unsigned Reg = UnspilledCS1GPRs[i];
944 // Don't spill high register if the function is thumb1
945 if (!AFI->isThumb1OnlyFunction() ||
946 isARMLowRegister(Reg) || Reg == ARM::LR) {
947 MF.getRegInfo().setPhysRegUsed(Reg);
948 AFI->setCSRegisterIsSpilled(Reg);
949 if (!isReservedReg(MF, Reg))
954 } else if (!UnspilledCS2GPRs.empty() &&
955 !AFI->isThumb1OnlyFunction()) {
956 unsigned Reg = UnspilledCS2GPRs.front();
957 MF.getRegInfo().setPhysRegUsed(Reg);
958 AFI->setCSRegisterIsSpilled(Reg);
959 if (!isReservedReg(MF, Reg))
964 // Estimate if we might need to scavenge a register at some point in order
965 // to materialize a stack offset. If so, either spill one additional
966 // callee-saved register or reserve a special spill slot to facilitate
967 // register scavenging. Thumb1 needs a spill slot for stack pointer
968 // adjustments also, even when the frame itself is small.
969 if (BigStack && !ExtraCSSpill) {
970 // If any non-reserved CS register isn't spilled, just spill one or two
971 // extra. That should take care of it!
972 unsigned NumExtras = TargetAlign / 4;
973 SmallVector<unsigned, 2> Extras;
974 while (NumExtras && !UnspilledCS1GPRs.empty()) {
975 unsigned Reg = UnspilledCS1GPRs.back();
976 UnspilledCS1GPRs.pop_back();
977 if (!isReservedReg(MF, Reg) &&
978 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
980 Extras.push_back(Reg);
984 // For non-Thumb1 functions, also check for hi-reg CS registers
985 if (!AFI->isThumb1OnlyFunction()) {
986 while (NumExtras && !UnspilledCS2GPRs.empty()) {
987 unsigned Reg = UnspilledCS2GPRs.back();
988 UnspilledCS2GPRs.pop_back();
989 if (!isReservedReg(MF, Reg)) {
990 Extras.push_back(Reg);
995 if (Extras.size() && NumExtras == 0) {
996 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
997 MF.getRegInfo().setPhysRegUsed(Extras[i]);
998 AFI->setCSRegisterIsSpilled(Extras[i]);
1000 } else if (!AFI->isThumb1OnlyFunction()) {
1001 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
1002 // closest to SP or frame pointer.
1003 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
1004 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1012 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1013 AFI->setCSRegisterIsSpilled(ARM::LR);
1014 AFI->setLRIsSpilledForFarJump(true);
1018 unsigned ARMBaseRegisterInfo::getRARegister() const {
1023 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1029 // Provide a base+offset reference to an FI slot for debug info. It's the
1030 // same as what we use for resolving the code-gen references for now.
1031 // FIXME: This can go wrong when references are SP-relative and simple call
1032 // frames aren't used.
1034 ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
1035 unsigned &FrameReg) const {
1036 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
1040 ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
1044 const MachineFrameInfo *MFI = MF.getFrameInfo();
1045 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1046 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1047 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1048 bool isFixed = MFI->isFixedObjectIndex(FI);
1052 if (AFI->isGPRCalleeSavedArea1Frame(FI))
1053 return Offset - AFI->getGPRCalleeSavedArea1Offset();
1054 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1055 return Offset - AFI->getGPRCalleeSavedArea2Offset();
1056 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1057 return Offset - AFI->getDPRCalleeSavedAreaOffset();
1059 // When dynamically realigning the stack, use the frame pointer for
1060 // parameters, and the stack/base pointer for locals.
1061 if (needsStackRealignment(MF)) {
1062 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1064 FrameReg = getFrameRegister(MF);
1066 } else if (MFI->hasVarSizedObjects()) {
1067 assert(hasBasePointer(MF) &&
1068 "VLAs and dynamic stack alignment, but missing base pointer!");
1074 // If there is a frame pointer, use it when we can.
1075 if (hasFP(MF) && AFI->hasStackFrame()) {
1076 // Use frame pointer to reference fixed objects. Use it for locals if
1077 // there are VLAs (and thus the SP isn't reliable as a base).
1078 if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
1079 FrameReg = getFrameRegister(MF);
1081 } else if (MFI->hasVarSizedObjects()) {
1082 assert(hasBasePointer(MF) && "missing base pointer!");
1083 // Use the base register since we have it.
1085 } else if (AFI->isThumb2Function()) {
1086 // In Thumb2 mode, the negative offset is very limited. Try to avoid
1087 // out of range references.
1088 if (FPOffset >= -255 && FPOffset < 0) {
1089 FrameReg = getFrameRegister(MF);
1092 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1093 // Otherwise, use SP or FP, whichever is closer to the stack slot.
1094 FrameReg = getFrameRegister(MF);
1098 // Use the base pointer if we have one.
1099 if (hasBasePointer(MF))
1105 ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1108 return getFrameIndexReference(MF, FI, FrameReg);
1111 unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1112 llvm_unreachable("What is the exception register");
1116 unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1117 llvm_unreachable("What is the exception handler register");
1121 int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1122 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1125 unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1126 const MachineFunction &MF) const {
1129 // Return 0 if either register of the pair is a special register.
1138 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1141 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
1143 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1215 unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1216 const MachineFunction &MF) const {
1219 // Return 0 if either register of the pair is a special register.
1228 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1231 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
1233 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1305 /// emitLoadConstPool - Emits a load from constpool to materialize the
1306 /// specified immediate.
1307 void ARMBaseRegisterInfo::
1308 emitLoadConstPool(MachineBasicBlock &MBB,
1309 MachineBasicBlock::iterator &MBBI,
1311 unsigned DestReg, unsigned SubIdx, int Val,
1312 ARMCC::CondCodes Pred,
1313 unsigned PredReg) const {
1314 MachineFunction &MF = *MBB.getParent();
1315 MachineConstantPool *ConstantPool = MF.getConstantPool();
1317 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1318 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1320 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1321 .addReg(DestReg, getDefRegState(true), SubIdx)
1322 .addConstantPoolIndex(Idx)
1323 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1326 bool ARMBaseRegisterInfo::
1327 requiresRegisterScavenging(const MachineFunction &MF) const {
1331 bool ARMBaseRegisterInfo::
1332 requiresFrameIndexScavenging(const MachineFunction &MF) const {
1336 bool ARMBaseRegisterInfo::
1337 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1338 return EnableLocalStackAlloc;
1341 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1342 // not required, we reserve argument space for call sites in the function
1343 // immediately on entry to the current function. This eliminates the need for
1344 // add/sub sp brackets around call sites. Returns true if the call frame is
1345 // included as part of the stack frame.
1346 bool ARMBaseRegisterInfo::
1347 hasReservedCallFrame(const MachineFunction &MF) const {
1348 const MachineFrameInfo *FFI = MF.getFrameInfo();
1349 unsigned CFSize = FFI->getMaxCallFrameSize();
1350 // It's not always a good idea to include the call frame as part of the
1351 // stack frame. ARM (especially Thumb) has small immediate offset to
1352 // address the stack frame. So a large call frame can cause poor codegen
1353 // and may even makes it impossible to scavenge a register.
1354 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
1357 return !MF.getFrameInfo()->hasVarSizedObjects();
1360 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
1361 // call frame pseudos can be simplified. Unlike most targets, having a FP
1362 // is not sufficient here since we still may reference some objects via SP
1363 // even when FP is available in Thumb2 mode.
1364 bool ARMBaseRegisterInfo::
1365 canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1366 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1370 emitSPUpdate(bool isARM,
1371 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1372 DebugLoc dl, const ARMBaseInstrInfo &TII,
1374 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1376 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1377 Pred, PredReg, TII);
1379 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1380 Pred, PredReg, TII);
1384 void ARMBaseRegisterInfo::
1385 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1386 MachineBasicBlock::iterator I) const {
1387 if (!hasReservedCallFrame(MF)) {
1388 // If we have alloca, convert as follows:
1389 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1390 // ADJCALLSTACKUP -> add, sp, sp, amount
1391 MachineInstr *Old = I;
1392 DebugLoc dl = Old->getDebugLoc();
1393 unsigned Amount = Old->getOperand(0).getImm();
1395 // We need to keep the stack aligned properly. To do this, we round the
1396 // amount of space needed for the outgoing arguments up to the next
1397 // alignment boundary.
1398 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1399 Amount = (Amount+Align-1)/Align*Align;
1401 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1402 assert(!AFI->isThumb1OnlyFunction() &&
1403 "This eliminateCallFramePseudoInstr does not support Thumb1!");
1404 bool isARM = !AFI->isThumbFunction();
1406 // Replace the pseudo instruction with a new instruction...
1407 unsigned Opc = Old->getOpcode();
1408 int PIdx = Old->findFirstPredOperandIdx();
1409 ARMCC::CondCodes Pred = (PIdx == -1)
1410 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1411 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1412 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1413 unsigned PredReg = Old->getOperand(2).getReg();
1414 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1416 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1417 unsigned PredReg = Old->getOperand(3).getReg();
1418 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1419 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1426 int64_t ARMBaseRegisterInfo::
1427 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1428 const TargetInstrDesc &Desc = MI->getDesc();
1429 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1430 int64_t InstrOffs = 0;;
1432 unsigned ImmIdx = 0;
1434 case ARMII::AddrModeT2_i8:
1435 case ARMII::AddrModeT2_i12:
1436 // i8 supports only negative, and i12 supports only positive, so
1437 // based on Offset sign, consider the appropriate instruction
1438 InstrOffs = MI->getOperand(Idx+1).getImm();
1441 case ARMII::AddrMode5: {
1442 // VFP address mode.
1443 const MachineOperand &OffOp = MI->getOperand(Idx+1);
1444 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1445 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1446 InstrOffs = -InstrOffs;
1450 case ARMII::AddrMode2: {
1452 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1453 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1454 InstrOffs = -InstrOffs;
1457 case ARMII::AddrMode3: {
1459 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1460 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1461 InstrOffs = -InstrOffs;
1464 case ARMII::AddrModeT1_s: {
1466 InstrOffs = MI->getOperand(ImmIdx).getImm();
1471 llvm_unreachable("Unsupported addressing mode!");
1475 return InstrOffs * Scale;
1478 /// needsFrameBaseReg - Returns true if the instruction's frame index
1479 /// reference would be better served by a base register other than FP
1480 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1481 /// references it should create new base registers for.
1482 bool ARMBaseRegisterInfo::
1483 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1484 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1485 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1488 // It's the load/store FI references that cause issues, as it can be difficult
1489 // to materialize the offset if it won't fit in the literal field. Estimate
1490 // based on the size of the local frame and some conservative assumptions
1491 // about the rest of the stack frame (note, this is pre-regalloc, so
1492 // we don't know everything for certain yet) whether this offset is likely
1493 // to be out of range of the immediate. Return true if so.
1495 // We only generate virtual base registers for loads and stores, so
1496 // return false for everything else.
1497 unsigned Opc = MI->getOpcode();
1499 case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1500 case ARM::STR: case ARM::STRH: case ARM::STRB:
1501 case ARM::t2LDRi12: case ARM::t2LDRi8:
1502 case ARM::t2STRi12: case ARM::t2STRi8:
1503 case ARM::VLDRS: case ARM::VLDRD:
1504 case ARM::VSTRS: case ARM::VSTRD:
1505 case ARM::tSTRspi: case ARM::tLDRspi:
1506 if (ForceAllBaseRegAlloc)
1513 // Without a virtual base register, if the function has variable sized
1514 // objects, all fixed-size local references will be via the frame pointer,
1515 // Approximate the offset and see if it's legal for the instruction.
1516 // Note that the incoming offset is based on the SP value at function entry,
1517 // so it'll be negative.
1518 MachineFunction &MF = *MI->getParent()->getParent();
1519 MachineFrameInfo *MFI = MF.getFrameInfo();
1520 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1522 // Estimate an offset from the frame pointer.
1523 // Conservatively assume all callee-saved registers get pushed. R4-R6
1524 // will be earlier than the FP, so we ignore those.
1526 int64_t FPOffset = Offset - 8;
1527 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1528 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1530 // Estimate an offset from the stack pointer.
1531 // The incoming offset is relating to the SP at the start of the function,
1532 // but when we access the local it'll be relative to the SP after local
1533 // allocation, so adjust our SP-relative offset by that allocation size.
1535 Offset += MFI->getLocalFrameSize();
1536 // Assume that we'll have at least some spill slots allocated.
1537 // FIXME: This is a total SWAG number. We should run some statistics
1538 // and pick a real one.
1539 Offset += 128; // 128 bytes of spill slots
1541 // If there is a frame pointer, try using it.
1542 // The FP is only available if there is no dynamic realignment. We
1543 // don't know for sure yet whether we'll need that, so we guess based
1544 // on whether there are any local variables that would trigger it.
1545 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1547 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1548 if (isFrameOffsetLegal(MI, FPOffset))
1551 // If we can reference via the stack pointer, try that.
1552 // FIXME: This (and the code that resolves the references) can be improved
1553 // to only disallow SP relative references in the live range of
1554 // the VLA(s). In practice, it's unclear how much difference that
1555 // would make, but it may be worth doing.
1556 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1559 // The offset likely isn't legal, we want to allocate a virtual base register.
1563 /// materializeFrameBaseRegister - Insert defining instruction(s) for
1564 /// BaseReg to be a pointer to FrameIdx before insertion point I.
1565 void ARMBaseRegisterInfo::
1566 materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1567 int FrameIdx, int64_t Offset) const {
1568 ARMFunctionInfo *AFI =
1569 I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1570 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1571 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1573 MachineInstrBuilder MIB =
1574 BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1575 .addFrameIndex(FrameIdx).addImm(Offset);
1576 if (!AFI->isThumb1OnlyFunction())
1577 AddDefaultCC(AddDefaultPred(MIB));
1581 ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1582 unsigned BaseReg, int64_t Offset) const {
1583 MachineInstr &MI = *I;
1584 MachineBasicBlock &MBB = *MI.getParent();
1585 MachineFunction &MF = *MBB.getParent();
1586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1587 int Off = Offset; // ARM doesn't need the general 64-bit offsets
1590 assert(!AFI->isThumb1OnlyFunction() &&
1591 "This resolveFrameIndex does not support Thumb1!");
1593 while (!MI.getOperand(i).isFI()) {
1595 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1598 if (!AFI->isThumbFunction())
1599 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1601 assert(AFI->isThumb2Function());
1602 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1604 assert (Done && "Unable to resolve frame index!");
1607 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1608 int64_t Offset) const {
1609 const TargetInstrDesc &Desc = MI->getDesc();
1610 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1613 while (!MI->getOperand(i).isFI()) {
1615 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1618 // AddrMode4 and AddrMode6 cannot handle any offset.
1619 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1622 unsigned NumBits = 0;
1624 bool isSigned = true;
1626 case ARMII::AddrModeT2_i8:
1627 case ARMII::AddrModeT2_i12:
1628 // i8 supports only negative, and i12 supports only positive, so
1629 // based on Offset sign, consider the appropriate instruction
1638 case ARMII::AddrMode5:
1639 // VFP address mode.
1643 case ARMII::AddrMode2:
1646 case ARMII::AddrMode3:
1649 case ARMII::AddrModeT1_s:
1655 llvm_unreachable("Unsupported addressing mode!");
1659 Offset += getFrameIndexInstrOffset(MI, i);
1660 // Make sure the offset is encodable for instructions that scale the
1662 if ((Offset & (Scale-1)) != 0)
1665 if (isSigned && Offset < 0)
1668 unsigned Mask = (1 << NumBits) - 1;
1669 if ((unsigned)Offset <= Mask * Scale)
1676 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1677 int SPAdj, RegScavenger *RS) const {
1679 MachineInstr &MI = *II;
1680 MachineBasicBlock &MBB = *MI.getParent();
1681 MachineFunction &MF = *MBB.getParent();
1682 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1683 assert(!AFI->isThumb1OnlyFunction() &&
1684 "This eliminateFrameIndex does not support Thumb1!");
1686 while (!MI.getOperand(i).isFI()) {
1688 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1691 int FrameIndex = MI.getOperand(i).getIndex();
1694 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1696 // Special handling of dbg_value instructions.
1697 if (MI.isDebugValue()) {
1698 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1699 MI.getOperand(i+1).ChangeToImmediate(Offset);
1703 // Modify MI as necessary to handle as much of 'Offset' as possible
1705 if (!AFI->isThumbFunction())
1706 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1708 assert(AFI->isThumb2Function());
1709 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1714 // If we get here, the immediate doesn't fit into the instruction. We folded
1715 // as much as possible above, handle the rest, providing a register that is
1718 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1719 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1720 "This code isn't needed if offset already handled!");
1722 unsigned ScratchReg = 0;
1723 int PIdx = MI.findFirstPredOperandIdx();
1724 ARMCC::CondCodes Pred = (PIdx == -1)
1725 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1726 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1728 // Must be addrmode4/6.
1729 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1731 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1732 if (!AFI->isThumbFunction())
1733 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1734 Offset, Pred, PredReg, TII);
1736 assert(AFI->isThumb2Function());
1737 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1738 Offset, Pred, PredReg, TII);
1740 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1744 /// Move iterator past the next bunch of callee save load / store ops for
1745 /// the particular spill area (1: integer area 1, 2: integer area 2,
1746 /// 3: fp area, 0: don't care).
1747 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1748 MachineBasicBlock::iterator &MBBI,
1749 int Opc1, int Opc2, unsigned Area,
1750 const ARMSubtarget &STI) {
1751 while (MBBI != MBB.end() &&
1752 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1753 MBBI->getOperand(1).isFI()) {
1756 unsigned Category = 0;
1757 switch (MBBI->getOperand(0).getReg()) {
1758 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1762 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1763 Category = STI.isTargetDarwin() ? 2 : 1;
1765 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1766 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1773 if (Done || Category != Area)
1781 void ARMBaseRegisterInfo::
1782 emitPrologue(MachineFunction &MF) const {
1783 MachineBasicBlock &MBB = MF.front();
1784 MachineBasicBlock::iterator MBBI = MBB.begin();
1785 MachineFrameInfo *MFI = MF.getFrameInfo();
1786 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1787 assert(!AFI->isThumb1OnlyFunction() &&
1788 "This emitPrologue does not support Thumb1!");
1789 bool isARM = !AFI->isThumbFunction();
1790 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1791 unsigned NumBytes = MFI->getStackSize();
1792 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1793 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1795 // Determine the sizes of each callee-save spill areas and record which frame
1796 // belongs to which callee-save spill areas.
1797 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1798 int FramePtrSpillFI = 0;
1800 // Allocate the vararg register save area. This is not counted in NumBytes.
1802 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1804 if (!AFI->hasStackFrame()) {
1806 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1810 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1811 unsigned Reg = CSI[i].getReg();
1812 int FI = CSI[i].getFrameIdx();
1819 if (Reg == FramePtr)
1820 FramePtrSpillFI = FI;
1821 AFI->addGPRCalleeSavedArea1Frame(FI);
1828 if (Reg == FramePtr)
1829 FramePtrSpillFI = FI;
1830 if (STI.isTargetDarwin()) {
1831 AFI->addGPRCalleeSavedArea2Frame(FI);
1834 AFI->addGPRCalleeSavedArea1Frame(FI);
1839 AFI->addDPRCalleeSavedAreaFrame(FI);
1844 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1845 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1846 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1848 // Set FP to point to the stack slot that contains the previous FP.
1849 // For Darwin, FP is R7, which has now been stored in spill area 1.
1850 // Otherwise, if this is not Darwin, all the callee-saved registers go
1851 // into spill area 1, including the FP in R11. In either case, it is
1852 // now safe to emit this assignment.
1853 bool HasFP = hasFP(MF);
1855 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1856 MachineInstrBuilder MIB =
1857 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1858 .addFrameIndex(FramePtrSpillFI).addImm(0);
1859 AddDefaultCC(AddDefaultPred(MIB));
1862 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1863 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1865 // Build the new SUBri to adjust SP for FP callee-save spill area.
1866 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1867 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1869 // Determine starting offsets of spill areas.
1870 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1871 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1872 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1874 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1876 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1877 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1878 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1880 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1881 NumBytes = DPRCSOffset;
1883 // Adjust SP after all the callee-save spills.
1884 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1886 AFI->setShouldRestoreSPFromFP(true);
1889 if (STI.isTargetELF() && hasFP(MF)) {
1890 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1891 AFI->getFramePtrSpillOffset());
1892 AFI->setShouldRestoreSPFromFP(true);
1895 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1896 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1897 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1899 // If we need dynamic stack realignment, do it here. Be paranoid and make
1900 // sure if we also have VLAs, we have a base pointer for frame access.
1901 if (needsStackRealignment(MF)) {
1902 unsigned MaxAlign = MFI->getMaxAlignment();
1903 assert (!AFI->isThumb1OnlyFunction());
1904 if (!AFI->isThumbFunction()) {
1905 // Emit bic sp, sp, MaxAlign
1906 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1907 TII.get(ARM::BICri), ARM::SP)
1908 .addReg(ARM::SP, RegState::Kill)
1909 .addImm(MaxAlign-1)));
1911 // We cannot use sp as source/dest register here, thus we're emitting the
1912 // following sequence:
1914 // bic r4, r4, MaxAlign
1916 // FIXME: It will be better just to find spare register here.
1917 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1918 .addReg(ARM::SP, RegState::Kill);
1919 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1920 TII.get(ARM::t2BICri), ARM::R4)
1921 .addReg(ARM::R4, RegState::Kill)
1922 .addImm(MaxAlign-1)));
1923 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1924 .addReg(ARM::R4, RegState::Kill);
1927 AFI->setShouldRestoreSPFromFP(true);
1930 // If we need a base pointer, set it up here. It's whatever the value
1931 // of the stack pointer is at this point. Any variable size objects
1932 // will be allocated after this, so we can still use the base pointer
1933 // to reference locals.
1934 if (hasBasePointer(MF)) {
1936 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1938 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1940 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1944 // If the frame has variable sized objects then the epilogue must restore
1946 if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1947 AFI->setShouldRestoreSPFromFP(true);
1950 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1951 for (unsigned i = 0; CSRegs[i]; ++i)
1952 if (Reg == CSRegs[i])
1957 static bool isCSRestore(MachineInstr *MI,
1958 const ARMBaseInstrInfo &TII,
1959 const unsigned *CSRegs) {
1960 return ((MI->getOpcode() == (int)ARM::VLDRD ||
1961 MI->getOpcode() == (int)ARM::LDR ||
1962 MI->getOpcode() == (int)ARM::t2LDRi12) &&
1963 MI->getOperand(1).isFI() &&
1964 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1967 void ARMBaseRegisterInfo::
1968 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1969 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1970 assert(MBBI->getDesc().isReturn() &&
1971 "Can only insert epilog into returning blocks");
1972 unsigned RetOpcode = MBBI->getOpcode();
1973 DebugLoc dl = MBBI->getDebugLoc();
1974 MachineFrameInfo *MFI = MF.getFrameInfo();
1975 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1976 assert(!AFI->isThumb1OnlyFunction() &&
1977 "This emitEpilogue does not support Thumb1!");
1978 bool isARM = !AFI->isThumbFunction();
1980 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1981 int NumBytes = (int)MFI->getStackSize();
1983 if (!AFI->hasStackFrame()) {
1985 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1987 // Unwind MBBI to point to first LDR / VLDRD.
1988 const unsigned *CSRegs = getCalleeSavedRegs();
1989 if (MBBI != MBB.begin()) {
1992 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1993 if (!isCSRestore(MBBI, TII, CSRegs))
1997 // Move SP to start of FP callee save spill area.
1998 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1999 AFI->getGPRCalleeSavedArea2Size() +
2000 AFI->getDPRCalleeSavedAreaSize());
2002 // Reset SP based on frame pointer only if the stack frame extends beyond
2003 // frame pointer stack slot or target is ELF and the function has FP.
2004 if (AFI->shouldRestoreSPFromFP()) {
2005 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
2008 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
2011 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
2016 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
2017 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
2019 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
2022 } else if (NumBytes)
2023 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
2025 // Move SP to start of integer callee save spill area 2.
2026 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
2027 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
2029 // Move SP to start of integer callee save spill area 1.
2030 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
2031 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
2033 // Move SP to SP upon entry to the function.
2034 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
2035 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
2038 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
2039 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
2040 // Tail call return: adjust the stack pointer and jump to callee.
2041 MBBI = prior(MBB.end());
2042 MachineOperand &JumpTarget = MBBI->getOperand(0);
2044 // Jump to label or value in register.
2045 if (RetOpcode == ARM::TCRETURNdi) {
2046 BuildMI(MBB, MBBI, dl,
2047 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
2048 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
2049 JumpTarget.getTargetFlags());
2050 } else if (RetOpcode == ARM::TCRETURNdiND) {
2051 BuildMI(MBB, MBBI, dl,
2052 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
2053 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
2054 JumpTarget.getTargetFlags());
2055 } else if (RetOpcode == ARM::TCRETURNri) {
2056 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
2057 addReg(JumpTarget.getReg(), RegState::Kill);
2058 } else if (RetOpcode == ARM::TCRETURNriND) {
2059 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
2060 addReg(JumpTarget.getReg(), RegState::Kill);
2063 MachineInstr *NewMI = prior(MBBI);
2064 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
2065 NewMI->addOperand(MBBI->getOperand(i));
2067 // Delete the pseudo instruction TCRETURN.
2072 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
2075 #include "ARMGenRegisterInfo.inc"